[brcm63xx] some more fixes to the SPI controller driver
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / files / drivers / spi / bcm63xx_spi.c
1 /*
2 * Broadcom BCM63xx SPI controller support
3 *
4 * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the
18 * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
19 */
20
21 #include <linux/kernel.h>
22 #include <linux/init.h>
23 #include <linux/clk.h>
24 #include <linux/module.h>
25 #include <linux/platform_device.h>
26 #include <linux/delay.h>
27 #include <linux/interrupt.h>
28 #include <linux/spi/spi.h>
29 #include <linux/spi/spi_bitbang.h>
30 #include <linux/gpio.h>
31 #include <linux/completion.h>
32 #include <linux/err.h>
33
34 #include <bcm63xx_io.h>
35 #include <bcm63xx_regs.h>
36 #include <bcm63xx_dev_spi.h>
37
38 #define PFX KBUILD_MODNAME
39 #define DRV_VER "0.1.2"
40
41 struct bcm63xx_spi {
42 /* bitbang has to be first */
43 struct spi_bitbang bitbang;
44 struct completion done;
45
46 void __iomem *regs;
47 int irq;
48
49 /* Platform data */
50 u32 speed_hz;
51 unsigned fifo_size;
52
53 /* Data buffers */
54 const unsigned char *tx_ptr;
55 unsigned char *rx_ptr;
56 int remaining_bytes;
57
58 struct clk *clk;
59 struct resource *ioarea;
60 struct platform_device *pdev;
61 };
62
63 static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on)
64 {
65 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
66 u16 val;
67
68 val = bcm_spi_readw(bs->regs, SPI_CMD);
69 if (is_on == BITBANG_CS_INACTIVE)
70 val |= SPI_CMD_NOOP;
71 else if (is_on == BITBANG_CS_ACTIVE)
72 val |= (1 << spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
73
74 bcm_spi_writew(val, bs->regs, SPI_CMD);
75 }
76
77 static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
78 struct spi_transfer *t)
79 {
80 u8 bits_per_word;
81 u8 clk_cfg;
82 u32 hz;
83 unsigned int div;
84
85 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
86
87 bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
88 hz = (t) ? t->speed_hz : spi->max_speed_hz;
89 if (bits_per_word != 8) {
90 dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
91 __func__, bits_per_word);
92 return -EINVAL;
93 }
94
95 if (spi->chip_select > spi->master->num_chipselect) {
96 dev_err(&spi->dev, "%s, unsupported slave %d\n",
97 __func__, spi->chip_select);
98 return -EINVAL;
99 }
100
101 /* Check clock setting */
102 div = (bs->speed_hz / hz);
103 switch (div) {
104 case 2:
105 clk_cfg = SPI_CLK_25MHZ;
106 break;
107 case 4:
108 clk_cfg = SPI_CLK_12_50MHZ;
109 break;
110 case 8:
111 clk_cfg = SPI_CLK_6_250MHZ;
112 break;
113 case 16:
114 clk_cfg = SPI_CLK_3_125MHZ;
115 break;
116 case 32:
117 clk_cfg = SPI_CLK_1_563MHZ;
118 break;
119 case 128:
120 clk_cfg = SPI_CLK_0_781MHZ;
121 break;
122 case 64:
123 default:
124 /* Set to slowest mode for compatibility */
125 clk_cfg = SPI_CLK_0_781MHZ;
126 break;
127 }
128
129 bcm_spi_writeb(clk_cfg, bs->regs, SPI_CLK_CFG);
130 dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
131 div, hz, clk_cfg);
132
133 return 0;
134 }
135
136 /* the spi->mode bits understood by this driver: */
137 #define MODEBITS (SPI_CPOL | SPI_CPHA)
138
139 static int bcm63xx_spi_setup(struct spi_device *spi)
140 {
141 struct spi_bitbang *bitbang;
142 struct bcm63xx_spi *bs;
143 int retval;
144
145 bs = spi_master_get_devdata(spi->master);
146 bitbang = &bs->bitbang;
147
148 if (!spi->bits_per_word)
149 spi->bits_per_word = 8;
150
151 if (spi->mode & ~MODEBITS) {
152 dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
153 __func__, spi->mode & ~MODEBITS);
154 return -EINVAL;
155 }
156
157 retval = bcm63xx_spi_setup_transfer(spi, NULL);
158 if (retval < 0) {
159 dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
160 spi->mode & ~MODEBITS);
161 return retval;
162 }
163
164 dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
165 __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
166
167 return 0;
168 }
169
170 /* Fill the TX FIFO with as many bytes as possible */
171 static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
172 {
173 u8 tail;
174
175 /* Fill the Tx FIFO with as many bytes as possible */
176 tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
177 while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
178 if (bs->tx_ptr)
179 bcm_spi_writeb(*bs->tx_ptr++, bs->regs, SPI_MSG_DATA);
180 else
181 bcm_spi_writeb(0, bs->regs, SPI_MSG_DATA);
182 bs->remaining_bytes--;
183 tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
184 }
185 }
186
187 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
188 {
189 struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
190 u8 msg_ctl;
191 u16 cmd;
192
193 dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
194 t->tx_buf, t->rx_buf, t->len);
195
196 /* Transmitter is inhibited */
197 bs->tx_ptr = t->tx_buf;
198 bs->rx_ptr = t->rx_buf;
199 bs->remaining_bytes = t->len;
200 init_completion(&bs->done);
201
202 bcm63xx_spi_fill_tx_fifo(bs);
203
204 /* Enable the command done interrupt which
205 * we use to determine completion of a command */
206 bcm_spi_writeb(SPI_INTR_CMD_DONE, bs->regs, SPI_INT_MASK);
207
208 /* Fill in the Message control register */
209 msg_ctl = bcm_spi_readb(bs->regs, SPI_MSG_CTL);
210 msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT);
211 msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
212 bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL);
213
214 /* Issue the transfer */
215 cmd = bcm_spi_readb(bs->regs, SPI_CMD);
216 cmd |= SPI_CMD_START_IMMEDIATE;
217 cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
218 bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
219
220 wait_for_completion(&bs->done);
221
222 /* Disable the CMD_DONE interrupt */
223 bcm_spi_writeb(~(SPI_INTR_CMD_DONE), bs->regs, SPI_INT_MASK);
224
225 return t->len - bs->remaining_bytes;
226 }
227
228 /* This driver supports single master mode only. Hence
229 * CMD_DONE is the only interrupt we care about
230 */
231 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
232 {
233 struct spi_master *master = (struct spi_master *)dev_id;
234 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
235 u8 intr;
236 u16 cmd;
237
238 /* Read interupts and clear them immediately */
239 intr = bcm_spi_readb(bs->regs, SPI_INT_STATUS);
240 bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_STATUS);
241
242 /* A tansfer completed */
243 if (intr & SPI_INTR_CMD_DONE) {
244 u8 rx_empty;
245
246 rx_empty = bcm_spi_readb(bs->regs, SPI_ST);
247 /* Read out all the data */
248 while ((rx_empty & SPI_RX_EMPTY) == 0) {
249 u8 data;
250
251 data = bcm_spi_readb(bs->regs, SPI_RX_DATA);
252 if (bs->rx_ptr)
253 *bs->rx_ptr++ = data;
254
255 rx_empty = bcm_spi_readb(bs->regs, SPI_RX_EMPTY);
256 }
257
258 /* See if there is more data to send */
259 if (bs->remaining_bytes > 0) {
260 bcm63xx_spi_fill_tx_fifo(bs);
261
262 /* Start the transfer */
263 cmd = bcm_spi_readb(bs->regs, SPI_CMD);
264 cmd |= SPI_CMD_START_IMMEDIATE;
265 cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
266 bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
267 } else
268 complete(&bs->done);
269 }
270
271 return IRQ_HANDLED;
272 }
273
274
275 static int __init bcm63xx_spi_probe(struct platform_device *pdev)
276 {
277 struct resource *r;
278 struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
279 int irq;
280 struct spi_master *master;
281 struct clk *clk;
282 struct bcm63xx_spi *bs;
283 int ret;
284
285 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
286 if (!r) {
287 ret = -ENXIO;
288 goto out;
289 }
290
291 irq = platform_get_irq(pdev, 0);
292 if (irq < 0) {
293 ret = -ENXIO;
294 goto out;
295 }
296
297 clk = clk_get(&pdev->dev, "spi");
298 if (IS_ERR(clk)) {
299 dev_err(&pdev->dev, "No clock for device\n");
300 ret = -ENODEV;
301 goto out;
302 }
303
304 master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi));
305 if (!master) {
306 ret = -ENOMEM;
307 goto out_free;
308 }
309
310 bs = spi_master_get_devdata(master);
311 bs->bitbang.master = spi_master_get(master);
312 bs->bitbang.chipselect = bcm63xx_spi_chipselect;
313 bs->bitbang.setup_transfer = bcm63xx_spi_setup_transfer;
314 bs->bitbang.txrx_bufs = bcm63xx_txrx_bufs;
315 bs->bitbang.master->setup = bcm63xx_spi_setup;
316 init_completion(&bs->done);
317
318 platform_set_drvdata(pdev, master);
319 bs->pdev = pdev;
320
321 if (!request_mem_region(r->start,
322 r->end - r->start, PFX)) {
323 ret = -ENXIO;
324 goto out_free;
325 }
326
327 bs->regs = ioremap_nocache(r->start, r->end - r->start);
328 if (!bs->regs) {
329 printk(KERN_ERR PFX " unable to ioremap regs\n");
330 ret = -ENOMEM;
331 goto out_free;
332 }
333 bs->irq = irq;
334 bs->clk = clk;
335 bs->fifo_size = pdata->fifo_size;
336
337 ret = request_irq(irq, bcm63xx_spi_interrupt, 0,
338 pdev->dev.bus_id, master);
339 if (ret) {
340 printk(KERN_ERR PFX " unable to request irq\n");
341 goto out_unmap;
342 }
343
344 master->bus_num = pdata->bus_num;
345 master->num_chipselect = pdata->num_chipselect;
346 bs->speed_hz = pdata->speed_hz;
347
348 /* Initialize hardware */
349 clk_enable(bs->clk);
350 bcm_spi_writew(SPI_CMD_HARD_RESET, bs->regs, SPI_CMD);
351 bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
352
353 dev_info(&pdev->dev, PFX " at 0x%08x (irq %d, FIFOs size %d) v%s\n",
354 r->start, irq, bs->fifo_size, DRV_VER);
355
356 ret = spi_bitbang_start(&bs->bitbang);
357 if (ret) {
358 dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
359 goto out_reset_hw;
360 }
361
362 return ret;
363
364 out_reset_hw:
365 clk_disable(clk);
366 free_irq(irq, master);
367 out_unmap:
368 iounmap(bs->regs);
369 out_free:
370 clk_put(clk);
371 spi_master_put(master);
372 out:
373 return ret;
374 }
375
376 static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
377 {
378 struct spi_master *master = platform_get_drvdata(pdev);
379 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
380
381 spi_bitbang_stop(&bs->bitbang);
382 clk_disable(bs->clk);
383 clk_put(bs->clk);
384 free_irq(bs->irq, master);
385 iounmap(bs->regs);
386 platform_set_drvdata(pdev, 0);
387 spi_master_put(bs->bitbang.master);
388
389 return 0;
390 }
391
392 #ifdef CONFIG_PM
393 static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
394 {
395 struct spi_master *master = platform_get_drvdata(pdev);
396 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
397
398 clk_disable(bs->clk);
399
400 return 0;
401 }
402
403 static int bcm63xx_spi_resume(struct platform_device *pdev)
404 {
405 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
406 struct bcm63xx_spi *bs = spi_master_get_devdata(master);
407
408 clk_enable(bs->clk);
409
410 return 0;
411 }
412 #else
413 #define bcm63xx_spi_suspend NULL
414 #define bcm63xx_spi_resume NULL
415 #endif
416
417 static struct platform_driver bcm63xx_spi_driver = {
418 .driver = {
419 .name = "bcm63xx-spi",
420 .owner = THIS_MODULE,
421 },
422 .probe = bcm63xx_spi_probe,
423 .remove = bcm63xx_spi_remove,
424 .suspend = bcm63xx_spi_suspend,
425 .resume = bcm63xx_spi_resume,
426 };
427
428
429 static int __init bcm63xx_spi_init(void)
430 {
431 return platform_driver_register(&bcm63xx_spi_driver);
432 }
433
434 static void __exit bcm63xx_spi_exit(void)
435 {
436 platform_driver_unregister(&bcm63xx_spi_driver);
437 }
438
439 module_init(bcm63xx_spi_init);
440 module_exit(bcm63xx_spi_exit);
441
442 MODULE_ALIAS("platform:bcm63xx_spi");
443 MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
444 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
445 MODULE_LICENSE("GPL");
446 MODULE_VERSION(DRV_VER);