[brcm63xx] define bcm6338 SDRAM base register and make sure that the right CPU id...
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_cpu.h
1 #ifndef BCM63XX_CPU_H_
2 #define BCM63XX_CPU_H_
3
4 #include <linux/types.h>
5 #include <linux/init.h>
6
7 #include <bcm63xx_regs.h>
8
9 /*
10 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
11 * compile time if only one CPU support is enabled (idea stolen from
12 * arm mach-types)
13 */
14 #define BCM6338_CPU_ID 0x6338
15 #define BCM6345_CPU_ID 0x6345
16 #define BCM6348_CPU_ID 0x6348
17 #define BCM6358_CPU_ID 0x6358
18
19 void __init bcm63xx_cpu_init(void);
20 u16 __bcm63xx_get_cpu_id(void);
21 u16 bcm63xx_get_cpu_rev(void);
22 unsigned int bcm63xx_get_cpu_freq(void);
23
24 #ifdef CONFIG_BCM63XX_CPU_6338
25 # ifdef bcm63xx_get_cpu_id
26 # undef bcm63xx_get_cpu_id
27 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
28 # define BCMCPU_RUNTIME_DETECT
29 # else
30 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID
31 # endif
32 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
33 #else
34 # define BCMCPU_IS_6338() (0)
35 #endif
36
37 #ifdef CONFIG_BCM63XX_CPU_6345
38 # ifdef bcm63xx_get_cpu_id
39 # undef bcm63xx_get_cpu_id
40 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
41 # define BCMCPU_RUNTIME_DETECT
42 # else
43 # define bcm63xx_get_cpu_id() BCM6345_CPU_ID
44 # endif
45 # define BCMCPU_IS_6345() (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
46 #else
47 # define BCMCPU_IS_6345() (0)
48 #endif
49
50 #ifdef CONFIG_BCM63XX_CPU_6348
51 # ifdef bcm63xx_get_cpu_id
52 # undef bcm63xx_get_cpu_id
53 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
54 # define BCMCPU_RUNTIME_DETECT
55 # else
56 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
57 # endif
58 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
59 #else
60 # define BCMCPU_IS_6348() (0)
61 #endif
62
63 #ifdef CONFIG_BCM63XX_CPU_6358
64 # ifdef bcm63xx_get_cpu_id
65 # undef bcm63xx_get_cpu_id
66 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
67 # define BCMCPU_RUNTIME_DETECT
68 # else
69 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
70 # endif
71 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
72 #else
73 # define BCMCPU_IS_6358() (0)
74 #endif
75
76 #ifndef bcm63xx_get_cpu_id
77 #error "No CPU support configured"
78 #endif
79
80 /*
81 * While registers sets are (mostly) the same across 63xx CPU, base
82 * address of these sets do change.
83 */
84 enum bcm63xx_regs_set {
85 RSET_DSL_LMEM = 0,
86 RSET_PERF,
87 RSET_TIMER,
88 RSET_WDT,
89 RSET_UART0,
90 RSET_GPIO,
91 RSET_SPI,
92 RSET_UDC0,
93 RSET_OHCI0,
94 RSET_OHCI_PRIV,
95 RSET_USBH_PRIV,
96 RSET_MPI,
97 RSET_PCMCIA,
98 RSET_DSL,
99 RSET_ENET0,
100 RSET_ENET1,
101 RSET_ENETDMA,
102 RSET_EHCI0,
103 RSET_SDRAM,
104 RSET_MEMC,
105 RSET_DDR,
106 };
107
108 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
109 #define RSET_DSL_SIZE 4096
110 #define RSET_WDT_SIZE 12
111 #define RSET_ENET_SIZE 2048
112 #define RSET_ENETDMA_SIZE 2048
113 #define RSET_UART_SIZE 24
114 #define RSET_SPI_SIZE 256
115 #define RSET_UDC_SIZE 256
116 #define RSET_OHCI_SIZE 256
117 #define RSET_EHCI_SIZE 256
118 #define RSET_PCMCIA_SIZE 12
119
120 /*
121 * 6338 register sets base address
122 */
123
124 #define BCM_6338_PERF_BASE (0xfffe0000)
125 #define BCM_6338_BB_BASE (0xfffe0100) /* bus bridge registers */
126 #define BCM_6338_TIMER_BASE (0xfffe0200)
127 #define BCM_6338_WDT_BASE (0xfffe021c)
128 #define BCM_6338_UART0_BASE (0xfffe0300)
129 #define BCM_6338_GPIO_BASE (0xfffe0400)
130 #define BCM_6338_SPI_BASE (0xfffe0c00)
131 #define BCM_6338_DSL_BASE (0xfffe1000)
132 #define BCM_6338_SAR_BASE (0xfffe2000)
133 #define BCM_6338_ENETDMA_BASE (0xfffe2400)
134 #define BCM_6338_USBDMA_BASE (0xfffe2400)
135 #define BCM_6338_ENET0_BASE (0xfffe2800)
136 #define BCM_6338_UDC0_BASE (0xfffe3000) /* USB_CTL_BASE */
137 #define BCM_6338_SDRAM_REGS_BASE (0xfffe3100)
138 #define BCM_6338_SDRAM_BASE (0xfffe3100)
139 #define BCM_6338_MEMC_BASE (0xdeadbeef)
140
141 /*
142 * 6345 register sets base address
143 */
144 #define BCM_6345_PERF_BASE (0xfffe0000)
145 #define BCM_6345_TIMER_BASE (0xfffe0200)
146 #define BCM_6345_WDT_BASE (0xfffe021c)
147 #define BCM_6345_UART0_BASE (0xfffe0300)
148 #define BCM_6345_GPIO_BASE (0xfffe0400)
149
150 /*
151 * 6348 register sets base address
152 */
153 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
154 #define BCM_6348_PERF_BASE (0xfffe0000)
155 #define BCM_6348_BB_BASE (0xfffe0100) /* bus bridge registers */
156 #define BCM_6348_TIMER_BASE (0xfffe0200)
157 #define BCM_6348_WDT_BASE (0xfffe021c)
158 #define BCM_6348_UART0_BASE (0xfffe0300)
159 #define BCM_6348_GPIO_BASE (0xfffe0400)
160 #define BCM_6348_SPI_BASE (0xfffe0c00)
161 #define BCM_6348_UDC0_BASE (0xfffe1000)
162 #define BCM_6348_USBDMA_BASE (0xfffe1400)
163 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
164 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
165 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
166 #define BCM_6348_MPI_BASE (0xfffe2000)
167 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
168 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
169 #define BCM_6348_DSL_BASE (0xfffe3000)
170 #define BCM_6348_SAR_BASE (0xfffe4000)
171 #define BCM_6348_UBUS_BASE (0xfffe5000)
172 #define BCM_6348_ENET0_BASE (0xfffe6000)
173 #define BCM_6348_ENET1_BASE (0xfffe6800)
174 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
175 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
176 #define BCM_6348_SDRAM_BASE (0xfffe2300)
177 #define BCM_6348_MEMC_BASE (0xdeadbeef)
178 #define BCM_6348_DDR_BASE (0xdeadbeef)
179
180 /*
181 * 6358 register sets base address
182 */
183 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
184 #define BCM_6358_PERF_BASE (0xfffe0000)
185 #define BCM_6358_TIMER_BASE (0xfffe0040)
186 #define BCM_6358_WDT_BASE (0xfffe005c)
187 #define BCM_6358_GPIO_BASE (0xfffe0080)
188 #define BCM_6358_UART0_BASE (0xfffe0100)
189 #define BCM_6358_UDC0_BASE (0xfffe0400)
190 #define BCM_6358_SPI_BASE (0xfffe0800)
191 #define BCM_6358_MPI_BASE (0xfffe1000)
192 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
193 #define BCM_6358_OHCI0_BASE (0xfffe1400)
194 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
195 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
196 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
197 #define BCM_6358_DSL_BASE (0xfffe3000)
198 #define BCM_6358_ENET0_BASE (0xfffe4000)
199 #define BCM_6358_ENET1_BASE (0xfffe4800)
200 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
201 #define BCM_6358_EHCI0_BASE (0xfffe1300)
202 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
203 #define BCM_6358_MEMC_BASE (0xfffe1200)
204 #define BCM_6358_DDR_BASE (0xfffe12a0)
205
206
207 extern const unsigned long *bcm63xx_regs_base;
208
209 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
210 {
211 #ifdef BCMCPU_RUNTIME_DETECT
212 return bcm63xx_regs_base[set];
213 #else
214 #ifdef CONFIG_BCM63XX_CPU_6338
215 switch (set) {
216 case RSET_PERF:
217 return BCM_6338_PERF_BASE;
218 case RSET_TIMER:
219 return BCM_6338_TIMER_BASE;
220 case RSET_WDT:
221 return BCM_6338_WDT_BASE;
222 case RSET_UART0:
223 return BCM_6338_UART0_BASE;
224 case RSET_GPIO:
225 return BCM_6338_GPIO_BASE;
226 case RSET_SPI:
227 return BCM_6338_SPI_BASE;
228 case RSET_MEMC:
229 return BCM_6338_MEMC_BASE;
230 case RSET_SDRAM:
231 return BCM_6338_SDRAM_BASE;
232 }
233 #endif
234 #ifdef CONFIG_BCM63XX_CPU_6345
235 switch (set) {
236 case RSET_PERF:
237 return BCM_6345_PERF_BASE;
238 case RSET_TIMER:
239 return BCM_6345_TIMER_BASE;
240 case RSET_WDT:
241 return BCM_6345_WDT_BASE;
242 case RSET_UART0:
243 return BCM_6345_UART0_BASE;
244 case RSET_GPIO:
245 return BCM_6345_GPIO_BASE;
246 }
247 #endif
248 #ifdef CONFIG_BCM63XX_CPU_6348
249 switch (set) {
250 case RSET_DSL_LMEM:
251 return BCM_6348_DSL_LMEM_BASE;
252 case RSET_PERF:
253 return BCM_6348_PERF_BASE;
254 case RSET_TIMER:
255 return BCM_6348_TIMER_BASE;
256 case RSET_WDT:
257 return BCM_6348_WDT_BASE;
258 case RSET_UART0:
259 return BCM_6348_UART0_BASE;
260 case RSET_GPIO:
261 return BCM_6348_GPIO_BASE;
262 case RSET_SPI:
263 return BCM_6348_SPI_BASE;
264 case RSET_UDC0:
265 return BCM_6348_UDC0_BASE;
266 case RSET_OHCI0:
267 return BCM_6348_OHCI0_BASE;
268 case RSET_OHCI_PRIV:
269 return BCM_6348_OHCI_PRIV_BASE;
270 case RSET_USBH_PRIV:
271 return BCM_6348_USBH_PRIV_BASE;
272 case RSET_MPI:
273 return BCM_6348_MPI_BASE;
274 case RSET_PCMCIA:
275 return BCM_6348_PCMCIA_BASE;
276 case RSET_DSL:
277 return BCM_6348_DSL_BASE;
278 case RSET_ENET0:
279 return BCM_6348_ENET0_BASE;
280 case RSET_ENET1:
281 return BCM_6348_ENET1_BASE;
282 case RSET_ENETDMA:
283 return BCM_6348_ENETDMA_BASE;
284 case RSET_EHCI0:
285 return BCM_6348_EHCI0_BASE;
286 case RSET_SDRAM:
287 return BCM_6348_SDRAM_BASE;
288 case RSET_MEMC:
289 return BCM_6348_MEMC_BASE;
290 case RSET_DDR:
291 return BCM_6348_DDR_BASE;
292 }
293 #endif
294 #ifdef CONFIG_BCM63XX_CPU_6358
295 switch (set) {
296 case RSET_DSL_LMEM:
297 return BCM_6358_DSL_LMEM_BASE;
298 case RSET_PERF:
299 return BCM_6358_PERF_BASE;
300 case RSET_TIMER:
301 return BCM_6358_TIMER_BASE;
302 case RSET_WDT:
303 return BCM_6358_WDT_BASE;
304 case RSET_UART0:
305 return BCM_6358_UART0_BASE;
306 case RSET_GPIO:
307 return BCM_6358_GPIO_BASE;
308 case RSET_SPI:
309 return BCM_6358_SPI_BASE;
310 case RSET_UDC0:
311 return BCM_6358_UDC0_BASE;
312 case RSET_OHCI0:
313 return BCM_6358_OHCI0_BASE;
314 case RSET_OHCI_PRIV:
315 return BCM_6358_OHCI_PRIV_BASE;
316 case RSET_USBH_PRIV:
317 return BCM_6358_USBH_PRIV_BASE;
318 case RSET_MPI:
319 return BCM_6358_MPI_BASE;
320 case RSET_PCMCIA:
321 return BCM_6358_PCMCIA_BASE;
322 case RSET_ENET0:
323 return BCM_6358_ENET0_BASE;
324 case RSET_ENET1:
325 return BCM_6358_ENET1_BASE;
326 case RSET_ENETDMA:
327 return BCM_6358_ENETDMA_BASE;
328 case RSET_DSL:
329 return BCM_6358_DSL_BASE;
330 case RSET_EHCI0:
331 return BCM_6358_EHCI0_BASE;
332 case RSET_SDRAM:
333 return BCM_6358_SDRAM_BASE;
334 case RSET_MEMC:
335 return BCM_6358_MEMC_BASE;
336 case RSET_DDR:
337 return BCM_6358_DDR_BASE;
338 }
339 #endif
340 #endif
341 /* unreached */
342 return 0;
343 }
344
345 /*
346 * SPI register layout is not compatible
347 * accross CPU versions but it is software
348 * compatible
349 */
350
351 enum bcm63xx_regs_spi {
352 SPI_CMD,
353 SPI_INT_STATUS,
354 SPI_INT_MASK_ST,
355 SPI_INT_MASK,
356 SPI_ST,
357 SPI_CLK_CFG,
358 SPI_FILL_BYTE,
359 SPI_MSG_TAIL,
360 SPI_RX_TAIL,
361 SPI_MSG_CTL,
362 SPI_MSG_DATA,
363 SPI_RX_DATA,
364 };
365
366 extern const unsigned long *bcm63xx_regs_spi;
367
368 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
369 {
370 #ifdef BCMCPU_RUNTIME_DETECT
371 return bcm63xx_regs_spi[reg];
372 #else
373 #ifdef CONFIG_BCM63XX_CPU_6338
374 switch (reg) {
375 case SPI_CMD:
376 return SPI_BCM_6338_SPI_CMD;
377 case SPI_INT_STATUS:
378 return SPI_BCM_6338_SPI_INT_STATUS;
379 case SPI_INT_MASK_ST:
380 return SPI_BCM_6338_SPI_MASK_INT_ST;
381 case SPI_INT_MASK:
382 return SPI_BCM_6338_SPI_INT_MASK;
383 case SPI_ST:
384 return SPI_BCM_6338_SPI_ST;
385 case SPI_CLK_CFG:
386 return SPI_BCM_6338_SPI_CLK_CFG;
387 case SPI_FILL_BYTE:
388 return SPI_BCM_6338_SPI_FILL_BYTE;
389 case SPI_MSG_TAIL:
390 return SPI_BCM_6338_SPI_MSG_TAIL;
391 case SPI_RX_TAIL:
392 return SPI_BCM_6338_SPI_RX_TAIL;
393 case SPI_MSG_CTL:
394 return SPI_BCM_6338_SPI_MSG_CTL;
395 case SPI_MSG_DATA:
396 return SPI_BCM_6338_SPI_MSG_DATA;
397 case SPI_RX_DATA:
398 return SPI_BCM_6338_SPI_RX_DATA;
399 }
400 #endif
401 #ifdef CONFIG_BCM63XX_CPU_6348
402 switch (reg) {
403 case SPI_CMD:
404 return SPI_BCM_6348_SPI_CMD;
405 case SPI_INT_MASK_ST:
406 return SPI_BCM_6348_SPI_MASK_INT_ST;
407 case SPI_INT_MASK:
408 return SPI_BCM_6348_SPI_INT_MASK;
409 case SPI_INT_STATUS:
410 return SPI_BCM_6348_SPI_INT_STATUS;
411 case SPI_ST:
412 return SPI_BCM_6348_SPI_ST;
413 case SPI_CLK_CFG:
414 return SPI_BCM_6348_SPI_CLK_CFG;
415 case SPI_FILL_BYTE:
416 return SPI_BCM_6348_SPI_FILL_BYTE;
417 case SPI_MSG_TAIL:
418 return SPI_BCM_6348_SPI_MSG_TAIL;
419 case SPI_RX_TAIL:
420 return SPI_BCM_6348_SPI_RX_TAIL;
421 case SPI_MSG_CTL:
422 return SPI_BCM_6348_SPI_MSG_CTL;
423 case SPI_MSG_DATA:
424 return SPI_BCM_6348_SPI_MSG_DATA;
425 case SPI_RX_DATA:
426 return SPI_BCM_6348_SPI_RX_DATA;
427 }
428 #endif
429 #ifdef CONFIG_BCM63XX_CPU_6358
430 switch (reg) {
431 case SPI_CMD:
432 return SPI_BCM_6358_SPI_CMD;
433 case SPI_INT_STATUS:
434 return SPI_BCM_6358_SPI_INT_STATUS;
435 case SPI_INT_MASK_ST:
436 return SPI_BCM_6358_SPI_MASK_INT_ST;
437 case SPI_INT_MASK:
438 return SPI_BCM_6358_SPI_INT_MASK;
439 case SPI_ST:
440 return SPI_BCM_6358_SPI_STATUS;
441 case SPI_CLK_CFG:
442 return SPI_BCM_6358_SPI_CLK_CFG;
443 case SPI_FILL_BYTE:
444 return SPI_BCM_6358_SPI_FILL_BYTE;
445 case SPI_MSG_TAIL:
446 return SPI_BCM_6358_SPI_MSG_TAIL;
447 case SPI_RX_TAIL:
448 return SPI_BCM_6358_SPI_RX_TAIL;
449 case SPI_MSG_CTL:
450 return SPI_BCM_6358_MSG_CTL;
451 case SPI_MSG_DATA:
452 return SPI_BCM_6358_SPI_MSG_DATA;
453 case SPI_RX_DATA:
454 return SPI_BCM_6358_SPI_RX_DATA;
455 }
456 #endif
457 #endif
458 return 0;
459 }
460
461 /*
462 * IRQ number changes across CPU too
463 */
464 enum bcm63xx_irq {
465 IRQ_TIMER = 0,
466 IRQ_UART0,
467 IRQ_SPI,
468 IRQ_DSL,
469 IRQ_UDC0,
470 IRQ_ENET0,
471 IRQ_ENET1,
472 IRQ_ENET_PHY,
473 IRQ_OHCI0,
474 IRQ_EHCI0,
475 IRQ_PCMCIA0,
476 IRQ_ENET0_RXDMA,
477 IRQ_ENET0_TXDMA,
478 IRQ_ENET1_RXDMA,
479 IRQ_ENET1_TXDMA,
480 IRQ_PCI,
481 IRQ_PCMCIA,
482 };
483
484 /*
485 * 6338 irqs
486 */
487 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
488 #define BCM_6338_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
489 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
490 #define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
491 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
492 #define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
493 #define BCM_6338_UDC0_IRQ (IRQ_INTERNAL_BASE + 7)
494 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
495 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
496 #define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
497 #define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
498 #define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
499 #define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
500 #define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
501 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
502 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
503 #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
504
505 /*
506 * 6345 irqs
507 */
508 #define BCM_6345_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
509 #define BCM_6345_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
510 #define BCM_6345_DSL_IRQ (IRQ_INTERNAL_BASE + 3)
511 #define BCM_6345_ATM_IRQ (IRQ_INTERNAL_BASE + 4)
512 #define BCM_6345_USB_IRQ (IRQ_INTERNAL_BASE + 5)
513 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
514 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
515
516 /*
517 * 6348 irqs
518 */
519 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
520 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
521 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
522 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
523 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
524 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
525 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
526 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
527 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
528 #define BCM_6348_USB_CNTL_RX_DMA (IRQ_INTERNAL_BASE + 14)
529 #define BCM_6348_USB_CNTL_TX_DMA (IRQ_INTERNAL_BASE + 15)
530 #define BCM_6348_USB_BULK_RX_DMA (IRQ_INTERNAL_BASE + 16)
531 #define BCM_6348_USB_BULK_TX_DMA (IRQ_INTERNAL_BASE + 17)
532 #define BCM_6348_USB_ISO_RX_DMA (IRQ_INTERNAL_BASE + 18)
533 #define BCM_6348_USB_ISO_TX_DMA (IRQ_INTERNAL_BASE + 19)
534 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
535 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
536 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
537 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
538 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
539 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
540
541 /*
542 * 6358 irqs
543 */
544 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
545 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
546 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
547 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
548 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
549 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
550 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
551 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
552 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
553 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
554 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
555 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
556 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
557 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
558 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
559
560 extern const int *bcm63xx_irqs;
561
562 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
563 {
564 return bcm63xx_irqs[irq];
565 }
566
567 /*
568 * return installed memory size
569 */
570 unsigned int bcm63xx_get_memory_size(void);
571
572 #endif /* !BCM63XX_CPU_H_ */