[brcm63xx] fix register definitions for bcm6358, thanks SGDA
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_cpu.h
1 #ifndef BCM63XX_CPU_H_
2 #define BCM63XX_CPU_H_
3
4 #include <linux/types.h>
5 #include <linux/init.h>
6
7 /*
8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types)
11 */
12 #define BCM6348_CPU_ID 0x6348
13 #define BCM6358_CPU_ID 0x6358
14
15 void __init bcm63xx_cpu_init(void);
16 u16 __bcm63xx_get_cpu_id(void);
17 u16 bcm63xx_get_cpu_rev(void);
18 unsigned int bcm63xx_get_cpu_freq(void);
19
20 #ifdef CONFIG_BCM63XX_CPU_6348
21 # ifdef bcm63xx_get_cpu_id
22 # undef bcm63xx_get_cpu_id
23 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
24 # define BCMCPU_RUNTIME_DETECT
25 # else
26 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
27 # endif
28 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
29 #else
30 # define BCMCPU_IS_6348() (0)
31 #endif
32
33 #ifdef CONFIG_BCM63XX_CPU_6358
34 # ifdef bcm63xx_get_cpu_id
35 # undef bcm63xx_get_cpu_id
36 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
37 # define BCMCPU_RUNTIME_DETECT
38 # else
39 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
40 # endif
41 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
42 #else
43 # define BCMCPU_IS_6358() (0)
44 #endif
45
46 #ifndef bcm63xx_get_cpu_id
47 #error "No CPU support configured"
48 #endif
49
50 /*
51 * While registers sets are (mostly) the same across 63xx CPU, base
52 * address of these sets do change.
53 */
54 enum bcm63xx_regs_set {
55 RSET_DSL_LMEM = 0,
56 RSET_PERF,
57 RSET_TIMER,
58 RSET_WDT,
59 RSET_UART0,
60 RSET_GPIO,
61 RSET_SPI,
62 RSET_UDC0,
63 RSET_OHCI0,
64 RSET_OHCI_PRIV,
65 RSET_USBH_PRIV,
66 RSET_MPI,
67 RSET_PCMCIA,
68 RSET_DSL,
69 RSET_ENET0,
70 RSET_ENET1,
71 RSET_ENETDMA,
72 RSET_EHCI0,
73 RSET_SDRAM,
74 RSET_MEMC,
75 RSET_DDR,
76 };
77
78 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
79 #define RSET_DSL_SIZE 4096
80 #define RSET_WDT_SIZE 12
81 #define RSET_ENET_SIZE 2048
82 #define RSET_ENETDMA_SIZE 2048
83 #define RSET_UART_SIZE 24
84 #define RSET_SPI_SIZE 2048
85 #define RSET_UDC_SIZE 256
86 #define RSET_OHCI_SIZE 256
87 #define RSET_EHCI_SIZE 256
88 #define RSET_PCMCIA_SIZE 12
89
90 /*
91 * 6348 register sets base address
92 */
93 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
94 #define BCM_6348_PERF_BASE (0xfffe0000)
95 #define BCM_6348_TIMER_BASE (0xfffe0200)
96 #define BCM_6348_WDT_BASE (0xfffe021c)
97 #define BCM_6348_UART0_BASE (0xfffe0300)
98 #define BCM_6348_GPIO_BASE (0xfffe0400)
99 #define BCM_6348_SPI_BASE (0xfffe0c00)
100 #define BCM_6348_UDC0_BASE (0xfffe1000)
101 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
102 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
103 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
104 #define BCM_6348_MPI_BASE (0xfffe2000)
105 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
106 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
107 #define BCM_6348_DSL_BASE (0xfffe3000)
108 #define BCM_6348_ENET0_BASE (0xfffe6000)
109 #define BCM_6348_ENET1_BASE (0xfffe6800)
110 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
111 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
112 #define BCM_6348_SDRAM_BASE (0xfffe2300)
113 #define BCM_6348_MEMC_BASE (0xdeadbeef)
114 #define BCM_6348_DDR_BASE (0xdeadbeef)
115
116 /*
117 * 6358 register sets base address
118 */
119 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
120 #define BCM_6358_PERF_BASE (0xfffe0000)
121 #define BCM_6358_TIMER_BASE (0xfffe0040)
122 #define BCM_6358_WDT_BASE (0xfffe005c)
123 #define BCM_6358_GPIO_BASE (0xfffe0080)
124 #define BCM_6358_UART0_BASE (0xfffe0100)
125 #define BCM_6358_UDC0_BASE (0xfffe0400)
126 #define BCM_6358_SPI_BASE (0xfffe0800)
127 #define BCM_6358_MPI_BASE (0xfffe1000)
128 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
129 #define BCM_6358_OHCI0_BASE (0xfffe1400)
130 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
131 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
132 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
133 #define BCM_6358_DSL_BASE (0xfffe3000)
134 #define BCM_6358_ENET0_BASE (0xfffe4000)
135 #define BCM_6358_ENET1_BASE (0xfffe4800)
136 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
137 #define BCM_6358_EHCI0_BASE (0xfffe1300)
138 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
139 #define BCM_6358_MEMC_BASE (0xfffe1200)
140 #define BCM_6358_DDR_BASE (0xfffe12a0)
141
142
143 extern const unsigned long *bcm63xx_regs_base;
144
145 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
146 {
147 #ifdef BCMCPU_RUNTIME_DETECT
148 return bcm63xx_regs_base[set];
149 #else
150 #ifdef CONFIG_BCM63XX_CPU_6348
151 switch (set) {
152 case RSET_DSL_LMEM:
153 return BCM_6348_DSL_LMEM_BASE;
154 case RSET_PERF:
155 return BCM_6348_PERF_BASE;
156 case RSET_TIMER:
157 return BCM_6348_TIMER_BASE;
158 case RSET_WDT:
159 return BCM_6348_WDT_BASE;
160 case RSET_UART0:
161 return BCM_6348_UART0_BASE;
162 case RSET_GPIO:
163 return BCM_6348_GPIO_BASE;
164 case RSET_SPI:
165 return BCM_6348_SPI_BASE;
166 case RSET_UDC0:
167 return BCM_6348_UDC0_BASE;
168 case RSET_OHCI0:
169 return BCM_6348_OHCI0_BASE;
170 case RSET_OHCI_PRIV:
171 return BCM_6348_OHCI_PRIV_BASE;
172 case RSET_USBH_PRIV:
173 return BCM_6348_USBH_PRIV_BASE;
174 case RSET_MPI:
175 return BCM_6348_MPI_BASE;
176 case RSET_PCMCIA:
177 return BCM_6348_PCMCIA_BASE;
178 case RSET_DSL:
179 return BCM_6348_DSL_BASE;
180 case RSET_ENET0:
181 return BCM_6348_ENET0_BASE;
182 case RSET_ENET1:
183 return BCM_6348_ENET1_BASE;
184 case RSET_ENETDMA:
185 return BCM_6348_ENETDMA_BASE;
186 case RSET_EHCI0:
187 return BCM_6348_EHCI0_BASE;
188 case RSET_SDRAM:
189 return BCM_6348_SDRAM_BASE;
190 case RSET_MEMC:
191 return BCM_6348_MEMC_BASE;
192 case RSET_DDR:
193 return BCM_6348_DDR_BASE;
194 }
195 #endif
196 #ifdef CONFIG_BCM63XX_CPU_6358
197 switch (set) {
198 case RSET_DSL_LMEM:
199 return BCM_6358_DSL_LMEM_BASE;
200 case RSET_PERF:
201 return BCM_6358_PERF_BASE;
202 case RSET_TIMER:
203 return BCM_6358_TIMER_BASE;
204 case RSET_WDT:
205 return BCM_6358_WDT_BASE;
206 case RSET_UART0:
207 return BCM_6358_UART0_BASE;
208 case RSET_GPIO:
209 return BCM_6358_GPIO_BASE;
210 case RSET_SPI:
211 return BCM_6358_SPI_BASE;
212 case RSET_UDC0:
213 return BCM_6358_UDC0_BASE;
214 case RSET_OHCI0:
215 return BCM_6358_OHCI0_BASE;
216 case RSET_OHCI_PRIV:
217 return BCM_6358_OHCI_PRIV_BASE;
218 case RSET_USBH_PRIV:
219 return BCM_6358_USBH_PRIV_BASE;
220 case RSET_MPI:
221 return BCM_6358_MPI_BASE;
222 case RSET_PCMCIA:
223 return BCM_6358_PCMCIA_BASE;
224 case RSET_ENET0:
225 return BCM_6358_ENET0_BASE;
226 case RSET_ENET1:
227 return BCM_6358_ENET1_BASE;
228 case RSET_ENETDMA:
229 return BCM_6358_ENETDMA_BASE;
230 case RSET_DSL:
231 return BCM_6358_DSL_BASE;
232 case RSET_EHCI0:
233 return BCM_6358_EHCI0_BASE;
234 case RSET_SDRAM:
235 return BCM_6358_SDRAM_BASE;
236 case RSET_MEMC:
237 return BCM_6358_MEMC_BASE;
238 case RSET_DDR:
239 return BCM_6358_DDR_BASE;
240 }
241 #endif
242 #endif
243 /* unreached */
244 return 0;
245 }
246
247 /*
248 * IRQ number changes across CPU too
249 */
250 enum bcm63xx_irq {
251 IRQ_TIMER = 0,
252 IRQ_UART0,
253 IRQ_SPI,
254 IRQ_DSL,
255 IRQ_ENET0,
256 IRQ_ENET1,
257 IRQ_ENET_PHY,
258 IRQ_OHCI0,
259 IRQ_EHCI0,
260 IRQ_PCMCIA0,
261 IRQ_ENET0_RXDMA,
262 IRQ_ENET0_TXDMA,
263 IRQ_ENET1_RXDMA,
264 IRQ_ENET1_TXDMA,
265 IRQ_PCI,
266 IRQ_PCMCIA,
267 };
268
269 /*
270 * 6348 irqs
271 */
272 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
273 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
274 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
275 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
276 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
277 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
278 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
279 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
280 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
281 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
282 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
283 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
284 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
285 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
286
287 /*
288 * 6358 irqs
289 */
290 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
291 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
292 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
293 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
294 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
295 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
296 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
297 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
298 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
299 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
300 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
301 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
302 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
303 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
304 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
305
306 extern const int *bcm63xx_irqs;
307
308 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
309 {
310 return bcm63xx_irqs[irq];
311 }
312
313 /*
314 * return installed memory size
315 */
316 unsigned int bcm63xx_get_memory_size(void);
317
318 #endif /* !BCM63XX_CPU_H_ */