[brcm63xx] add experimental support for bcm6338
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_cpu.h
1 #ifndef BCM63XX_CPU_H_
2 #define BCM63XX_CPU_H_
3
4 #include <linux/types.h>
5 #include <linux/init.h>
6
7 /*
8 * Macro to fetch bcm63xx cpu id and revision, should be optimized at
9 * compile time if only one CPU support is enabled (idea stolen from
10 * arm mach-types)
11 */
12 #define BCM6338_CPU_ID 0x6338
13 #define BCM6348_CPU_ID 0x6348
14 #define BCM6358_CPU_ID 0x6358
15
16 void __init bcm63xx_cpu_init(void);
17 u16 __bcm63xx_get_cpu_id(void);
18 u16 bcm63xx_get_cpu_rev(void);
19 unsigned int bcm63xx_get_cpu_freq(void);
20
21 #ifdef CONFIG_BCM63XX_CPU_6338
22 # ifdef bcm63xx_get_cpu_id
23 # undef bcm63xx_get_cpu_id
24 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
25 # define BCMCPU_RUNTIME_DETECT
26 # else
27 # define bcm63xx_get_cpu_id() BCM6338_CPU_ID
28 # endif
29 # define BCMCPU_IS_6338() (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
30 #else
31 # define BCMCPU_IS_6338() (0)
32 #endif
33
34 #ifdef CONFIG_BCM63XX_CPU_6348
35 # ifdef bcm63xx_get_cpu_id
36 # undef bcm63xx_get_cpu_id
37 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
38 # define BCMCPU_RUNTIME_DETECT
39 # else
40 # define bcm63xx_get_cpu_id() BCM6348_CPU_ID
41 # endif
42 # define BCMCPU_IS_6348() (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
43 #else
44 # define BCMCPU_IS_6348() (0)
45 #endif
46
47 #ifdef CONFIG_BCM63XX_CPU_6358
48 # ifdef bcm63xx_get_cpu_id
49 # undef bcm63xx_get_cpu_id
50 # define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
51 # define BCMCPU_RUNTIME_DETECT
52 # else
53 # define bcm63xx_get_cpu_id() BCM6358_CPU_ID
54 # endif
55 # define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
56 #else
57 # define BCMCPU_IS_6358() (0)
58 #endif
59
60 #ifndef bcm63xx_get_cpu_id
61 #error "No CPU support configured"
62 #endif
63
64 /*
65 * While registers sets are (mostly) the same across 63xx CPU, base
66 * address of these sets do change.
67 */
68 enum bcm63xx_regs_set {
69 RSET_DSL_LMEM = 0,
70 RSET_PERF,
71 RSET_TIMER,
72 RSET_WDT,
73 RSET_UART0,
74 RSET_GPIO,
75 RSET_SPI,
76 RSET_UDC0,
77 RSET_OHCI0,
78 RSET_OHCI_PRIV,
79 RSET_USBH_PRIV,
80 RSET_MPI,
81 RSET_PCMCIA,
82 RSET_DSL,
83 RSET_ENET0,
84 RSET_ENET1,
85 RSET_ENETDMA,
86 RSET_EHCI0,
87 RSET_SDRAM,
88 RSET_MEMC,
89 RSET_DDR,
90 };
91
92 #define RSET_DSL_LMEM_SIZE (64 * 1024 * 4)
93 #define RSET_DSL_SIZE 4096
94 #define RSET_WDT_SIZE 12
95 #define RSET_ENET_SIZE 2048
96 #define RSET_ENETDMA_SIZE 2048
97 #define RSET_UART_SIZE 24
98 #define RSET_SPI_SIZE 2048
99 #define RSET_UDC_SIZE 256
100 #define RSET_OHCI_SIZE 256
101 #define RSET_EHCI_SIZE 256
102 #define RSET_PCMCIA_SIZE 12
103
104 /*
105 * 6338 register sets base address
106 */
107
108 #define BCM_6338_PERF_BASE (0xfffe0000)
109 #define BCM_6338_TIMER_BASE (0xfffe0000)
110 #define BCM_6338_WDT_BASE (0xfffe001c)
111 #define BCM_6338_UART0_BASE (0xfffe0300)
112 #define BCM_6338_GPIO_BASE (0xfffe0400)
113 #define BCM_6338_SPI_BASE (0xfffe0c00)
114 #define BCM_6338_SAR_BASE (0xfffe2000)
115 #define BCM_6338_MEMC_BASE (0xfffe3100)
116
117 /*
118 * 6348 register sets base address
119 */
120 #define BCM_6348_DSL_LMEM_BASE (0xfff00000)
121 #define BCM_6348_PERF_BASE (0xfffe0000)
122 #define BCM_6348_TIMER_BASE (0xfffe0200)
123 #define BCM_6348_WDT_BASE (0xfffe021c)
124 #define BCM_6348_UART0_BASE (0xfffe0300)
125 #define BCM_6348_GPIO_BASE (0xfffe0400)
126 #define BCM_6348_SPI_BASE (0xfffe0c00)
127 #define BCM_6348_UDC0_BASE (0xfffe1000)
128 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
129 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
130 #define BCM_6348_USBH_PRIV_BASE (0xdeadbeef)
131 #define BCM_6348_MPI_BASE (0xfffe2000)
132 #define BCM_6348_PCMCIA_BASE (0xfffe2054)
133 #define BCM_6348_SDRAM_REGS_BASE (0xfffe2300)
134 #define BCM_6348_DSL_BASE (0xfffe3000)
135 #define BCM_6348_ENET0_BASE (0xfffe6000)
136 #define BCM_6348_ENET1_BASE (0xfffe6800)
137 #define BCM_6348_ENETDMA_BASE (0xfffe7000)
138 #define BCM_6348_EHCI0_BASE (0xdeadbeef)
139 #define BCM_6348_SDRAM_BASE (0xfffe2300)
140 #define BCM_6348_MEMC_BASE (0xdeadbeef)
141 #define BCM_6348_DDR_BASE (0xdeadbeef)
142
143 /*
144 * 6358 register sets base address
145 */
146 #define BCM_6358_DSL_LMEM_BASE (0xfff00000)
147 #define BCM_6358_PERF_BASE (0xfffe0000)
148 #define BCM_6358_TIMER_BASE (0xfffe0040)
149 #define BCM_6358_WDT_BASE (0xfffe005c)
150 #define BCM_6358_GPIO_BASE (0xfffe0080)
151 #define BCM_6358_UART0_BASE (0xfffe0100)
152 #define BCM_6358_UDC0_BASE (0xfffe0400)
153 #define BCM_6358_SPI_BASE (0xfffe0800)
154 #define BCM_6358_MPI_BASE (0xfffe1000)
155 #define BCM_6358_PCMCIA_BASE (0xfffe1054)
156 #define BCM_6358_OHCI0_BASE (0xfffe1400)
157 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
158 #define BCM_6358_USBH_PRIV_BASE (0xfffe1500)
159 #define BCM_6358_SDRAM_REGS_BASE (0xfffe2300)
160 #define BCM_6358_DSL_BASE (0xfffe3000)
161 #define BCM_6358_ENET0_BASE (0xfffe4000)
162 #define BCM_6358_ENET1_BASE (0xfffe4800)
163 #define BCM_6358_ENETDMA_BASE (0xfffe5000)
164 #define BCM_6358_EHCI0_BASE (0xfffe1300)
165 #define BCM_6358_SDRAM_BASE (0xdeadbeef)
166 #define BCM_6358_MEMC_BASE (0xfffe1200)
167 #define BCM_6358_DDR_BASE (0xfffe12a0)
168
169
170 extern const unsigned long *bcm63xx_regs_base;
171
172 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
173 {
174 #ifdef BCMCPU_RUNTIME_DETECT
175 return bcm63xx_regs_base[set];
176 #else
177 #ifdef CONFIG_BCM63XX_CPU_6338
178 switch (set) {
179 case RSET_PERF:
180 return BCM_6338_PERF_BASE;
181 case RSET_TIMER:
182 return BCM_6338_TIMER_BASE;
183 case RSET_WDT:
184 return BCM_6338_WDT_BASE;
185 case RSET_UART0:
186 return BCM_6338_UART0_BASE;
187 case RSET_GPIO:
188 return BCM_6338_GPIO_BASE;
189 case RSET_SPI:
190 return BCM_6338_SPI_BASE;
191 case RSET_MEMC:
192 return BCM_6338_MEMC_BASE;
193 }
194 #endif
195 #ifdef CONFIG_BCM63XX_CPU_6348
196 switch (set) {
197 case RSET_DSL_LMEM:
198 return BCM_6348_DSL_LMEM_BASE;
199 case RSET_PERF:
200 return BCM_6348_PERF_BASE;
201 case RSET_TIMER:
202 return BCM_6348_TIMER_BASE;
203 case RSET_WDT:
204 return BCM_6348_WDT_BASE;
205 case RSET_UART0:
206 return BCM_6348_UART0_BASE;
207 case RSET_GPIO:
208 return BCM_6348_GPIO_BASE;
209 case RSET_SPI:
210 return BCM_6348_SPI_BASE;
211 case RSET_UDC0:
212 return BCM_6348_UDC0_BASE;
213 case RSET_OHCI0:
214 return BCM_6348_OHCI0_BASE;
215 case RSET_OHCI_PRIV:
216 return BCM_6348_OHCI_PRIV_BASE;
217 case RSET_USBH_PRIV:
218 return BCM_6348_USBH_PRIV_BASE;
219 case RSET_MPI:
220 return BCM_6348_MPI_BASE;
221 case RSET_PCMCIA:
222 return BCM_6348_PCMCIA_BASE;
223 case RSET_DSL:
224 return BCM_6348_DSL_BASE;
225 case RSET_ENET0:
226 return BCM_6348_ENET0_BASE;
227 case RSET_ENET1:
228 return BCM_6348_ENET1_BASE;
229 case RSET_ENETDMA:
230 return BCM_6348_ENETDMA_BASE;
231 case RSET_EHCI0:
232 return BCM_6348_EHCI0_BASE;
233 case RSET_SDRAM:
234 return BCM_6348_SDRAM_BASE;
235 case RSET_MEMC:
236 return BCM_6348_MEMC_BASE;
237 case RSET_DDR:
238 return BCM_6348_DDR_BASE;
239 }
240 #endif
241 #ifdef CONFIG_BCM63XX_CPU_6358
242 switch (set) {
243 case RSET_DSL_LMEM:
244 return BCM_6358_DSL_LMEM_BASE;
245 case RSET_PERF:
246 return BCM_6358_PERF_BASE;
247 case RSET_TIMER:
248 return BCM_6358_TIMER_BASE;
249 case RSET_WDT:
250 return BCM_6358_WDT_BASE;
251 case RSET_UART0:
252 return BCM_6358_UART0_BASE;
253 case RSET_GPIO:
254 return BCM_6358_GPIO_BASE;
255 case RSET_SPI:
256 return BCM_6358_SPI_BASE;
257 case RSET_UDC0:
258 return BCM_6358_UDC0_BASE;
259 case RSET_OHCI0:
260 return BCM_6358_OHCI0_BASE;
261 case RSET_OHCI_PRIV:
262 return BCM_6358_OHCI_PRIV_BASE;
263 case RSET_USBH_PRIV:
264 return BCM_6358_USBH_PRIV_BASE;
265 case RSET_MPI:
266 return BCM_6358_MPI_BASE;
267 case RSET_PCMCIA:
268 return BCM_6358_PCMCIA_BASE;
269 case RSET_ENET0:
270 return BCM_6358_ENET0_BASE;
271 case RSET_ENET1:
272 return BCM_6358_ENET1_BASE;
273 case RSET_ENETDMA:
274 return BCM_6358_ENETDMA_BASE;
275 case RSET_DSL:
276 return BCM_6358_DSL_BASE;
277 case RSET_EHCI0:
278 return BCM_6358_EHCI0_BASE;
279 case RSET_SDRAM:
280 return BCM_6358_SDRAM_BASE;
281 case RSET_MEMC:
282 return BCM_6358_MEMC_BASE;
283 case RSET_DDR:
284 return BCM_6358_DDR_BASE;
285 }
286 #endif
287 #endif
288 /* unreached */
289 return 0;
290 }
291
292 /*
293 * IRQ number changes across CPU too
294 */
295 enum bcm63xx_irq {
296 IRQ_TIMER = 0,
297 IRQ_UART0,
298 IRQ_SPI,
299 IRQ_DSL,
300 IRQ_ENET0,
301 IRQ_ENET1,
302 IRQ_ENET_PHY,
303 IRQ_OHCI0,
304 IRQ_EHCI0,
305 IRQ_PCMCIA0,
306 IRQ_ENET0_RXDMA,
307 IRQ_ENET0_TXDMA,
308 IRQ_ENET1_RXDMA,
309 IRQ_ENET1_TXDMA,
310 IRQ_PCI,
311 IRQ_PCMCIA,
312 };
313
314 /*
315 * 6338 irqs
316 */
317 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
318 #define BCM_6338_SPI_IR (IRQ_INTERNAL_BASE + 1)
319 #define BCM_6338_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
320 #define BCM_6338_DG_IRQ (IRQ_INTERNAL_BASE + 4)
321 #define BCM_6338_DSL_IRQ (IRQ_INTERNAL_BASE + 5)
322 #define BCM_6338_ATM_IRQ (IRQ_INTERNAL_BASE + 6)
323 #define BCM_6338_USBS_IRQ (IRQ_INTERNAL_BASE + 7)
324 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
325 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
326 #define BCM_6338_SDRAM_IRQ (IRQ_INTERNAL_BASE + 10)
327 #define BCM_6338_USB_CNTL_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 11)
328 #define BCM_6338_USB_CNTL_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 12)
329 #define BCM_6338_USB_BULK_RX_DMA_IRQ (IRQ_INTERNAL_BASE + 13)
330 #define BCM_6338_USB_BULK_TX_DMA_IRQ (IRQ_INTERNAL_BASE + 14)
331 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
332 #define BCM_6338_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
333 #define BCM_6338_SDIO_IRQ (IRQ_INTERNAL_BASE + 17)
334
335 /*
336 * 6348 irqs
337 */
338 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
339 #define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
340 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
341 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
342 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
343 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
344 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
345 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
346 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
347 #define BCM_6348_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 21)
348 #define BCM_6348_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 22)
349 #define BCM_6348_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 23)
350 #define BCM_6348_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
351 #define BCM_6348_PCI_IRQ (IRQ_INTERNAL_BASE + 24)
352
353 /*
354 * 6358 irqs
355 */
356 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
357 #define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
358 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
359 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
360 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
361 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
362 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
363 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
364 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
365 #define BCM_6358_ENET0_TXDMA_IRQ (IRQ_INTERNAL_BASE + 16)
366 #define BCM_6358_ENET1_RXDMA_IRQ (IRQ_INTERNAL_BASE + 17)
367 #define BCM_6358_ENET1_TXDMA_IRQ (IRQ_INTERNAL_BASE + 18)
368 #define BCM_6358_DSL_IRQ (IRQ_INTERNAL_BASE + 29)
369 #define BCM_6358_PCI_IRQ (IRQ_INTERNAL_BASE + 31)
370 #define BCM_6358_PCMCIA_IRQ (IRQ_INTERNAL_BASE + 24)
371
372 extern const int *bcm63xx_irqs;
373
374 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
375 {
376 return bcm63xx_irqs[irq];
377 }
378
379 /*
380 * return installed memory size
381 */
382 unsigned int bcm63xx_get_memory_size(void);
383
384 #endif /* !BCM63XX_CPU_H_ */