target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h

   1 #ifndef BCM63XX_CPU_H_
   2 #define BCM63XX_CPU_H_
   3
   4 #include <linux/types.h>
   5 #include <linux/init.h>
   6
   7 #include <bcm63xx_regs.h>
   8
   9 /*
  10  * Macro to fetch bcm63xx cpu id and revision, should be optimized at
  11  * compile time if only one CPU support is enabled (idea stolen from
  12  * arm mach-types)
  13  */
  14 #define BCM6338_CPU_ID          0x6338
  15 #define BCM6345_CPU_ID          0x6345
  16 #define BCM6348_CPU_ID          0x6348
  17 #define BCM6358_CPU_ID          0x6358
  18
  19 void __init bcm63xx_cpu_init(void);
  20 u16 __bcm63xx_get_cpu_id(void);
  21 u16 bcm63xx_get_cpu_rev(void);
  22 unsigned int bcm63xx_get_cpu_freq(void);
  23
  24 #ifdef CONFIG_BCM63XX_CPU_6338
  25 # ifdef bcm63xx_get_cpu_id
  26 #  undef bcm63xx_get_cpu_id
  27 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  28 #  define BCMCPU_RUNTIME_DETECT
  29 # else
  30 #  define bcm63xx_get_cpu_id()  BCM6338_CPU_ID
  31 # endif
  32 # define BCMCPU_IS_6338()       (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
  33 #else
  34 # define BCMCPU_IS_6338()       (0)
  35 #endif
  36
  37 #ifdef CONFIG_BCM63XX_CPU_6345
  38 # ifdef bcm63xx_get_cpu_id
  39 #  undef bcm63xx_get_cpu_id
  40 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  41 #  define BCMCPU_RUNTIME_DETECT
  42 # else
  43 #  define bcm63xx_get_cpu_id()  BCM6345_CPU_ID
  44 # endif
  45 # define BCMCPU_IS_6345()       (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
  46 #else
  47 # define BCMCPU_IS_6345()       (0)
  48 #endif
  49
  50 #ifdef CONFIG_BCM63XX_CPU_6348
  51 # ifdef bcm63xx_get_cpu_id
  52 #  undef bcm63xx_get_cpu_id
  53 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  54 #  define BCMCPU_RUNTIME_DETECT
  55 # else
  56 #  define bcm63xx_get_cpu_id()  BCM6348_CPU_ID
  57 # endif
  58 # define BCMCPU_IS_6348()       (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
  59 #else
  60 # define BCMCPU_IS_6348()       (0)
  61 #endif
  62
  63 #ifdef CONFIG_BCM63XX_CPU_6358
  64 # ifdef bcm63xx_get_cpu_id
  65 #  undef bcm63xx_get_cpu_id
  66 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  67 #  define BCMCPU_RUNTIME_DETECT
  68 # else
  69 #  define bcm63xx_get_cpu_id()  BCM6358_CPU_ID
  70 # endif
  71 # define BCMCPU_IS_6358()       (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
  72 #else
  73 # define BCMCPU_IS_6358()       (0)
  74 #endif
  75
  76 #ifndef bcm63xx_get_cpu_id
  77 #error "No CPU support configured"
  78 #endif
  79
  80 /*
  81  * While registers sets are (mostly) the same across 63xx CPU, base
  82  * address of these sets do change.
  83  */
  84 enum bcm63xx_regs_set {
  85         RSET_DSL_LMEM = 0,
  86         RSET_PERF,
  87         RSET_TIMER,
  88         RSET_WDT,
  89         RSET_UART0,
  90         RSET_GPIO,
  91         RSET_SPI,
  92         RSET_UDC0,
  93         RSET_OHCI0,
  94         RSET_OHCI_PRIV,
  95         RSET_USBH_PRIV,
  96         RSET_MPI,
  97         RSET_PCMCIA,
  98         RSET_DSL,
  99         RSET_ENET0,
 100         RSET_ENET1,
 101         RSET_ENETDMA,
 102         RSET_EHCI0,
 103         RSET_SDRAM,
 104         RSET_MEMC,
 105         RSET_DDR,
 106 };
 107
 108 #define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
 109 #define RSET_DSL_SIZE                   4096
 110 #define RSET_WDT_SIZE                   12
 111 #define RSET_ENET_SIZE                  2048
 112 #define RSET_ENETDMA_SIZE               2048
 113 #define RSET_UART_SIZE                  24
 114 #define RSET_SPI_SIZE                   256
 115 #define RSET_UDC_SIZE                   256
 116 #define RSET_OHCI_SIZE                  256
 117 #define RSET_EHCI_SIZE                  256
 118 #define RSET_PCMCIA_SIZE                12
 119
 120 /*
 121  * 6338 register sets base address
 122  */
 123
 124 #define BCM_6338_DSL_LMEM_BASE          (0xfff00000)
 125 #define BCM_6338_PERF_BASE              (0xfffe0000)
 126 #define BCM_6338_BB_BASE                (0xfffe0100)
 127 #define BCM_6338_TIMER_BASE             (0xfffe0200)
 128 #define BCM_6338_WDT_BASE               (0xfffe021c)
 129 #define BCM_6338_UART0_BASE             (0xfffe0300)
 130 #define BCM_6338_GPIO_BASE              (0xfffe0400)
 131 #define BCM_6338_SPI_BASE               (0xfffe0c00)
 132 #define BCM_6338_UDC0_BASE              (0xdeadbeef)
 133 #define BCM_6338_USBDMA_BASE            (0xfffe2400)
 134 #define BCM_6338_OHCI0_BASE             (0xdeadbeef)
 135 #define BCM_6338_OHCI_PRIV_BASE         (0xfffe3000)
 136 #define BCM_6338_USBH_PRIV_BASE         (0xdeadbeef)
 137 #define BCM_6338_MPI_BASE               (0xfffe3160)
 138 #define BCM_6338_PCMCIA_BASE            (0xdeadbeef)
 139 #define BCM_6338_SDRAM_REGS_BASE        (0xfffe3100)
 140 #define BCM_6338_DSL_BASE               (0xfffe1000)
 141 #define BCM_6338_SAR_BASE               (0xfffe2000)
 142 #define BCM_6338_UBUS_BASE              (0xdeadbeef)
 143 #define BCM_6338_ENET0_BASE             (0xfffe2800)
 144 #define BCM_6338_ENET1_BASE             (0xdeadbeef)
 145 #define BCM_6338_ENETDMA_BASE           (0xfffe2400)
 146 #define BCM_6338_EHCI0_BASE             (0xdeadbeef)
 147 #define BCM_6338_SDRAM_BASE             (0xfffe3100)
 148 #define BCM_6338_MEMC_BASE              (0xdeadbeef)
 149 #define BCM_6338_DDR_BASE               (0xdeadbeef)
 150
 151 /*
 152  * 6345 register sets base address
 153  */
 154 #define BCM_6345_PERF_BASE              (0xfffe0000)
 155 #define BCM_6345_TIMER_BASE             (0xfffe0200)
 156 #define BCM_6345_WDT_BASE               (0xfffe021c)
 157 #define BCM_6345_UART0_BASE             (0xfffe0300)
 158 #define BCM_6345_GPIO_BASE              (0xfffe0400)
 159
 160 /*
 161  * 6348 register sets base address
 162  */
 163 #define BCM_6348_DSL_LMEM_BASE          (0xfff00000)
 164 #define BCM_6348_PERF_BASE              (0xfffe0000)
 165 #define BCM_6348_BB_BASE                (0xfffe0100) /* bus bridge registers */
 166 #define BCM_6348_TIMER_BASE             (0xfffe0200)
 167 #define BCM_6348_WDT_BASE               (0xfffe021c)
 168 #define BCM_6348_UART0_BASE             (0xfffe0300)
 169 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 170 #define BCM_6348_SPI_BASE               (0xfffe0c00)
 171 #define BCM_6348_UDC0_BASE              (0xfffe1000)
 172 #define BCM_6348_USBDMA_BASE            (0xfffe1400)
 173 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 174 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
 175 #define BCM_6348_USBH_PRIV_BASE         (0xdeadbeef)
 176 #define BCM_6348_MPI_BASE               (0xfffe2000)
 177 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
 178 #define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
 179 #define BCM_6348_DSL_BASE               (0xfffe3000)
 180 #define BCM_6348_SAR_BASE               (0xfffe4000)
 181 #define BCM_6348_UBUS_BASE              (0xfffe5000)
 182 #define BCM_6348_ENET0_BASE             (0xfffe6000)
 183 #define BCM_6348_ENET1_BASE             (0xfffe6800)
 184 #define BCM_6348_ENETDMA_BASE           (0xfffe7000)
 185 #define BCM_6348_EHCI0_BASE             (0xdeadbeef)
 186 #define BCM_6348_SDRAM_BASE             (0xfffe2300)
 187 #define BCM_6348_MEMC_BASE              (0xdeadbeef)
 188 #define BCM_6348_DDR_BASE               (0xdeadbeef)
 189
 190 /*
 191  * 6358 register sets base address
 192  */
 193 #define BCM_6358_DSL_LMEM_BASE          (0xfff00000)
 194 #define BCM_6358_PERF_BASE              (0xfffe0000)
 195 #define BCM_6358_TIMER_BASE             (0xfffe0040)
 196 #define BCM_6358_WDT_BASE               (0xfffe005c)
 197 #define BCM_6358_GPIO_BASE              (0xfffe0080)
 198 #define BCM_6358_UART0_BASE             (0xfffe0100)
 199 #define BCM_6358_UDC0_BASE              (0xfffe0400)
 200 #define BCM_6358_SPI_BASE               (0xfffe0800)
 201 #define BCM_6358_MPI_BASE               (0xfffe1000)
 202 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
 203 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 204 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
 205 #define BCM_6358_USBH_PRIV_BASE         (0xfffe1500)
 206 #define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
 207 #define BCM_6358_DSL_BASE               (0xfffe3000)
 208 #define BCM_6358_ENET0_BASE             (0xfffe4000)
 209 #define BCM_6358_ENET1_BASE             (0xfffe4800)
 210 #define BCM_6358_ENETDMA_BASE           (0xfffe5000)
 211 #define BCM_6358_EHCI0_BASE             (0xfffe1300)
 212 #define BCM_6358_SDRAM_BASE             (0xdeadbeef)
 213 #define BCM_6358_MEMC_BASE              (0xfffe1200)
 214 #define BCM_6358_DDR_BASE               (0xfffe12a0)
 215
 216
 217 extern const unsigned long *bcm63xx_regs_base;
 218
 219 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 220 {
 221 #ifdef BCMCPU_RUNTIME_DETECT
 222         return bcm63xx_regs_base[set];
 223 #else
 224 #ifdef CONFIG_BCM63XX_CPU_6338
 225         switch (set) {
 226         case RSET_DSL_LMEM:
 227                 return BCM_6338_DSL_LMEM_BASE;
 228         case RSET_PERF:
 229                 return BCM_6338_PERF_BASE;
 230         case RSET_TIMER:
 231                 return BCM_6338_TIMER_BASE;
 232         case RSET_WDT:
 233                 return BCM_6338_WDT_BASE;
 234         case RSET_UART0:
 235                 return BCM_6338_UART0_BASE;
 236         case RSET_GPIO:
 237                 return BCM_6338_GPIO_BASE;
 238         case RSET_SPI:
 239                 return BCM_6338_SPI_BASE;
 240         case RSET_UDC0:
 241                 return BCM_6338_UDC0_BASE;
 242         case RSET_OHCI0:
 243                 return BCM_6338_OHCI0_BASE;
 244         case RSET_OHCI_PRIV:
 245                 return BCM_6338_OHCI_PRIV_BASE;
 246         case RSET_USBH_PRIV:
 247                 return BCM_6338_USBH_PRIV_BASE;
 248         case RSET_MPI:
 249                 return BCM_6338_MPI_BASE;
 250         case RSET_PCMCIA:
 251                 return BCM_6338_PCMCIA_BASE;
 252         case RSET_DSL:
 253                 return BCM_6338_DSL_BASE;
 254         case RSET_ENET0:
 255                 return BCM_6338_ENET0_BASE;
 256         case RSET_ENET1:
 257                 return BCM_6338_ENET1_BASE;
 258         case RSET_ENETDMA:
 259                 return BCM_6338_ENETDMA_BASE;
 260         case RSET_EHCI0:
 261                 return BCM_6338_EHCI0_BASE;
 262         case RSET_SDRAM:
 263                 return BCM_6338_SDRAM_BASE;
 264         case RSET_MEMC:
 265                 return BCM_6338_MEMC_BASE;
 266         case RSET_DDR:
 267                 return BCM_6338_DDR_BASE;
 268         }
 269 #endif
 270 #ifdef CONFIG_BCM63XX_CPU_6345
 271         switch (set) {
 272         case RSET_PERF:
 273                 return BCM_6345_PERF_BASE;
 274         case RSET_TIMER:
 275                 return BCM_6345_TIMER_BASE;
 276         case RSET_WDT:
 277                 return BCM_6345_WDT_BASE;
 278         case RSET_UART0:
 279                 return BCM_6345_UART0_BASE;
 280         case RSET_GPIO:
 281                 return BCM_6345_GPIO_BASE;
 282         }
 283 #endif
 284 #ifdef CONFIG_BCM63XX_CPU_6348
 285         switch (set) {
 286         case RSET_DSL_LMEM:
 287                 return BCM_6348_DSL_LMEM_BASE;
 288         case RSET_PERF:
 289                 return BCM_6348_PERF_BASE;
 290         case RSET_TIMER:
 291                 return BCM_6348_TIMER_BASE;
 292         case RSET_WDT:
 293                 return BCM_6348_WDT_BASE;
 294         case RSET_UART0:
 295                 return BCM_6348_UART0_BASE;
 296         case RSET_GPIO:
 297                 return BCM_6348_GPIO_BASE;
 298         case RSET_SPI:
 299                 return BCM_6348_SPI_BASE;
 300         case RSET_UDC0:
 301                 return BCM_6348_UDC0_BASE;
 302         case RSET_OHCI0:
 303                 return BCM_6348_OHCI0_BASE;
 304         case RSET_OHCI_PRIV:
 305                 return BCM_6348_OHCI_PRIV_BASE;
 306         case RSET_USBH_PRIV:
 307                 return BCM_6348_USBH_PRIV_BASE;
 308         case RSET_MPI:
 309                 return BCM_6348_MPI_BASE;
 310         case RSET_PCMCIA:
 311                 return BCM_6348_PCMCIA_BASE;
 312         case RSET_DSL:
 313                 return BCM_6348_DSL_BASE;
 314         case RSET_ENET0:
 315                 return BCM_6348_ENET0_BASE;
 316         case RSET_ENET1:
 317                 return BCM_6348_ENET1_BASE;
 318         case RSET_ENETDMA:
 319                 return BCM_6348_ENETDMA_BASE;
 320         case RSET_EHCI0:
 321                 return BCM_6348_EHCI0_BASE;
 322         case RSET_SDRAM:
 323                 return BCM_6348_SDRAM_BASE;
 324         case RSET_MEMC:
 325                 return BCM_6348_MEMC_BASE;
 326         case RSET_DDR:
 327                 return BCM_6348_DDR_BASE;
 328         }
 329 #endif
 330 #ifdef CONFIG_BCM63XX_CPU_6358
 331         switch (set) {
 332         case RSET_DSL_LMEM:
 333                 return BCM_6358_DSL_LMEM_BASE;
 334         case RSET_PERF:
 335                 return BCM_6358_PERF_BASE;
 336         case RSET_TIMER:
 337                 return BCM_6358_TIMER_BASE;
 338         case RSET_WDT:
 339                 return BCM_6358_WDT_BASE;
 340         case RSET_UART0:
 341                 return BCM_6358_UART0_BASE;
 342         case RSET_GPIO:
 343                 return BCM_6358_GPIO_BASE;
 344         case RSET_SPI:
 345                 return BCM_6358_SPI_BASE;
 346         case RSET_UDC0:
 347                 return BCM_6358_UDC0_BASE;
 348         case RSET_OHCI0:
 349                 return BCM_6358_OHCI0_BASE;
 350         case RSET_OHCI_PRIV:
 351                 return BCM_6358_OHCI_PRIV_BASE;
 352         case RSET_USBH_PRIV:
 353                 return BCM_6358_USBH_PRIV_BASE;
 354         case RSET_MPI:
 355                 return BCM_6358_MPI_BASE;
 356         case RSET_PCMCIA:
 357                 return BCM_6358_PCMCIA_BASE;
 358         case RSET_ENET0:
 359                 return BCM_6358_ENET0_BASE;
 360         case RSET_ENET1:
 361                 return BCM_6358_ENET1_BASE;
 362         case RSET_ENETDMA:
 363                 return BCM_6358_ENETDMA_BASE;
 364         case RSET_DSL:
 365                 return BCM_6358_DSL_BASE;
 366         case RSET_EHCI0:
 367                 return BCM_6358_EHCI0_BASE;
 368         case RSET_SDRAM:
 369                 return BCM_6358_SDRAM_BASE;
 370         case RSET_MEMC:
 371                 return BCM_6358_MEMC_BASE;
 372         case RSET_DDR:
 373                 return BCM_6358_DDR_BASE;
 374         }
 375 #endif
 376 #endif
 377         /* unreached */
 378         return 0;
 379 }
 380
 381 /*
 382  * SPI register layout is not compatible
 383  * accross CPU versions but it is software
 384  * compatible
 385  */
 386
 387 enum bcm63xx_regs_spi {
 388         SPI_CMD,
 389         SPI_INT_STATUS,
 390         SPI_INT_MASK_ST,
 391         SPI_INT_MASK,
 392         SPI_ST,
 393         SPI_CLK_CFG,
 394         SPI_FILL_BYTE,
 395         SPI_MSG_TAIL,
 396         SPI_RX_TAIL,
 397         SPI_MSG_CTL,
 398         SPI_MSG_DATA,
 399         SPI_RX_DATA,
 400 };
 401
 402 extern const unsigned long *bcm63xx_regs_spi;
 403
 404 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 405 {
 406 #ifdef BCMCPU_RUNTIME_DETECT
 407         return bcm63xx_regs_spi[reg];
 408 #else
 409 #ifdef CONFIG_BCM63XX_CPU_6338
 410 switch (reg) {
 411         case SPI_CMD:
 412                 return SPI_BCM_6338_SPI_CMD;
 413         case SPI_INT_STATUS:
 414                 return SPI_BCM_6338_SPI_INT_STATUS;
 415         case SPI_INT_MASK_ST:
 416                 return SPI_BCM_6338_SPI_MASK_INT_ST;
 417         case SPI_INT_MASK:
 418                 return SPI_BCM_6338_SPI_INT_MASK;
 419         case SPI_ST:
 420                 return SPI_BCM_6338_SPI_ST;
 421         case SPI_CLK_CFG:
 422                 return SPI_BCM_6338_SPI_CLK_CFG;
 423         case SPI_FILL_BYTE:
 424                 return SPI_BCM_6338_SPI_FILL_BYTE;
 425         case SPI_MSG_TAIL:
 426                 return SPI_BCM_6338_SPI_MSG_TAIL;
 427         case SPI_RX_TAIL:
 428                 return SPI_BCM_6338_SPI_RX_TAIL;
 429         case SPI_MSG_CTL:
 430                 return SPI_BCM_6338_SPI_MSG_CTL;
 431         case SPI_MSG_DATA:
 432                 return SPI_BCM_6338_SPI_MSG_DATA;
 433         case SPI_RX_DATA:
 434                 return SPI_BCM_6338_SPI_RX_DATA;
 435 }
 436 #endif
 437 #ifdef CONFIG_BCM63XX_CPU_6348
 438 switch (reg) {
 439         case SPI_CMD:
 440                 return SPI_BCM_6348_SPI_CMD;
 441         case SPI_INT_MASK_ST:
 442                 return SPI_BCM_6348_SPI_MASK_INT_ST;
 443         case SPI_INT_MASK:
 444                 return SPI_BCM_6348_SPI_INT_MASK;
 445         case SPI_INT_STATUS:
 446                 return SPI_BCM_6348_SPI_INT_STATUS;
 447         case SPI_ST:
 448                 return SPI_BCM_6348_SPI_ST;
 449         case SPI_CLK_CFG:
 450                 return SPI_BCM_6348_SPI_CLK_CFG;
 451         case SPI_FILL_BYTE:
 452                 return SPI_BCM_6348_SPI_FILL_BYTE;
 453         case SPI_MSG_TAIL:
 454                 return SPI_BCM_6348_SPI_MSG_TAIL;
 455         case SPI_RX_TAIL:
 456                 return SPI_BCM_6348_SPI_RX_TAIL;
 457         case SPI_MSG_CTL:
 458                 return SPI_BCM_6348_SPI_MSG_CTL;
 459         case SPI_MSG_DATA:
 460                 return SPI_BCM_6348_SPI_MSG_DATA;
 461         case SPI_RX_DATA:
 462                 return SPI_BCM_6348_SPI_RX_DATA;
 463 }
 464 #endif
 465 #ifdef CONFIG_BCM63XX_CPU_6358
 466 switch (reg) {
 467         case SPI_CMD:
 468                 return SPI_BCM_6358_SPI_CMD;
 469         case SPI_INT_STATUS:
 470                 return SPI_BCM_6358_SPI_INT_STATUS;
 471         case SPI_INT_MASK_ST:
 472                 return SPI_BCM_6358_SPI_MASK_INT_ST;
 473         case SPI_INT_MASK:
 474                 return SPI_BCM_6358_SPI_INT_MASK;
 475         case SPI_ST:
 476                 return SPI_BCM_6358_SPI_STATUS;
 477         case SPI_CLK_CFG:
 478                 return SPI_BCM_6358_SPI_CLK_CFG;
 479         case SPI_FILL_BYTE:
 480                 return SPI_BCM_6358_SPI_FILL_BYTE;
 481         case SPI_MSG_TAIL:
 482                 return SPI_BCM_6358_SPI_MSG_TAIL;
 483         case SPI_RX_TAIL:
 484                 return SPI_BCM_6358_SPI_RX_TAIL;
 485         case SPI_MSG_CTL:
 486                 return SPI_BCM_6358_MSG_CTL;
 487         case SPI_MSG_DATA:
 488                 return SPI_BCM_6358_SPI_MSG_DATA;
 489         case SPI_RX_DATA:
 490                 return SPI_BCM_6358_SPI_RX_DATA;
 491 }
 492 #endif
 493 #endif
 494         return 0;
 495 }
 496
 497 /*
 498  * IRQ number changes across CPU too
 499  */
 500 enum bcm63xx_irq {
 501         IRQ_TIMER = 0,
 502         IRQ_UART0,
 503         IRQ_SPI,
 504         IRQ_DSL,
 505         IRQ_UDC0,
 506         IRQ_ENET0,
 507         IRQ_ENET1,
 508         IRQ_ENET_PHY,
 509         IRQ_OHCI0,
 510         IRQ_EHCI0,
 511         IRQ_PCMCIA0,
 512         IRQ_ENET0_RXDMA,
 513         IRQ_ENET0_TXDMA,
 514         IRQ_ENET1_RXDMA,
 515         IRQ_ENET1_TXDMA,
 516         IRQ_PCI,
 517         IRQ_PCMCIA,
 518 };
 519
 520 /*
 521  * 6338 irqs
 522  */
 523 #define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 524 #define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 525 #define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 526 #define BCM_6338_DG_IRQ                 (IRQ_INTERNAL_BASE + 4)
 527 #define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
 528 #define BCM_6338_ATM_IRQ                (IRQ_INTERNAL_BASE + 6)
 529 #define BCM_6338_UDC0_IRQ               (IRQ_INTERNAL_BASE + 7)
 530 #define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 531 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 532 #define BCM_6338_SDRAM_IRQ              (IRQ_INTERNAL_BASE + 10)
 533 #define BCM_6338_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 11)
 534 #define BCM_6338_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 12)
 535 #define BCM_6338_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13)
 536 #define BCM_6338_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 14)
 537 #define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 538 #define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 539 #define BCM_6338_SDIO_IRQ               (IRQ_INTERNAL_BASE + 17)
 540
 541 /*
 542  * 6345 irqs
 543  */
 544 #define BCM_6345_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 545 #define BCM_6345_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 546 #define BCM_6345_DSL_IRQ                (IRQ_INTERNAL_BASE + 3)
 547 #define BCM_6345_ATM_IRQ                (IRQ_INTERNAL_BASE + 4)
 548 #define BCM_6345_USB_IRQ                (IRQ_INTERNAL_BASE + 5)
 549 #define BCM_6345_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 550 #define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
 551
 552 /*
 553  * 6348 irqs
 554  */
 555 #define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 556 #define BCM_6348_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 557 #define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 558 #define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
 559 #define BCM_6348_UDC0_IRQ               (IRQ_INTERNAL_BASE + 6)
 560 #define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 561 #define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 562 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 563 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
 564 #define BCM_6348_USB_CNTL_RX_DMA        (IRQ_INTERNAL_BASE + 14)
 565 #define BCM_6348_USB_CNTL_TX_DMA        (IRQ_INTERNAL_BASE + 15)
 566 #define BCM_6348_USB_BULK_RX_DMA        (IRQ_INTERNAL_BASE + 16)
 567 #define BCM_6348_USB_BULK_TX_DMA        (IRQ_INTERNAL_BASE + 17)
 568 #define BCM_6348_USB_ISO_RX_DMA         (IRQ_INTERNAL_BASE + 18)
 569 #define BCM_6348_USB_ISO_TX_DMA         (IRQ_INTERNAL_BASE + 19)
 570 #define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
 571 #define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
 572 #define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
 573 #define BCM_6348_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 23)
 574 #define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 575 #define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
 576
 577 /*
 578  * 6358 irqs
 579  */
 580 #define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 581 #define BCM_6358_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 582 #define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 583 #define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 584 #define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
 585 #define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 586 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 587 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
 588 #define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 589 #define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 590 #define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 591 #define BCM_6358_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
 592 #define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 593 #define BCM_6358_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
 594 #define BCM_6358_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 595
 596 extern const int *bcm63xx_irqs;
 597
 598 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 599 {
 600         return bcm63xx_irqs[irq];
 601 }
 602
 603 /*
 604  * return installed memory size
 605  */
 606 unsigned int bcm63xx_get_memory_size(void);
 607
 608 #endif /* !BCM63XX_CPU_H_ */