[brcm63xx] enable all blocks on 6338 and uart clock on 6345
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_regs.h
1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
3
4 /*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
7
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG 0x0
10 #define REV_CHIPID_SHIFT 16
11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT 0
13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
14
15 /* Clock Control register */
16 #define PERF_CKCTL_REG 0x4
17
18 #define CKCTL_6338_ENET_EN (1 << 4)
19 #define CKCTL_6338_USBS_EN (1 << 4)
20 #define CKCTL_6338_SAR_EN (1 << 5)
21 #define CKCTL_6338_SPI_EN (1 << 9)
22
23 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ENET_EN | \
24 CKCTL_6338_SAR_EN | \
25 CKCTL_6338_SPI_EN)
26
27 #define CKCTL_6345_CPU_EN (1 << 0)
28 #define CKCTL_6345_UART_EN (1 << 3)
29 #define CKCTL_6345_ENET_EN (1 << 7)
30 #define CKCTL_6345_USBH_EN (1 << 8)
31
32 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
33 #define CKCTL_6348_MPI_EN (1 << 1)
34 #define CKCTL_6348_SDRAM_EN (1 << 2)
35 #define CKCTL_6348_M2M_EN (1 << 3)
36 #define CKCTL_6348_ENET_EN (1 << 4)
37 #define CKCTL_6348_SAR_EN (1 << 5)
38 #define CKCTL_6348_USBS_EN (1 << 6)
39 #define CKCTL_6348_USBH_EN (1 << 8)
40 #define CKCTL_6348_SPI_EN (1 << 9)
41
42 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
43 CKCTL_6348_M2M_EN | \
44 CKCTL_6348_ENET_EN | \
45 CKCTL_6348_SAR_EN | \
46 CKCTL_6348_USBS_EN | \
47 CKCTL_6348_USBH_EN | \
48 CKCTL_6348_SPI_EN)
49
50 #define CKCTL_6358_ENET_EN (1 << 4)
51 #define CKCTL_6358_ADSLPHY_EN (1 << 5)
52 #define CKCTL_6358_PCM_EN (1 << 8)
53 #define CKCTL_6358_SPI_EN (1 << 9)
54 #define CKCTL_6358_USBS_EN (1 << 10)
55 #define CKCTL_6358_SAR_EN (1 << 11)
56 #define CKCTL_6358_EMUSB_EN (1 << 17)
57 #define CKCTL_6358_ENET0_EN (1 << 18)
58 #define CKCTL_6358_ENET1_EN (1 << 19)
59 #define CKCTL_6358_USBSU_EN (1 << 20)
60 #define CKCTL_6358_EPHY_EN (1 << 21)
61
62 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
63 CKCTL_6358_ADSLPHY_EN | \
64 CKCTL_6358_PCM_EN | \
65 CKCTL_6358_SPI_EN | \
66 CKCTL_6358_USBS_EN | \
67 CKCTL_6358_SAR_EN | \
68 CKCTL_6358_EMUSB_EN | \
69 CKCTL_6358_ENET0_EN | \
70 CKCTL_6358_ENET1_EN | \
71 CKCTL_6358_USBSU_EN | \
72 CKCTL_6358_EPHY_EN)
73
74 /* System PLL Control register */
75 #define PERF_SYS_PLL_CTL_REG 0x8
76 #define SYS_PLL_SOFT_RESET 0x1
77
78 /* Interrupt Mask register */
79 #define PERF_IRQMASK_REG 0xc
80 #define PERF_IRQSTAT_REG 0x10
81
82 /* Interrupt Status register */
83 #define PERF_IRQSTAT_REG 0x10
84
85 /* External Interrupt Configuration register */
86 #define PERF_EXTIRQ_CFG_REG 0x14
87 #define EXTIRQ_CFG_SENSE(x) (1 << (x))
88 #define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
89 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
90 #define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
91 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
92 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
93
94 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
95 #define EXTIRQ_CFG_MASK_ALL (0xf << 15)
96
97 /* Soft Reset register */
98 #define PERF_SOFTRESET_REG 0x28
99
100 #define SOFTRESET_6338_SPI_MASK (1 << 0)
101 #define SOFTRESET_6338_ENET_MASK (1 << 2)
102 #define SOFTRESET_6338_USBH_MASK (1 << 3)
103 #define SOFTRESET_6338_USBS_MASK (1 << 4)
104 #define SOFTRESET_6338_ADSL_MASK (1 << 5)
105 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
106 #define SOFTRESET_6338_SAR_MASK (1 << 7)
107 #define SOFTRESET_6338_ACLC_MASK (1 << 8)
108 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
109 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
110 SOFTRESET_6338_ENET_MASK | \
111 SOFTRESET_6338_USBH_MASK | \
112 SOFTRESET_6338_USBS_MASK | \
113 SOFTRESET_6338_ADSL_MASK | \
114 SOFTRESET_6338_DMAMEM_MASK | \
115 SOFTRESET_6338_SAR_MASK | \
116 SOFTRESET_6338_ACLC_MASK | \
117 SOFTRESET_6338_ADSLMIPSPLL_MASK)
118
119 #define SOFTRESET_6348_SPI_MASK (1 << 0)
120 #define SOFTRESET_6348_ENET_MASK (1 << 2)
121 #define SOFTRESET_6348_USBH_MASK (1 << 3)
122 #define SOFTRESET_6348_USBS_MASK (1 << 4)
123 #define SOFTRESET_6348_ADSL_MASK (1 << 5)
124 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
125 #define SOFTRESET_6348_SAR_MASK (1 << 7)
126 #define SOFTRESET_6348_ACLC_MASK (1 << 8)
127 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
128
129 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
130 SOFTRESET_6348_ENET_MASK | \
131 SOFTRESET_6348_USBH_MASK | \
132 SOFTRESET_6348_USBS_MASK | \
133 SOFTRESET_6348_ADSL_MASK | \
134 SOFTRESET_6348_DMAMEM_MASK | \
135 SOFTRESET_6348_SAR_MASK | \
136 SOFTRESET_6348_ACLC_MASK | \
137 SOFTRESET_6348_ADSLMIPSPLL_MASK)
138
139 /* MIPS PLL control register */
140 #define PERF_MIPSPLLCTL_REG 0x34
141 #define MIPSPLLCTL_N1_SHIFT 20
142 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
143 #define MIPSPLLCTL_N2_SHIFT 15
144 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
145 #define MIPSPLLCTL_M1REF_SHIFT 12
146 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
147 #define MIPSPLLCTL_M2REF_SHIFT 9
148 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
149 #define MIPSPLLCTL_M1CPU_SHIFT 6
150 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
151 #define MIPSPLLCTL_M1BUS_SHIFT 3
152 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
153 #define MIPSPLLCTL_M2BUS_SHIFT 0
154 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
155
156 /* ADSL PHY PLL Control register */
157 #define PERF_ADSLPLLCTL_REG 0x38
158 #define ADSLPLLCTL_N1_SHIFT 20
159 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
160 #define ADSLPLLCTL_N2_SHIFT 15
161 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
162 #define ADSLPLLCTL_M1REF_SHIFT 12
163 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
164 #define ADSLPLLCTL_M2REF_SHIFT 9
165 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
166 #define ADSLPLLCTL_M1CPU_SHIFT 6
167 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
168 #define ADSLPLLCTL_M1BUS_SHIFT 3
169 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
170 #define ADSLPLLCTL_M2BUS_SHIFT 0
171 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
172
173 #define ADSLPLLCTL_VAL(n1,n2,m1ref,m2ref,m1cpu,m1bus,m2bus) \
174 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
175 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
176 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
177 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
178 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
179 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
180 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
181
182
183 /*************************************************************************
184 * _REG relative to RSET_TIMER
185 *************************************************************************/
186
187 #define BCM63XX_TIMER_COUNT 4
188 #define TIMER_T0_ID 0
189 #define TIMER_T1_ID 1
190 #define TIMER_T2_ID 2
191 #define TIMER_WDT_ID 3
192
193 /* Timer irqstat register */
194 #define TIMER_IRQSTAT_REG 0
195 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
196 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
197 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
198 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
199 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
200 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
201 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
202 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
203 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
204
205 /* Timer control register */
206 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
207 #define TIMER_CTL0_REG 0x4
208 #define TIMER_CTL1_REG 0x8
209 #define TIMER_CTL2_REG 0xC
210 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
211 #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
212 #define TIMER_CTL_ENABLE_MASK (1 << 31)
213
214
215 /*************************************************************************
216 * _REG relative to RSET_WDT
217 *************************************************************************/
218
219 /* Watchdog default count register */
220 #define WDT_DEFVAL_REG 0x0
221
222 /* Watchdog control register */
223 #define WDT_CTL_REG 0x4
224
225 /* Watchdog control register constants */
226 #define WDT_START_1 (0xff00)
227 #define WDT_START_2 (0x00ff)
228 #define WDT_STOP_1 (0xee00)
229 #define WDT_STOP_2 (0x00ee)
230
231 /* Watchdog reset length register */
232 #define WDT_RSTLEN_REG 0x8
233
234
235 /*************************************************************************
236 * _REG relative to RSET_UARTx
237 *************************************************************************/
238
239 /* UART Control Register */
240 #define UART_CTL_REG 0x0
241 #define UART_CTL_RXTMOUTCNT_SHIFT 0
242 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
243 #define UART_CTL_RSTTXDN_SHIFT 5
244 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
245 #define UART_CTL_RSTRXFIFO_SHIFT 6
246 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
247 #define UART_CTL_RSTTXFIFO_SHIFT 7
248 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
249 #define UART_CTL_STOPBITS_SHIFT 8
250 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
251 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
252 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
253 #define UART_CTL_BITSPERSYM_SHIFT 12
254 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
255 #define UART_CTL_XMITBRK_SHIFT 14
256 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
257 #define UART_CTL_RSVD_SHIFT 15
258 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
259 #define UART_CTL_RXPAREVEN_SHIFT 16
260 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
261 #define UART_CTL_RXPAREN_SHIFT 17
262 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
263 #define UART_CTL_TXPAREVEN_SHIFT 18
264 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
265 #define UART_CTL_TXPAREN_SHIFT 18
266 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
267 #define UART_CTL_LOOPBACK_SHIFT 20
268 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
269 #define UART_CTL_RXEN_SHIFT 21
270 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
271 #define UART_CTL_TXEN_SHIFT 22
272 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
273 #define UART_CTL_BRGEN_SHIFT 23
274 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
275
276 /* UART Baudword register */
277 #define UART_BAUD_REG 0x4
278
279 /* UART Misc Control register */
280 #define UART_MCTL_REG 0x8
281 #define UART_MCTL_DTR_SHIFT 0
282 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
283 #define UART_MCTL_RTS_SHIFT 1
284 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
285 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
286 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
287 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
288 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
289 #define UART_MCTL_RXFIFOFILL_SHIFT 16
290 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
291 #define UART_MCTL_TXFIFOFILL_SHIFT 24
292 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
293
294 /* UART External Input Configuration register */
295 #define UART_EXTINP_REG 0xc
296 #define UART_EXTINP_RI_SHIFT 0
297 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
298 #define UART_EXTINP_CTS_SHIFT 1
299 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
300 #define UART_EXTINP_DCD_SHIFT 2
301 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
302 #define UART_EXTINP_DSR_SHIFT 3
303 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
304 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
305 #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
306 #define UART_EXTINP_IR_RI 0
307 #define UART_EXTINP_IR_CTS 1
308 #define UART_EXTINP_IR_DCD 2
309 #define UART_EXTINP_IR_DSR 3
310 #define UART_EXTINP_RI_NOSENSE_SHIFT 16
311 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
312 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
313 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
314 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
315 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
316 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
317 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
318
319 /* UART Interrupt register */
320 #define UART_IR_REG 0x10
321 #define UART_IR_MASK(x) (1 << (x + 16))
322 #define UART_IR_STAT(x) (1 << (x))
323 #define UART_IR_EXTIP 0
324 #define UART_IR_TXUNDER 1
325 #define UART_IR_TXOVER 2
326 #define UART_IR_TXTRESH 3
327 #define UART_IR_TXRDLATCH 4
328 #define UART_IR_TXEMPTY 5
329 #define UART_IR_RXUNDER 6
330 #define UART_IR_RXOVER 7
331 #define UART_IR_RXTIMEOUT 8
332 #define UART_IR_RXFULL 9
333 #define UART_IR_RXTHRESH 10
334 #define UART_IR_RXNOTEMPTY 11
335 #define UART_IR_RXFRAMEERR 12
336 #define UART_IR_RXPARERR 13
337 #define UART_IR_RXBRK 14
338 #define UART_IR_TXDONE 15
339
340 /* UART Fifo register */
341 #define UART_FIFO_REG 0x14
342 #define UART_FIFO_VALID_SHIFT 0
343 #define UART_FIFO_VALID_MASK 0xff
344 #define UART_FIFO_FRAMEERR_SHIFT 8
345 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
346 #define UART_FIFO_PARERR_SHIFT 9
347 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
348 #define UART_FIFO_BRKDET_SHIFT 10
349 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
350 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
351 UART_FIFO_PARERR_MASK | \
352 UART_FIFO_BRKDET_MASK)
353
354
355 /*************************************************************************
356 * _REG relative to RSET_GPIO
357 *************************************************************************/
358
359 /* GPIO registers */
360 #define GPIO_CTL_HI_REG 0x0
361 #define GPIO_CTL_LO_REG 0x4
362 #define GPIO_DATA_HI_REG 0x8
363 #define GPIO_DATA_LO_REG 0xC
364
365 /* GPIO mux registers and constants */
366 #define GPIO_MODE_REG 0x18
367
368 #define GPIO_MODE_6348_G4_DIAG 0x00090000
369 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
370 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
371 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
372 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
373 #define GPIO_MODE_6348_G3_DIAG 0x00009000
374 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
375 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
376 #define GPIO_MODE_6348_G2_DIAG 0x00000900
377 #define GPIO_MODE_6348_G2_PCI 0x00000500
378 #define GPIO_MODE_6348_G1_DIAG 0x00000090
379 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
380 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
381 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
382 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
383 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
384 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
385 #define GPIO_MODE_6348_G0_DIAG 0x00000009
386 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
387
388 #define GPIO_MODE_6358_EXTRACS (1 << 5)
389 #define GPIO_MODE_6358_UART1 (1 << 6)
390 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
391 #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
392 #define GPIO_MODE_6358_UTOPIA (1 << 12)
393
394
395 /*************************************************************************
396 * _REG relative to RSET_ENET
397 *************************************************************************/
398
399 /* Receiver Configuration register */
400 #define ENET_RXCFG_REG 0x0
401 #define ENET_RXCFG_ALLMCAST_SHIFT 1
402 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
403 #define ENET_RXCFG_PROMISC_SHIFT 3
404 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
405 #define ENET_RXCFG_LOOPBACK_SHIFT 4
406 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
407 #define ENET_RXCFG_ENFLOW_SHIFT 5
408 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
409
410 /* Receive Maximum Length register */
411 #define ENET_RXMAXLEN_REG 0x4
412 #define ENET_RXMAXLEN_SHIFT 0
413 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
414
415 /* Transmit Maximum Length register */
416 #define ENET_TXMAXLEN_REG 0x8
417 #define ENET_TXMAXLEN_SHIFT 0
418 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
419
420 /* MII Status/Control register */
421 #define ENET_MIISC_REG 0x10
422 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
423 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
424 #define ENET_MIISC_PREAMBLEEN_SHIFT 7
425 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
426
427 /* MII Data register */
428 #define ENET_MIIDATA_REG 0x14
429 #define ENET_MIIDATA_DATA_SHIFT 0
430 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
431 #define ENET_MIIDATA_TA_SHIFT 16
432 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
433 #define ENET_MIIDATA_REG_SHIFT 18
434 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
435 #define ENET_MIIDATA_PHYID_SHIFT 23
436 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
437 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
438 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
439
440 /* Ethernet Interrupt Mask register */
441 #define ENET_IRMASK_REG 0x18
442
443 /* Ethernet Interrupt register */
444 #define ENET_IR_REG 0x1c
445 #define ENET_IR_MII (1 << 0)
446 #define ENET_IR_MIB (1 << 1)
447 #define ENET_IR_FLOWC (1 << 2)
448
449 /* Ethernet Control register */
450 #define ENET_CTL_REG 0x2c
451 #define ENET_CTL_ENABLE_SHIFT 0
452 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
453 #define ENET_CTL_DISABLE_SHIFT 1
454 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
455 #define ENET_CTL_SRESET_SHIFT 2
456 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
457 #define ENET_CTL_EPHYSEL_SHIFT 3
458 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
459
460 /* Transmit Control register */
461 #define ENET_TXCTL_REG 0x30
462 #define ENET_TXCTL_FD_SHIFT 0
463 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
464
465 /* Transmit Watermask register */
466 #define ENET_TXWMARK_REG 0x34
467 #define ENET_TXWMARK_WM_SHIFT 0
468 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
469
470 /* MIB Control register */
471 #define ENET_MIBCTL_REG 0x38
472 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
473 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
474
475 /* Perfect Match Data Low register */
476 #define ENET_PML_REG(x) (0x58 + (x) * 8)
477 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
478 #define ENET_PMH_DATAVALID_SHIFT 16
479 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
480
481 /* MIB register */
482 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
483 #define ENET_MIB_REG_COUNT 55
484
485
486 /*************************************************************************
487 * _REG relative to RSET_ENETDMA
488 *************************************************************************/
489
490 /* Controller Configuration Register */
491 #define ENETDMA_CFG_REG (0x0)
492 #define ENETDMA_CFG_EN_SHIFT 0
493 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
494 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
495
496 /* Flow Control Descriptor Low Threshold register */
497 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
498
499 /* Flow Control Descriptor High Threshold register */
500 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
501
502 /* Flow Control Descriptor Buffer Alloca Threshold register */
503 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
504 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
505 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
506
507 /* Channel Configuration register */
508 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
509 #define ENETDMA_CHANCFG_EN_SHIFT 0
510 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
511 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
512 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
513
514 /* Interrupt Control/Status register */
515 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
516 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
517 #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
518 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
519
520 /* Interrupt Mask register */
521 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
522
523 /* Maximum Burst Length */
524 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
525
526 /* Ring Start Address register */
527 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
528
529 /* State Ram Word 2 */
530 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
531
532 /* State Ram Word 3 */
533 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
534
535 /* State Ram Word 4 */
536 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
537
538
539 /*************************************************************************
540 * _REG relative to RSET_OHCI_PRIV
541 *************************************************************************/
542
543 #define OHCI_PRIV_REG 0x0
544 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
545 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
546 #define OHCI_PRIV_REG_SWAP_SHIFT 3
547 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
548
549
550 /*************************************************************************
551 * _REG relative to RSET_USBH_PRIV
552 *************************************************************************/
553
554 #define USBH_PRIV_SWAP_REG 0x0
555 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
556 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
557 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
558 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
559 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
560 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
561 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
562 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
563
564 #define USBH_PRIV_TEST_REG 0x24
565
566
567 /*************************************************************************
568 * _REG relative to RSET_MPI
569 *************************************************************************/
570
571 /* well known (hard wired) chip select */
572 #define MPI_CS_PCMCIA_COMMON 4
573 #define MPI_CS_PCMCIA_ATTR 5
574 #define MPI_CS_PCMCIA_IO 6
575
576 /* Chip select base register */
577 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
578 #define MPI_CSBASE_BASE_SHIFT 13
579 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
580 #define MPI_CSBASE_SIZE_SHIFT 0
581 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
582
583 #define MPI_CSBASE_SIZE_8K 0
584 #define MPI_CSBASE_SIZE_16K 1
585 #define MPI_CSBASE_SIZE_32K 2
586 #define MPI_CSBASE_SIZE_64K 3
587 #define MPI_CSBASE_SIZE_128K 4
588 #define MPI_CSBASE_SIZE_256K 5
589 #define MPI_CSBASE_SIZE_512K 6
590 #define MPI_CSBASE_SIZE_1M 7
591 #define MPI_CSBASE_SIZE_2M 8
592 #define MPI_CSBASE_SIZE_4M 9
593 #define MPI_CSBASE_SIZE_8M 10
594 #define MPI_CSBASE_SIZE_16M 11
595 #define MPI_CSBASE_SIZE_32M 12
596 #define MPI_CSBASE_SIZE_64M 13
597 #define MPI_CSBASE_SIZE_128M 14
598 #define MPI_CSBASE_SIZE_256M 15
599
600 /* Chip select control register */
601 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
602 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
603 #define MPI_CSCTL_WAIT_SHIFT 1
604 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
605 #define MPI_CSCTL_DATA16_MASK (1 << 4)
606 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
607 #define MPI_CSCTL_TSIZE_MASK (1 << 8)
608 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
609 #define MPI_CSCTL_SETUP_SHIFT 16
610 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
611 #define MPI_CSCTL_HOLD_SHIFT 20
612 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
613
614 /* PCI registers */
615 #define MPI_SP0_RANGE_REG 0x100
616 #define MPI_SP0_REMAP_REG 0x104
617 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
618 #define MPI_SP1_RANGE_REG 0x10C
619 #define MPI_SP1_REMAP_REG 0x110
620 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
621
622 #define MPI_L2PCFG_REG 0x11C
623 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
624 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
625 #define MPI_L2PCFG_REG_SHIFT 2
626 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
627 #define MPI_L2PCFG_FUNC_SHIFT 8
628 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
629 #define MPI_L2PCFG_DEVNUM_SHIFT 11
630 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
631 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
632 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
633
634 #define MPI_L2PMEMRANGE1_REG 0x120
635 #define MPI_L2PMEMBASE1_REG 0x124
636 #define MPI_L2PMEMREMAP1_REG 0x128
637 #define MPI_L2PMEMRANGE2_REG 0x12C
638 #define MPI_L2PMEMBASE2_REG 0x130
639 #define MPI_L2PMEMREMAP2_REG 0x134
640 #define MPI_L2PIORANGE_REG 0x138
641 #define MPI_L2PIOBASE_REG 0x13C
642 #define MPI_L2PIOREMAP_REG 0x140
643 #define MPI_L2P_BASE_MASK (0xffff8000)
644 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
645 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
646
647 #define MPI_PCIMODESEL_REG 0x144
648 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
649 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
650 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
651 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
652 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
653
654 #define MPI_LOCBUSCTL_REG 0x14C
655 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
656 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
657
658 #define MPI_LOCINT_REG 0x150
659 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
660 #define MPI_LOCINT_STAT(x) (1 << (x))
661 #define MPI_LOCINT_DIR_FAILED 6
662 #define MPI_LOCINT_EXT_PCI_INT 7
663 #define MPI_LOCINT_SERR 8
664 #define MPI_LOCINT_CSERR 9
665
666 #define MPI_PCICFGCTL_REG 0x178
667 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
668 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
669 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
670
671 #define MPI_PCICFGDATA_REG 0x17C
672
673 /* PCI host bridge custom register */
674 #define BCMPCI_REG_TIMERS 0x40
675 #define REG_TIMER_TRDY_SHIFT 0
676 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
677 #define REG_TIMER_RETRY_SHIFT 8
678 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
679
680
681 /*************************************************************************
682 * _REG relative to RSET_PCMCIA
683 *************************************************************************/
684
685 #define PCMCIA_C1_REG 0x0
686 #define PCMCIA_C1_CD1_MASK (1 << 0)
687 #define PCMCIA_C1_CD2_MASK (1 << 1)
688 #define PCMCIA_C1_VS1_MASK (1 << 2)
689 #define PCMCIA_C1_VS2_MASK (1 << 3)
690 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
691 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
692 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
693 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
694 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
695 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
696 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
697 #define PCMCIA_C1_RESET_MASK (1 << 18)
698
699 #define PCMCIA_C2_REG 0x8
700 #define PCMCIA_C2_DATA16_MASK (1 << 0)
701 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
702 #define PCMCIA_C2_RWCOUNT_SHIFT 2
703 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
704 #define PCMCIA_C2_INACTIVE_SHIFT 8
705 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
706 #define PCMCIA_C2_SETUP_SHIFT 16
707 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
708 #define PCMCIA_C2_HOLD_SHIFT 24
709 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
710
711
712 /*************************************************************************
713 * _REG relative to RSET_SDRAM
714 *************************************************************************/
715
716 #define SDRAM_CFG_REG 0x0
717 #define SDRAM_CFG_ROW_SHIFT 4
718 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
719 #define SDRAM_CFG_COL_SHIFT 6
720 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
721 #define SDRAM_CFG_32B_SHIFT 10
722 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
723 #define SDRAM_CFG_BANK_SHIFT 13
724 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
725
726 #define SDRAM_PRIO_REG 0x2C
727 #define SDRAM_PRIO_MIPS_SHIFT 29
728 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
729 #define SDRAM_PRIO_ADSL_SHIFT 30
730 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
731 #define SDRAM_PRIO_EN_SHIFT 31
732 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
733
734
735 /*************************************************************************
736 * _REG relative to RSET_MEMC
737 *************************************************************************/
738
739 #define MEMC_CFG_REG 0x4
740 #define MEMC_CFG_32B_SHIFT 1
741 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
742 #define MEMC_CFG_COL_SHIFT 3
743 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
744 #define MEMC_CFG_ROW_SHIFT 6
745 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
746
747
748 /*************************************************************************
749 * _REG relative to RSET_DDR
750 *************************************************************************/
751
752 #define DDR_DMIPSPLLCFG_REG 0x18
753 #define DMIPSPLLCFG_M1_SHIFT 0
754 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
755 #define DMIPSPLLCFG_N1_SHIFT 23
756 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
757 #define DMIPSPLLCFG_N2_SHIFT 29
758 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
759
760 /*************************************************************************
761 * _REG relative to RSET_SPI
762 *************************************************************************/
763
764 /* BCM 6338 SPI core */
765 #define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
766 #define SPI_BCM_6338_SPI_INT_STATUS 0x02
767 #define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
768 #define SPI_BCM_6338_SPI_INT_MASK 0x04
769 #define SPI_BCM_6338_SPI_ST 0x05
770 #define SPI_BCM_6338_SPI_CLK_CFG 0x06
771 #define SPI_BCM_6338_SPI_FILL_BYTE 0x07
772 #define SPI_BCM_6338_SPI_MSG_TAIL 0x09
773 #define SPI_BCM_6338_SPI_RX_TAIL 0x0b
774 #define SPI_BCM_6338_SPI_MSG_CTL 0x40
775 #define SPI_BCM_6338_SPI_MSG_DATA 0x41
776 #define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
777 #define SPI_BCM_6338_SPI_RX_DATA 0x80
778 #define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
779
780 /* BCM 6348 SPI core */
781 #define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
782 #define SPI_BCM_6348_SPI_INT_STATUS 0x01
783 #define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
784 #define SPI_BCM_6348_SPI_FILL_BYTE 0x04
785 #define SPI_BCM_6348_SPI_CLK_CFG 0x05
786 #define SPI_BCM_6348_SPI_ST 0x06
787 #define SPI_BCM_6348_SPI_INT_MASK 0x07
788 #define SPI_BCM_6348_SPI_RX_TAIL 0x08
789 #define SPI_BCM_6348_SPI_MSG_TAIL 0x10
790 #define SPI_BCM_6348_SPI_MSG_DATA 0x40
791 #define SPI_BCM_6348_SPI_MSG_CTL 0x42
792 #define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
793 #define SPI_BCM_6348_SPI_RX_DATA 0x80
794 #define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
795
796 /* BCM 6358 SPI core */
797 #define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
798
799 #define SPI_BCM_6358_SPI_MSG_DATA 0x02
800 #define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
801
802 #define SPI_BCM_6358_SPI_RX_DATA 0x400
803 #define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
804
805 #define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
806
807 #define SPI_BCM_6358_SPI_INT_STATUS 0x702
808 #define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
809
810 #define SPI_BCM_6358_SPI_INT_MASK 0x704
811
812 #define SPI_BCM_6358_SPI_STATUS 0x705
813
814 #define SPI_BCM_6358_SPI_CLK_CFG 0x706
815
816 #define SPI_BCM_6358_SPI_FILL_BYTE 0x707
817 #define SPI_BCM_6358_SPI_MSG_TAIL 0x709
818 #define SPI_BCM_6358_SPI_RX_TAIL 0x70B
819
820 /* Shared SPI definitions */
821
822 /* Message configuration */
823 #define SPI_FD_RW 0x00
824 #define SPI_HD_W 0x01
825 #define SPI_HD_R 0x02
826 #define SPI_BYTE_CNT_SHIFT 0
827 #define SPI_MSG_TYPE_SHIFT 14
828
829 /* Command */
830 #define SPI_CMD_NOOP 0x01
831 #define SPI_CMD_SOFT_RESET 0x02
832 #define SPI_CMD_HARD_RESET 0x04
833 #define SPI_CMD_START_IMMEDIATE 0x08
834 #define SPI_CMD_COMMAND_SHIFT 0
835 #define SPI_CMD_COMMAND_MASK 0x000f
836 #define SPI_CMD_DEVICE_ID_SHIFT 4
837 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
838 #define SPI_CMD_ONE_BYTE_SHIFT 11
839 #define SPI_CMD_ONE_WIRE_SHIFT 12
840 #define SPI_DEV_ID_0 0
841 #define SPI_DEV_ID_1 1
842 #define SPI_DEV_ID_2 2
843 #define SPI_DEV_ID_3 3
844
845 /* Interrupt mask */
846 #define SPI_INTR_CMD_DONE 0x01
847 #define SPI_INTR_RX_OVERFLOW 0x02
848 #define SPI_INTR_TX_UNDERFLOW 0x04
849 #define SPI_INTR_TX_OVERFLOW 0x08
850 #define SPI_INTR_RX_UNDERFLOW 0x10
851 #define SPI_INTR_CLEAR_ALL 0x1f
852
853 /* Status */
854 #define SPI_RX_EMPTY 0x02
855 #define SPI_CMD_BUSY 0x04
856 #define SPI_SERIAL_BUSY 0x08
857
858 /* Clock configuration */
859 #define SPI_CLK_20MHZ 0x00
860 #define SPI_CLK_0_391MHZ 0x01
861 #define SPI_CLK_0_781MHZ 0x02 /* default */
862 #define SPI_CLK_1_563MHZ 0x03
863 #define SPI_CLK_3_125MHZ 0x04
864 #define SPI_CLK_6_250MHZ 0x05
865 #define SPI_CLK_12_50MHZ 0x06
866 #define SPI_CLK_25MHZ 0x07
867 #define SPI_CLK_MASK 0x07
868 #define SPI_SSOFFTIME_MASK 0x38
869 #define SPI_SSOFFTIME_SHIFT 3
870 #define SPI_BYTE_SWAP 0x80
871
872
873 #endif /* BCM63XX_REGS_H_ */