6323e45dd968d4fd24432facbde15ef30224841a
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / files / include / asm-mips / mach-bcm63xx / bcm63xx_regs.h
1 #ifndef BCM63XX_REGS_H_
2 #define BCM63XX_REGS_H_
3
4 /*************************************************************************
5 * _REG relative to RSET_PERF
6 *************************************************************************/
7
8 /* Chip Identifier / Revision register */
9 #define PERF_REV_REG 0x0
10 #define REV_CHIPID_SHIFT 16
11 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
12 #define REV_REVID_SHIFT 0
13 #define REV_REVID_MASK (0xffff << REV_REVID_SHIFT)
14
15 /* Clock Control register */
16 #define PERF_CKCTL_REG 0x4
17
18 #define CKCTL_6338_ENET_EN (1 << 4)
19 #define CKCTL_6338_USBS_EN (1 << 4)
20 #define CKCTL_6338_SAR_EN (1 << 5)
21 #define CKCTL_6338_SPI_EN (1 << 9)
22
23 #define CKCTL_6338_ALL_SAFE_EN (CKCTL_6338_ENET_EN | \
24 CKCTL_6338_SAR_EN | \
25 CKCTL_6338_SPI_EN)
26
27 #define CKCTL_6348_ADSLPHY_EN (1 << 0)
28 #define CKCTL_6348_MPI_EN (1 << 1)
29 #define CKCTL_6348_SDRAM_EN (1 << 2)
30 #define CKCTL_6348_M2M_EN (1 << 3)
31 #define CKCTL_6348_ENET_EN (1 << 4)
32 #define CKCTL_6348_SAR_EN (1 << 5)
33 #define CKCTL_6348_USBS_EN (1 << 6)
34 #define CKCTL_6348_USBH_EN (1 << 8)
35 #define CKCTL_6348_SPI_EN (1 << 9)
36
37 #define CKCTL_6348_ALL_SAFE_EN (CKCTL_6348_ADSLPHY_EN | \
38 CKCTL_6348_M2M_EN | \
39 CKCTL_6348_ENET_EN | \
40 CKCTL_6348_SAR_EN | \
41 CKCTL_6348_USBS_EN | \
42 CKCTL_6348_USBH_EN | \
43 CKCTL_6348_SPI_EN)
44
45 #define CKCTL_6358_ENET_EN (1 << 4)
46 #define CKCTL_6358_ADSLPHY_EN (1 << 5)
47 #define CKCTL_6358_PCM_EN (1 << 8)
48 #define CKCTL_6358_SPI_EN (1 << 9)
49 #define CKCTL_6358_USBS_EN (1 << 10)
50 #define CKCTL_6358_SAR_EN (1 << 11)
51 #define CKCTL_6358_EMUSB_EN (1 << 17)
52 #define CKCTL_6358_ENET0_EN (1 << 18)
53 #define CKCTL_6358_ENET1_EN (1 << 19)
54 #define CKCTL_6358_USBSU_EN (1 << 20)
55 #define CKCTL_6358_EPHY_EN (1 << 21)
56
57 #define CKCTL_6358_ALL_SAFE_EN (CKCTL_6358_ENET_EN | \
58 CKCTL_6358_ADSLPHY_EN | \
59 CKCTL_6358_PCM_EN | \
60 CKCTL_6358_SPI_EN | \
61 CKCTL_6358_USBS_EN | \
62 CKCTL_6358_SAR_EN | \
63 CKCTL_6358_EMUSB_EN | \
64 CKCTL_6358_ENET0_EN | \
65 CKCTL_6358_ENET1_EN | \
66 CKCTL_6358_USBSU_EN | \
67 CKCTL_6358_EPHY_EN)
68
69 /* System PLL Control register */
70 #define PERF_SYS_PLL_CTL_REG 0x8
71 #define SYS_PLL_SOFT_RESET 0x1
72
73 /* Interrupt Mask register */
74 #define PERF_IRQMASK_REG 0xc
75 #define PERF_IRQSTAT_REG 0x10
76
77 /* Interrupt Status register */
78 #define PERF_IRQSTAT_REG 0x10
79
80 /* External Interrupt Configuration register */
81 #define PERF_EXTIRQ_CFG_REG 0x14
82 #define EXTIRQ_CFG_SENSE(x) (1 << (x))
83 #define EXTIRQ_CFG_STAT(x) (1 << (x + 5))
84 #define EXTIRQ_CFG_CLEAR(x) (1 << (x + 10))
85 #define EXTIRQ_CFG_MASK(x) (1 << (x + 15))
86 #define EXTIRQ_CFG_BOTHEDGE(x) (1 << (x + 20))
87 #define EXTIRQ_CFG_LEVELSENSE(x) (1 << (x + 25))
88
89 #define EXTIRQ_CFG_CLEAR_ALL (0xf << 10)
90 #define EXTIRQ_CFG_MASK_ALL (0xf << 15)
91
92 /* Soft Reset register */
93 #define PERF_SOFTRESET_REG 0x28
94
95 #define SOFTRESET_6338_SPI_MASK (1 << 0)
96 #define SOFTRESET_6338_ENET_MASK (1 << 2)
97 #define SOFTRESET_6338_USBH_MASK (1 << 3)
98 #define SOFTRESET_6338_USBS_MASK (1 << 4)
99 #define SOFTRESET_6338_ADSL_MASK (1 << 5)
100 #define SOFTRESET_6338_DMAMEM_MASK (1 << 6)
101 #define SOFTRESET_6338_SAR_MASK (1 << 7)
102 #define SOFTRESET_6338_ACLC_MASK (1 << 8)
103 #define SOFTRESET_6338_ADSLMIPSPLL_MASK (1 << 10)
104 #define SOFTRESET_6338_ALL (SOFTRESET_6338_SPI_MASK | \
105 SOFTRESET_6338_ENET_MASK | \
106 SOFTRESET_6338_USBH_MASK | \
107 SOFTRESET_6338_USBS_MASK | \
108 SOFTRESET_6338_ADSL_MASK | \
109 SOFTRESET_6338_DMAMEM_MASK | \
110 SOFTRESET_6338_SAR_MASK | \
111 SOFTRESET_6338_ACLC_MASK | \
112 SOFTRESET_6338_ADSLMIPSPLL_MASK)
113
114 #define SOFTRESET_6348_SPI_MASK (1 << 0)
115 #define SOFTRESET_6348_ENET_MASK (1 << 2)
116 #define SOFTRESET_6348_USBH_MASK (1 << 3)
117 #define SOFTRESET_6348_USBS_MASK (1 << 4)
118 #define SOFTRESET_6348_ADSL_MASK (1 << 5)
119 #define SOFTRESET_6348_DMAMEM_MASK (1 << 6)
120 #define SOFTRESET_6348_SAR_MASK (1 << 7)
121 #define SOFTRESET_6348_ACLC_MASK (1 << 8)
122 #define SOFTRESET_6348_ADSLMIPSPLL_MASK (1 << 10)
123
124 #define SOFTRESET_6348_ALL (SOFTRESET_6348_SPI_MASK | \
125 SOFTRESET_6348_ENET_MASK | \
126 SOFTRESET_6348_USBH_MASK | \
127 SOFTRESET_6348_USBS_MASK | \
128 SOFTRESET_6348_ADSL_MASK | \
129 SOFTRESET_6348_DMAMEM_MASK | \
130 SOFTRESET_6348_SAR_MASK | \
131 SOFTRESET_6348_ACLC_MASK | \
132 SOFTRESET_6348_ADSLMIPSPLL_MASK)
133
134 /* MIPS PLL control register */
135 #define PERF_MIPSPLLCTL_REG 0x34
136 #define MIPSPLLCTL_N1_SHIFT 20
137 #define MIPSPLLCTL_N1_MASK (0x7 << MIPSPLLCTL_N1_SHIFT)
138 #define MIPSPLLCTL_N2_SHIFT 15
139 #define MIPSPLLCTL_N2_MASK (0x1f << MIPSPLLCTL_N2_SHIFT)
140 #define MIPSPLLCTL_M1REF_SHIFT 12
141 #define MIPSPLLCTL_M1REF_MASK (0x7 << MIPSPLLCTL_M1REF_SHIFT)
142 #define MIPSPLLCTL_M2REF_SHIFT 9
143 #define MIPSPLLCTL_M2REF_MASK (0x7 << MIPSPLLCTL_M2REF_SHIFT)
144 #define MIPSPLLCTL_M1CPU_SHIFT 6
145 #define MIPSPLLCTL_M1CPU_MASK (0x7 << MIPSPLLCTL_M1CPU_SHIFT)
146 #define MIPSPLLCTL_M1BUS_SHIFT 3
147 #define MIPSPLLCTL_M1BUS_MASK (0x7 << MIPSPLLCTL_M1BUS_SHIFT)
148 #define MIPSPLLCTL_M2BUS_SHIFT 0
149 #define MIPSPLLCTL_M2BUS_MASK (0x7 << MIPSPLLCTL_M2BUS_SHIFT)
150
151 /* ADSL PHY PLL Control register */
152 #define PERF_ADSLPLLCTL_REG 0x38
153 #define ADSLPLLCTL_N1_SHIFT 20
154 #define ADSLPLLCTL_N1_MASK (0x7 << ADSLPLLCTL_N1_SHIFT)
155 #define ADSLPLLCTL_N2_SHIFT 15
156 #define ADSLPLLCTL_N2_MASK (0x1f << ADSLPLLCTL_N2_SHIFT)
157 #define ADSLPLLCTL_M1REF_SHIFT 12
158 #define ADSLPLLCTL_M1REF_MASK (0x7 << ADSLPLLCTL_M1REF_SHIFT)
159 #define ADSLPLLCTL_M2REF_SHIFT 9
160 #define ADSLPLLCTL_M2REF_MASK (0x7 << ADSLPLLCTL_M2REF_SHIFT)
161 #define ADSLPLLCTL_M1CPU_SHIFT 6
162 #define ADSLPLLCTL_M1CPU_MASK (0x7 << ADSLPLLCTL_M1CPU_SHIFT)
163 #define ADSLPLLCTL_M1BUS_SHIFT 3
164 #define ADSLPLLCTL_M1BUS_MASK (0x7 << ADSLPLLCTL_M1BUS_SHIFT)
165 #define ADSLPLLCTL_M2BUS_SHIFT 0
166 #define ADSLPLLCTL_M2BUS_MASK (0x7 << ADSLPLLCTL_M2BUS_SHIFT)
167
168 #define ADSLPLLCTL_VAL(n1,n2,m1ref,m2ref,m1cpu,m1bus,m2bus) \
169 (((n1) << ADSLPLLCTL_N1_SHIFT) | \
170 ((n2) << ADSLPLLCTL_N2_SHIFT) | \
171 ((m1ref) << ADSLPLLCTL_M1REF_SHIFT) | \
172 ((m2ref) << ADSLPLLCTL_M2REF_SHIFT) | \
173 ((m1cpu) << ADSLPLLCTL_M1CPU_SHIFT) | \
174 ((m1bus) << ADSLPLLCTL_M1BUS_SHIFT) | \
175 ((m2bus) << ADSLPLLCTL_M2BUS_SHIFT))
176
177
178 /*************************************************************************
179 * _REG relative to RSET_TIMER
180 *************************************************************************/
181
182 #define BCM63XX_TIMER_COUNT 4
183 #define TIMER_T0_ID 0
184 #define TIMER_T1_ID 1
185 #define TIMER_T2_ID 2
186 #define TIMER_WDT_ID 3
187
188 /* Timer irqstat register */
189 #define TIMER_IRQSTAT_REG 0
190 #define TIMER_IRQSTAT_TIMER_CAUSE(x) (1 << (x))
191 #define TIMER_IRQSTAT_TIMER0_CAUSE (1 << 0)
192 #define TIMER_IRQSTAT_TIMER1_CAUSE (1 << 1)
193 #define TIMER_IRQSTAT_TIMER2_CAUSE (1 << 2)
194 #define TIMER_IRQSTAT_WDT_CAUSE (1 << 3)
195 #define TIMER_IRQSTAT_TIMER_IR_EN(x) (1 << ((x) + 8))
196 #define TIMER_IRQSTAT_TIMER0_IR_EN (1 << 8)
197 #define TIMER_IRQSTAT_TIMER1_IR_EN (1 << 9)
198 #define TIMER_IRQSTAT_TIMER2_IR_EN (1 << 10)
199
200 /* Timer control register */
201 #define TIMER_CTLx_REG(x) (0x4 + (x * 4))
202 #define TIMER_CTL0_REG 0x4
203 #define TIMER_CTL1_REG 0x8
204 #define TIMER_CTL2_REG 0xC
205 #define TIMER_CTL_COUNTDOWN_MASK (0x3fffffff)
206 #define TIMER_CTL_MONOTONIC_MASK (1 << 30)
207 #define TIMER_CTL_ENABLE_MASK (1 << 31)
208
209
210 /*************************************************************************
211 * _REG relative to RSET_WDT
212 *************************************************************************/
213
214 /* Watchdog default count register */
215 #define WDT_DEFVAL_REG 0x0
216
217 /* Watchdog control register */
218 #define WDT_CTL_REG 0x4
219
220 /* Watchdog control register constants */
221 #define WDT_START_1 (0xff00)
222 #define WDT_START_2 (0x00ff)
223 #define WDT_STOP_1 (0xee00)
224 #define WDT_STOP_2 (0x00ee)
225
226 /* Watchdog reset length register */
227 #define WDT_RSTLEN_REG 0x8
228
229
230 /*************************************************************************
231 * _REG relative to RSET_UARTx
232 *************************************************************************/
233
234 /* UART Control Register */
235 #define UART_CTL_REG 0x0
236 #define UART_CTL_RXTMOUTCNT_SHIFT 0
237 #define UART_CTL_RXTMOUTCNT_MASK (0x1f << UART_CTL_RXTMOUTCNT_SHIFT)
238 #define UART_CTL_RSTTXDN_SHIFT 5
239 #define UART_CTL_RSTTXDN_MASK (1 << UART_CTL_RSTTXDN_SHIFT)
240 #define UART_CTL_RSTRXFIFO_SHIFT 6
241 #define UART_CTL_RSTRXFIFO_MASK (1 << UART_CTL_RSTRXFIFO_SHIFT)
242 #define UART_CTL_RSTTXFIFO_SHIFT 7
243 #define UART_CTL_RSTTXFIFO_MASK (1 << UART_CTL_RSTTXFIFO_SHIFT)
244 #define UART_CTL_STOPBITS_SHIFT 8
245 #define UART_CTL_STOPBITS_MASK (0xf << UART_CTL_STOPBITS_SHIFT)
246 #define UART_CTL_STOPBITS_1 (0x7 << UART_CTL_STOPBITS_SHIFT)
247 #define UART_CTL_STOPBITS_2 (0xf << UART_CTL_STOPBITS_SHIFT)
248 #define UART_CTL_BITSPERSYM_SHIFT 12
249 #define UART_CTL_BITSPERSYM_MASK (0x3 << UART_CTL_BITSPERSYM_SHIFT)
250 #define UART_CTL_XMITBRK_SHIFT 14
251 #define UART_CTL_XMITBRK_MASK (1 << UART_CTL_XMITBRK_SHIFT)
252 #define UART_CTL_RSVD_SHIFT 15
253 #define UART_CTL_RSVD_MASK (1 << UART_CTL_RSVD_SHIFT)
254 #define UART_CTL_RXPAREVEN_SHIFT 16
255 #define UART_CTL_RXPAREVEN_MASK (1 << UART_CTL_RXPAREVEN_SHIFT)
256 #define UART_CTL_RXPAREN_SHIFT 17
257 #define UART_CTL_RXPAREN_MASK (1 << UART_CTL_RXPAREN_SHIFT)
258 #define UART_CTL_TXPAREVEN_SHIFT 18
259 #define UART_CTL_TXPAREVEN_MASK (1 << UART_CTL_TXPAREVEN_SHIFT)
260 #define UART_CTL_TXPAREN_SHIFT 18
261 #define UART_CTL_TXPAREN_MASK (1 << UART_CTL_TXPAREN_SHIFT)
262 #define UART_CTL_LOOPBACK_SHIFT 20
263 #define UART_CTL_LOOPBACK_MASK (1 << UART_CTL_LOOPBACK_SHIFT)
264 #define UART_CTL_RXEN_SHIFT 21
265 #define UART_CTL_RXEN_MASK (1 << UART_CTL_RXEN_SHIFT)
266 #define UART_CTL_TXEN_SHIFT 22
267 #define UART_CTL_TXEN_MASK (1 << UART_CTL_TXEN_SHIFT)
268 #define UART_CTL_BRGEN_SHIFT 23
269 #define UART_CTL_BRGEN_MASK (1 << UART_CTL_BRGEN_SHIFT)
270
271 /* UART Baudword register */
272 #define UART_BAUD_REG 0x4
273
274 /* UART Misc Control register */
275 #define UART_MCTL_REG 0x8
276 #define UART_MCTL_DTR_SHIFT 0
277 #define UART_MCTL_DTR_MASK (1 << UART_MCTL_DTR_SHIFT)
278 #define UART_MCTL_RTS_SHIFT 1
279 #define UART_MCTL_RTS_MASK (1 << UART_MCTL_RTS_SHIFT)
280 #define UART_MCTL_RXFIFOTHRESH_SHIFT 8
281 #define UART_MCTL_RXFIFOTHRESH_MASK (0xf << UART_MCTL_RXFIFOTHRESH_SHIFT)
282 #define UART_MCTL_TXFIFOTHRESH_SHIFT 12
283 #define UART_MCTL_TXFIFOTHRESH_MASK (0xf << UART_MCTL_TXFIFOTHRESH_SHIFT)
284 #define UART_MCTL_RXFIFOFILL_SHIFT 16
285 #define UART_MCTL_RXFIFOFILL_MASK (0x1f << UART_MCTL_RXFIFOFILL_SHIFT)
286 #define UART_MCTL_TXFIFOFILL_SHIFT 24
287 #define UART_MCTL_TXFIFOFILL_MASK (0x1f << UART_MCTL_TXFIFOFILL_SHIFT)
288
289 /* UART External Input Configuration register */
290 #define UART_EXTINP_REG 0xc
291 #define UART_EXTINP_RI_SHIFT 0
292 #define UART_EXTINP_RI_MASK (1 << UART_EXTINP_RI_SHIFT)
293 #define UART_EXTINP_CTS_SHIFT 1
294 #define UART_EXTINP_CTS_MASK (1 << UART_EXTINP_CTS_SHIFT)
295 #define UART_EXTINP_DCD_SHIFT 2
296 #define UART_EXTINP_DCD_MASK (1 << UART_EXTINP_DCD_SHIFT)
297 #define UART_EXTINP_DSR_SHIFT 3
298 #define UART_EXTINP_DSR_MASK (1 << UART_EXTINP_DSR_SHIFT)
299 #define UART_EXTINP_IRSTAT(x) (1 << (x + 4))
300 #define UART_EXTINP_IRMASK(x) (1 << (x + 8))
301 #define UART_EXTINP_IR_RI 0
302 #define UART_EXTINP_IR_CTS 1
303 #define UART_EXTINP_IR_DCD 2
304 #define UART_EXTINP_IR_DSR 3
305 #define UART_EXTINP_RI_NOSENSE_SHIFT 16
306 #define UART_EXTINP_RI_NOSENSE_MASK (1 << UART_EXTINP_RI_NOSENSE_SHIFT)
307 #define UART_EXTINP_CTS_NOSENSE_SHIFT 17
308 #define UART_EXTINP_CTS_NOSENSE_MASK (1 << UART_EXTINP_CTS_NOSENSE_SHIFT)
309 #define UART_EXTINP_DCD_NOSENSE_SHIFT 18
310 #define UART_EXTINP_DCD_NOSENSE_MASK (1 << UART_EXTINP_DCD_NOSENSE_SHIFT)
311 #define UART_EXTINP_DSR_NOSENSE_SHIFT 19
312 #define UART_EXTINP_DSR_NOSENSE_MASK (1 << UART_EXTINP_DSR_NOSENSE_SHIFT)
313
314 /* UART Interrupt register */
315 #define UART_IR_REG 0x10
316 #define UART_IR_MASK(x) (1 << (x + 16))
317 #define UART_IR_STAT(x) (1 << (x))
318 #define UART_IR_EXTIP 0
319 #define UART_IR_TXUNDER 1
320 #define UART_IR_TXOVER 2
321 #define UART_IR_TXTRESH 3
322 #define UART_IR_TXRDLATCH 4
323 #define UART_IR_TXEMPTY 5
324 #define UART_IR_RXUNDER 6
325 #define UART_IR_RXOVER 7
326 #define UART_IR_RXTIMEOUT 8
327 #define UART_IR_RXFULL 9
328 #define UART_IR_RXTHRESH 10
329 #define UART_IR_RXNOTEMPTY 11
330 #define UART_IR_RXFRAMEERR 12
331 #define UART_IR_RXPARERR 13
332 #define UART_IR_RXBRK 14
333 #define UART_IR_TXDONE 15
334
335 /* UART Fifo register */
336 #define UART_FIFO_REG 0x14
337 #define UART_FIFO_VALID_SHIFT 0
338 #define UART_FIFO_VALID_MASK 0xff
339 #define UART_FIFO_FRAMEERR_SHIFT 8
340 #define UART_FIFO_FRAMEERR_MASK (1 << UART_FIFO_FRAMEERR_SHIFT)
341 #define UART_FIFO_PARERR_SHIFT 9
342 #define UART_FIFO_PARERR_MASK (1 << UART_FIFO_PARERR_SHIFT)
343 #define UART_FIFO_BRKDET_SHIFT 10
344 #define UART_FIFO_BRKDET_MASK (1 << UART_FIFO_BRKDET_SHIFT)
345 #define UART_FIFO_ANYERR_MASK (UART_FIFO_FRAMEERR_MASK | \
346 UART_FIFO_PARERR_MASK | \
347 UART_FIFO_BRKDET_MASK)
348
349
350 /*************************************************************************
351 * _REG relative to RSET_GPIO
352 *************************************************************************/
353
354 /* GPIO registers */
355 #define GPIO_CTL_HI_REG 0x0
356 #define GPIO_CTL_LO_REG 0x4
357 #define GPIO_DATA_HI_REG 0x8
358 #define GPIO_DATA_LO_REG 0xC
359
360 /* GPIO mux registers and constants */
361 #define GPIO_MODE_REG 0x18
362
363 #define GPIO_MODE_6348_G4_DIAG 0x00090000
364 #define GPIO_MODE_6348_G4_UTOPIA 0x00080000
365 #define GPIO_MODE_6348_G4_LEGACY_LED 0x00030000
366 #define GPIO_MODE_6348_G4_MII_SNOOP 0x00020000
367 #define GPIO_MODE_6348_G4_EXT_EPHY 0x00010000
368 #define GPIO_MODE_6348_G3_DIAG 0x00009000
369 #define GPIO_MODE_6348_G3_UTOPIA 0x00008000
370 #define GPIO_MODE_6348_G3_EXT_MII 0x00007000
371 #define GPIO_MODE_6348_G2_DIAG 0x00000900
372 #define GPIO_MODE_6348_G2_PCI 0x00000500
373 #define GPIO_MODE_6348_G1_DIAG 0x00000090
374 #define GPIO_MODE_6348_G1_UTOPIA 0x00000080
375 #define GPIO_MODE_6348_G1_SPI_UART 0x00000060
376 #define GPIO_MODE_6348_G1_SPI_MASTER 0x00000060
377 #define GPIO_MODE_6348_G1_MII_PCCARD 0x00000040
378 #define GPIO_MODE_6348_G1_MII_SNOOP 0x00000020
379 #define GPIO_MODE_6348_G1_EXT_EPHY 0x00000010
380 #define GPIO_MODE_6348_G0_DIAG 0x00000009
381 #define GPIO_MODE_6348_G0_EXT_MII 0x00000007
382
383 #define GPIO_MODE_6358_EXTRACS (1 << 5)
384 #define GPIO_MODE_6358_UART1 (1 << 6)
385 #define GPIO_MODE_6358_EXTRA_SPI_SS (1 << 7)
386 #define GPIO_MODE_6358_SERIAL_LED (1 << 10)
387 #define GPIO_MODE_6358_UTOPIA (1 << 12)
388
389
390 /*************************************************************************
391 * _REG relative to RSET_ENET
392 *************************************************************************/
393
394 /* Receiver Configuration register */
395 #define ENET_RXCFG_REG 0x0
396 #define ENET_RXCFG_ALLMCAST_SHIFT 1
397 #define ENET_RXCFG_ALLMCAST_MASK (1 << ENET_RXCFG_ALLMCAST_SHIFT)
398 #define ENET_RXCFG_PROMISC_SHIFT 3
399 #define ENET_RXCFG_PROMISC_MASK (1 << ENET_RXCFG_PROMISC_SHIFT)
400 #define ENET_RXCFG_LOOPBACK_SHIFT 4
401 #define ENET_RXCFG_LOOPBACK_MASK (1 << ENET_RXCFG_LOOPBACK_SHIFT)
402 #define ENET_RXCFG_ENFLOW_SHIFT 5
403 #define ENET_RXCFG_ENFLOW_MASK (1 << ENET_RXCFG_ENFLOW_SHIFT)
404
405 /* Receive Maximum Length register */
406 #define ENET_RXMAXLEN_REG 0x4
407 #define ENET_RXMAXLEN_SHIFT 0
408 #define ENET_RXMAXLEN_MASK (0x7ff << ENET_RXMAXLEN_SHIFT)
409
410 /* Transmit Maximum Length register */
411 #define ENET_TXMAXLEN_REG 0x8
412 #define ENET_TXMAXLEN_SHIFT 0
413 #define ENET_TXMAXLEN_MASK (0x7ff << ENET_TXMAXLEN_SHIFT)
414
415 /* MII Status/Control register */
416 #define ENET_MIISC_REG 0x10
417 #define ENET_MIISC_MDCFREQDIV_SHIFT 0
418 #define ENET_MIISC_MDCFREQDIV_MASK (0x7f << ENET_MIISC_MDCFREQDIV_SHIFT)
419 #define ENET_MIISC_PREAMBLEEN_SHIFT 7
420 #define ENET_MIISC_PREAMBLEEN_MASK (1 << ENET_MIISC_PREAMBLEEN_SHIFT)
421
422 /* MII Data register */
423 #define ENET_MIIDATA_REG 0x14
424 #define ENET_MIIDATA_DATA_SHIFT 0
425 #define ENET_MIIDATA_DATA_MASK (0xffff << ENET_MIIDATA_DATA_SHIFT)
426 #define ENET_MIIDATA_TA_SHIFT 16
427 #define ENET_MIIDATA_TA_MASK (0x3 << ENET_MIIDATA_TA_SHIFT)
428 #define ENET_MIIDATA_REG_SHIFT 18
429 #define ENET_MIIDATA_REG_MASK (0x1f << ENET_MIIDATA_REG_SHIFT)
430 #define ENET_MIIDATA_PHYID_SHIFT 23
431 #define ENET_MIIDATA_PHYID_MASK (0x1f << ENET_MIIDATA_PHYID_SHIFT)
432 #define ENET_MIIDATA_OP_READ_MASK (0x6 << 28)
433 #define ENET_MIIDATA_OP_WRITE_MASK (0x5 << 28)
434
435 /* Ethernet Interrupt Mask register */
436 #define ENET_IRMASK_REG 0x18
437
438 /* Ethernet Interrupt register */
439 #define ENET_IR_REG 0x1c
440 #define ENET_IR_MII (1 << 0)
441 #define ENET_IR_MIB (1 << 1)
442 #define ENET_IR_FLOWC (1 << 2)
443
444 /* Ethernet Control register */
445 #define ENET_CTL_REG 0x2c
446 #define ENET_CTL_ENABLE_SHIFT 0
447 #define ENET_CTL_ENABLE_MASK (1 << ENET_CTL_ENABLE_SHIFT)
448 #define ENET_CTL_DISABLE_SHIFT 1
449 #define ENET_CTL_DISABLE_MASK (1 << ENET_CTL_DISABLE_SHIFT)
450 #define ENET_CTL_SRESET_SHIFT 2
451 #define ENET_CTL_SRESET_MASK (1 << ENET_CTL_SRESET_SHIFT)
452 #define ENET_CTL_EPHYSEL_SHIFT 3
453 #define ENET_CTL_EPHYSEL_MASK (1 << ENET_CTL_EPHYSEL_SHIFT)
454
455 /* Transmit Control register */
456 #define ENET_TXCTL_REG 0x30
457 #define ENET_TXCTL_FD_SHIFT 0
458 #define ENET_TXCTL_FD_MASK (1 << ENET_TXCTL_FD_SHIFT)
459
460 /* Transmit Watermask register */
461 #define ENET_TXWMARK_REG 0x34
462 #define ENET_TXWMARK_WM_SHIFT 0
463 #define ENET_TXWMARK_WM_MASK (0x3f << ENET_TXWMARK_WM_SHIFT)
464
465 /* MIB Control register */
466 #define ENET_MIBCTL_REG 0x38
467 #define ENET_MIBCTL_RDCLEAR_SHIFT 0
468 #define ENET_MIBCTL_RDCLEAR_MASK (1 << ENET_MIBCTL_RDCLEAR_SHIFT)
469
470 /* Perfect Match Data Low register */
471 #define ENET_PML_REG(x) (0x58 + (x) * 8)
472 #define ENET_PMH_REG(x) (0x5c + (x) * 8)
473 #define ENET_PMH_DATAVALID_SHIFT 16
474 #define ENET_PMH_DATAVALID_MASK (1 << ENET_PMH_DATAVALID_SHIFT)
475
476 /* MIB register */
477 #define ENET_MIB_REG(x) (0x200 + (x) * 4)
478 #define ENET_MIB_REG_COUNT 55
479
480
481 /*************************************************************************
482 * _REG relative to RSET_ENETDMA
483 *************************************************************************/
484
485 /* Controller Configuration Register */
486 #define ENETDMA_CFG_REG (0x0)
487 #define ENETDMA_CFG_EN_SHIFT 0
488 #define ENETDMA_CFG_EN_MASK (1 << ENETDMA_CFG_EN_SHIFT)
489 #define ENETDMA_CFG_FLOWCH_MASK(x) (1 << ((x >> 1) + 1))
490
491 /* Flow Control Descriptor Low Threshold register */
492 #define ENETDMA_FLOWCL_REG(x) (0x4 + (x) * 6)
493
494 /* Flow Control Descriptor High Threshold register */
495 #define ENETDMA_FLOWCH_REG(x) (0x8 + (x) * 6)
496
497 /* Flow Control Descriptor Buffer Alloca Threshold register */
498 #define ENETDMA_BUFALLOC_REG(x) (0xc + (x) * 6)
499 #define ENETDMA_BUFALLOC_FORCE_SHIFT 31
500 #define ENETDMA_BUFALLOC_FORCE_MASK (1 << ENETDMA_BUFALLOC_FORCE_SHIFT)
501
502 /* Channel Configuration register */
503 #define ENETDMA_CHANCFG_REG(x) (0x100 + (x) * 0x10)
504 #define ENETDMA_CHANCFG_EN_SHIFT 0
505 #define ENETDMA_CHANCFG_EN_MASK (1 << ENETDMA_CHANCFG_EN_SHIFT)
506 #define ENETDMA_CHANCFG_PKTHALT_SHIFT 1
507 #define ENETDMA_CHANCFG_PKTHALT_MASK (1 << ENETDMA_CHANCFG_PKTHALT_SHIFT)
508
509 /* Interrupt Control/Status register */
510 #define ENETDMA_IR_REG(x) (0x104 + (x) * 0x10)
511 #define ENETDMA_IR_BUFDONE_MASK (1 << 0)
512 #define ENETDMA_IR_PKTDONE_MASK (1 << 1)
513 #define ENETDMA_IR_NOTOWNER_MASK (1 << 2)
514
515 /* Interrupt Mask register */
516 #define ENETDMA_IRMASK_REG(x) (0x108 + (x) * 0x10)
517
518 /* Maximum Burst Length */
519 #define ENETDMA_MAXBURST_REG(x) (0x10C + (x) * 0x10)
520
521 /* Ring Start Address register */
522 #define ENETDMA_RSTART_REG(x) (0x200 + (x) * 0x10)
523
524 /* State Ram Word 2 */
525 #define ENETDMA_SRAM2_REG(x) (0x204 + (x) * 0x10)
526
527 /* State Ram Word 3 */
528 #define ENETDMA_SRAM3_REG(x) (0x208 + (x) * 0x10)
529
530 /* State Ram Word 4 */
531 #define ENETDMA_SRAM4_REG(x) (0x20c + (x) * 0x10)
532
533
534 /*************************************************************************
535 * _REG relative to RSET_OHCI_PRIV
536 *************************************************************************/
537
538 #define OHCI_PRIV_REG 0x0
539 #define OHCI_PRIV_PORT1_HOST_SHIFT 0
540 #define OHCI_PRIV_PORT1_HOST_MASK (1 << OHCI_PRIV_PORT1_HOST_SHIFT)
541 #define OHCI_PRIV_REG_SWAP_SHIFT 3
542 #define OHCI_PRIV_REG_SWAP_MASK (1 << OHCI_PRIV_REG_SWAP_SHIFT)
543
544
545 /*************************************************************************
546 * _REG relative to RSET_USBH_PRIV
547 *************************************************************************/
548
549 #define USBH_PRIV_SWAP_REG 0x0
550 #define USBH_PRIV_SWAP_EHCI_ENDN_SHIFT 4
551 #define USBH_PRIV_SWAP_EHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_EHCI_ENDN_SHIFT)
552 #define USBH_PRIV_SWAP_EHCI_DATA_SHIFT 3
553 #define USBH_PRIV_SWAP_EHCI_DATA_MASK (1 << USBH_PRIV_SWAP_EHCI_DATA_SHIFT)
554 #define USBH_PRIV_SWAP_OHCI_ENDN_SHIFT 1
555 #define USBH_PRIV_SWAP_OHCI_ENDN_MASK (1 << USBH_PRIV_SWAP_OHCI_ENDN_SHIFT)
556 #define USBH_PRIV_SWAP_OHCI_DATA_SHIFT 0
557 #define USBH_PRIV_SWAP_OHCI_DATA_MASK (1 << USBH_PRIV_SWAP_OHCI_DATA_SHIFT)
558
559 #define USBH_PRIV_TEST_REG 0x24
560
561
562 /*************************************************************************
563 * _REG relative to RSET_MPI
564 *************************************************************************/
565
566 /* well known (hard wired) chip select */
567 #define MPI_CS_PCMCIA_COMMON 4
568 #define MPI_CS_PCMCIA_ATTR 5
569 #define MPI_CS_PCMCIA_IO 6
570
571 /* Chip select base register */
572 #define MPI_CSBASE_REG(x) (0x0 + (x) * 8)
573 #define MPI_CSBASE_BASE_SHIFT 13
574 #define MPI_CSBASE_BASE_MASK (0x1ffff << MPI_CSBASE_BASE_SHIFT)
575 #define MPI_CSBASE_SIZE_SHIFT 0
576 #define MPI_CSBASE_SIZE_MASK (0xf << MPI_CSBASE_SIZE_SHIFT)
577
578 #define MPI_CSBASE_SIZE_8K 0
579 #define MPI_CSBASE_SIZE_16K 1
580 #define MPI_CSBASE_SIZE_32K 2
581 #define MPI_CSBASE_SIZE_64K 3
582 #define MPI_CSBASE_SIZE_128K 4
583 #define MPI_CSBASE_SIZE_256K 5
584 #define MPI_CSBASE_SIZE_512K 6
585 #define MPI_CSBASE_SIZE_1M 7
586 #define MPI_CSBASE_SIZE_2M 8
587 #define MPI_CSBASE_SIZE_4M 9
588 #define MPI_CSBASE_SIZE_8M 10
589 #define MPI_CSBASE_SIZE_16M 11
590 #define MPI_CSBASE_SIZE_32M 12
591 #define MPI_CSBASE_SIZE_64M 13
592 #define MPI_CSBASE_SIZE_128M 14
593 #define MPI_CSBASE_SIZE_256M 15
594
595 /* Chip select control register */
596 #define MPI_CSCTL_REG(x) (0x4 + (x) * 8)
597 #define MPI_CSCTL_ENABLE_MASK (1 << 0)
598 #define MPI_CSCTL_WAIT_SHIFT 1
599 #define MPI_CSCTL_WAIT_MASK (0x7 << MPI_CSCTL_WAIT_SHIFT)
600 #define MPI_CSCTL_DATA16_MASK (1 << 4)
601 #define MPI_CSCTL_SYNCMODE_MASK (1 << 7)
602 #define MPI_CSCTL_TSIZE_MASK (1 << 8)
603 #define MPI_CSCTL_ENDIANSWAP_MASK (1 << 10)
604 #define MPI_CSCTL_SETUP_SHIFT 16
605 #define MPI_CSCTL_SETUP_MASK (0xf << MPI_CSCTL_SETUP_SHIFT)
606 #define MPI_CSCTL_HOLD_SHIFT 20
607 #define MPI_CSCTL_HOLD_MASK (0xf << MPI_CSCTL_HOLD_SHIFT)
608
609 /* PCI registers */
610 #define MPI_SP0_RANGE_REG 0x100
611 #define MPI_SP0_REMAP_REG 0x104
612 #define MPI_SP0_REMAP_ENABLE_MASK (1 << 0)
613 #define MPI_SP1_RANGE_REG 0x10C
614 #define MPI_SP1_REMAP_REG 0x110
615 #define MPI_SP1_REMAP_ENABLE_MASK (1 << 0)
616
617 #define MPI_L2PCFG_REG 0x11C
618 #define MPI_L2PCFG_CFG_TYPE_SHIFT 0
619 #define MPI_L2PCFG_CFG_TYPE_MASK (0x3 << MPI_L2PCFG_CFG_TYPE_SHIFT)
620 #define MPI_L2PCFG_REG_SHIFT 2
621 #define MPI_L2PCFG_REG_MASK (0x3f << MPI_L2PCFG_REG_SHIFT)
622 #define MPI_L2PCFG_FUNC_SHIFT 8
623 #define MPI_L2PCFG_FUNC_MASK (0x7 << MPI_L2PCFG_FUNC_SHIFT)
624 #define MPI_L2PCFG_DEVNUM_SHIFT 11
625 #define MPI_L2PCFG_DEVNUM_MASK (0x1f << MPI_L2PCFG_DEVNUM_SHIFT)
626 #define MPI_L2PCFG_CFG_USEREG_MASK (1 << 30)
627 #define MPI_L2PCFG_CFG_SEL_MASK (1 << 31)
628
629 #define MPI_L2PMEMRANGE1_REG 0x120
630 #define MPI_L2PMEMBASE1_REG 0x124
631 #define MPI_L2PMEMREMAP1_REG 0x128
632 #define MPI_L2PMEMRANGE2_REG 0x12C
633 #define MPI_L2PMEMBASE2_REG 0x130
634 #define MPI_L2PMEMREMAP2_REG 0x134
635 #define MPI_L2PIORANGE_REG 0x138
636 #define MPI_L2PIOBASE_REG 0x13C
637 #define MPI_L2PIOREMAP_REG 0x140
638 #define MPI_L2P_BASE_MASK (0xffff8000)
639 #define MPI_L2PREMAP_ENABLED_MASK (1 << 0)
640 #define MPI_L2PREMAP_IS_CARDBUS_MASK (1 << 2)
641
642 #define MPI_PCIMODESEL_REG 0x144
643 #define MPI_PCIMODESEL_BAR1_NOSWAP_MASK (1 << 0)
644 #define MPI_PCIMODESEL_BAR2_NOSWAP_MASK (1 << 1)
645 #define MPI_PCIMODESEL_EXT_ARB_MASK (1 << 2)
646 #define MPI_PCIMODESEL_PREFETCH_SHIFT 4
647 #define MPI_PCIMODESEL_PREFETCH_MASK (0xf << MPI_PCIMODESEL_PREFETCH_SHIFT)
648
649 #define MPI_LOCBUSCTL_REG 0x14C
650 #define MPI_LOCBUSCTL_EN_PCI_GPIO_MASK (1 << 0)
651 #define MPI_LOCBUSCTL_U2P_NOSWAP_MASK (1 << 1)
652
653 #define MPI_LOCINT_REG 0x150
654 #define MPI_LOCINT_MASK(x) (1 << (x + 16))
655 #define MPI_LOCINT_STAT(x) (1 << (x))
656 #define MPI_LOCINT_DIR_FAILED 6
657 #define MPI_LOCINT_EXT_PCI_INT 7
658 #define MPI_LOCINT_SERR 8
659 #define MPI_LOCINT_CSERR 9
660
661 #define MPI_PCICFGCTL_REG 0x178
662 #define MPI_PCICFGCTL_CFGADDR_SHIFT 2
663 #define MPI_PCICFGCTL_CFGADDR_MASK (0x1f << MPI_PCICFGCTL_CFGADDR_SHIFT)
664 #define MPI_PCICFGCTL_WRITEEN_MASK (1 << 7)
665
666 #define MPI_PCICFGDATA_REG 0x17C
667
668 /* PCI host bridge custom register */
669 #define BCMPCI_REG_TIMERS 0x40
670 #define REG_TIMER_TRDY_SHIFT 0
671 #define REG_TIMER_TRDY_MASK (0xff << REG_TIMER_TRDY_SHIFT)
672 #define REG_TIMER_RETRY_SHIFT 8
673 #define REG_TIMER_RETRY_MASK (0xff << REG_TIMER_RETRY_SHIFT)
674
675
676 /*************************************************************************
677 * _REG relative to RSET_PCMCIA
678 *************************************************************************/
679
680 #define PCMCIA_C1_REG 0x0
681 #define PCMCIA_C1_CD1_MASK (1 << 0)
682 #define PCMCIA_C1_CD2_MASK (1 << 1)
683 #define PCMCIA_C1_VS1_MASK (1 << 2)
684 #define PCMCIA_C1_VS2_MASK (1 << 3)
685 #define PCMCIA_C1_VS1OE_MASK (1 << 6)
686 #define PCMCIA_C1_VS2OE_MASK (1 << 7)
687 #define PCMCIA_C1_CBIDSEL_SHIFT (8)
688 #define PCMCIA_C1_CBIDSEL_MASK (0x1f << PCMCIA_C1_CBIDSEL_SHIFT)
689 #define PCMCIA_C1_EN_PCMCIA_GPIO_MASK (1 << 13)
690 #define PCMCIA_C1_EN_PCMCIA_MASK (1 << 14)
691 #define PCMCIA_C1_EN_CARDBUS_MASK (1 << 15)
692 #define PCMCIA_C1_RESET_MASK (1 << 18)
693
694 #define PCMCIA_C2_REG 0x8
695 #define PCMCIA_C2_DATA16_MASK (1 << 0)
696 #define PCMCIA_C2_BYTESWAP_MASK (1 << 1)
697 #define PCMCIA_C2_RWCOUNT_SHIFT 2
698 #define PCMCIA_C2_RWCOUNT_MASK (0x3f << PCMCIA_C2_RWCOUNT_SHIFT)
699 #define PCMCIA_C2_INACTIVE_SHIFT 8
700 #define PCMCIA_C2_INACTIVE_MASK (0x3f << PCMCIA_C2_INACTIVE_SHIFT)
701 #define PCMCIA_C2_SETUP_SHIFT 16
702 #define PCMCIA_C2_SETUP_MASK (0x3f << PCMCIA_C2_SETUP_SHIFT)
703 #define PCMCIA_C2_HOLD_SHIFT 24
704 #define PCMCIA_C2_HOLD_MASK (0x3f << PCMCIA_C2_HOLD_SHIFT)
705
706
707 /*************************************************************************
708 * _REG relative to RSET_SDRAM
709 *************************************************************************/
710
711 #define SDRAM_CFG_REG 0x0
712 #define SDRAM_CFG_ROW_SHIFT 4
713 #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
714 #define SDRAM_CFG_COL_SHIFT 6
715 #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
716 #define SDRAM_CFG_32B_SHIFT 10
717 #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
718 #define SDRAM_CFG_BANK_SHIFT 13
719 #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
720
721 #define SDRAM_PRIO_REG 0x2C
722 #define SDRAM_PRIO_MIPS_SHIFT 29
723 #define SDRAM_PRIO_MIPS_MASK (1 << SDRAM_PRIO_MIPS_SHIFT)
724 #define SDRAM_PRIO_ADSL_SHIFT 30
725 #define SDRAM_PRIO_ADSL_MASK (1 << SDRAM_PRIO_ADSL_SHIFT)
726 #define SDRAM_PRIO_EN_SHIFT 31
727 #define SDRAM_PRIO_EN_MASK (1 << SDRAM_PRIO_EN_SHIFT)
728
729
730 /*************************************************************************
731 * _REG relative to RSET_MEMC
732 *************************************************************************/
733
734 #define MEMC_CFG_REG 0x4
735 #define MEMC_CFG_32B_SHIFT 1
736 #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
737 #define MEMC_CFG_COL_SHIFT 3
738 #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
739 #define MEMC_CFG_ROW_SHIFT 6
740 #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
741
742
743 /*************************************************************************
744 * _REG relative to RSET_DDR
745 *************************************************************************/
746
747 #define DDR_DMIPSPLLCFG_REG 0x18
748 #define DMIPSPLLCFG_M1_SHIFT 0
749 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
750 #define DMIPSPLLCFG_N1_SHIFT 23
751 #define DMIPSPLLCFG_N1_MASK (0x3f << DMIPSPLLCFG_N1_SHIFT)
752 #define DMIPSPLLCFG_N2_SHIFT 29
753 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
754
755 /*************************************************************************
756 * _REG relative to RSET_SPI
757 *************************************************************************/
758
759 /* BCM 6338 SPI core */
760 #define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
761 #define SPI_BCM_6338_SPI_INT_STATUS 0x02
762 #define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
763 #define SPI_BCM_6338_SPI_INT_MASK 0x04
764 #define SPI_BCM_6338_SPI_ST 0x05
765 #define SPI_BCM_6338_SPI_CLK_CFG 0x06
766 #define SPI_BCM_6338_SPI_FILL_BYTE 0x07
767 #define SPI_BCM_6338_SPI_MSG_TAIL 0x09
768 #define SPI_BCM_6338_SPI_RX_TAIL 0x0b
769 #define SPI_BCM_6338_SPI_MSG_CTL 0x40
770 #define SPI_BCM_6338_SPI_MSG_DATA 0x41
771 #define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
772 #define SPI_BCM_6338_SPI_RX_DATA 0x80
773 #define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
774
775 /* BCM 6348 SPI core */
776 #define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
777 #define SPI_BCM_6348_SPI_INT_STATUS 0x01
778 #define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
779 #define SPI_BCM_6348_SPI_FILL_BYTE 0x04
780 #define SPI_BCM_6348_SPI_CLK_CFG 0x05
781 #define SPI_BCM_6348_SPI_ST 0x06
782 #define SPI_BCM_6348_SPI_INT_MASK 0x07
783 #define SPI_BCM_6348_SPI_RX_TAIL 0x08
784 #define SPI_BCM_6348_SPI_MSG_TAIL 0x10
785 #define SPI_BCM_6348_SPI_MSG_DATA 0x40
786 #define SPI_BCM_6348_SPI_MSG_CTL 0x42
787 #define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
788 #define SPI_BCM_6348_SPI_RX_DATA 0x80
789 #define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
790
791 /* BCM 6358 SPI core */
792 #define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
793
794 #define SPI_BCM_6358_SPI_MSG_DATA 0x02
795 #define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
796
797 #define SPI_BCM_6358_SPI_RX_DATA 0x400
798 #define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
799
800 #define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
801
802 #define SPI_BCM_6358_SPI_INT_STATUS 0x702
803 #define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
804
805 #define SPI_BCM_6358_SPI_INT_MASK 0x704
806
807 #define SPI_BCM_6358_SPI_STATUS 0x705
808
809 #define SPI_BCM_6358_SPI_CLK_CFG 0x706
810
811 #define SPI_BCM_6358_SPI_FILL_BYTE 0x707
812 #define SPI_BCM_6358_SPI_MSG_TAIL 0x709
813 #define SPI_BCM_6358_SPI_RX_TAIL 0x70B
814
815 /* Shared SPI definitions */
816
817 /* Message configuration */
818 #define SPI_FD_RW 0x00
819 #define SPI_HD_W 0x01
820 #define SPI_HD_R 0x02
821 #define SPI_BYTE_CNT_SHIFT 0
822 #define SPI_MSG_TYPE_SHIFT 14
823
824 /* Command */
825 #define SPI_CMD_NOOP 0x01
826 #define SPI_CMD_SOFT_RESET 0x02
827 #define SPI_CMD_HARD_RESET 0x04
828 #define SPI_CMD_START_IMMEDIATE 0x08
829 #define SPI_CMD_COMMAND_SHIFT 0
830 #define SPI_CMD_COMMAND_MASK 0x000f
831 #define SPI_CMD_DEVICE_ID_SHIFT 4
832 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
833 #define SPI_CMD_ONE_BYTE_SHIFT 11
834 #define SPI_CMD_ONE_WIRE_SHIFT 12
835 #define SPI_DEV_ID_0 0
836 #define SPI_DEV_ID_1 1
837 #define SPI_DEV_ID_2 2
838 #define SPI_DEV_ID_3 3
839
840 /* Interrupt mask */
841 #define SPI_INTR_CMD_DONE 0x01
842 #define SPI_INTR_RX_OVERFLOW 0x02
843 #define SPI_INTR_TX_UNDERFLOW 0x04
844 #define SPI_INTR_TX_OVERFLOW 0x08
845 #define SPI_INTR_RX_UNDERFLOW 0x10
846 #define SPI_INTR_CLEAR_ALL 0x1f
847
848 /* Status */
849 #define SPI_RX_EMPTY 0x02
850 #define SPI_CMD_BUSY 0x04
851 #define SPI_SERIAL_BUSY 0x08
852
853 /* Clock configuration */
854 #define SPI_CLK_20MHZ 0x00
855 #define SPI_CLK_0_391MHZ 0x01
856 #define SPI_CLK_0_781MHZ 0x02 /* default */
857 #define SPI_CLK_1_563MHZ 0x03
858 #define SPI_CLK_3_125MHZ 0x04
859 #define SPI_CLK_6_250MHZ 0x05
860 #define SPI_CLK_12_50MHZ 0x06
861 #define SPI_CLK_25MHZ 0x07
862 #define SPI_CLK_MASK 0x07
863 #define SPI_SSOFFTIME_MASK 0x38
864 #define SPI_SSOFFTIME_SHIFT 3
865 #define SPI_BYTE_SWAP 0x80
866
867
868 #endif /* BCM63XX_REGS_H_ */