bcm963xx: add new timer code
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-2.6.25 / 100-bcm963xx_add_new_timer_code.patch
1 From 7d6656dc127b54e53e507e8f264bb7e14e620cad Mon Sep 17 00:00:00 2001
2 From: Axel Gembe <ago@bastart.eu.org>
3 Date: Sat, 17 May 2008 15:02:39 +0200
4 Subject: [PATCH] bcm963xx: add new timer code
5
6 This basically selects the new generic MIPS timer code for BCM963xx and
7 simplifies the timer setup code.
8
9 Signed-off-by: Axel Gembe <ago@bastart.eu.org>
10 ---
11 arch/mips/Kconfig | 2 +
12 arch/mips/bcm963xx/time.c | 64 ++++++++++++++++++++------------------------
13 2 files changed, 31 insertions(+), 35 deletions(-)
14
15 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
16 index 1b1c4bf..3f8be3f 100644
17 --- a/arch/mips/Kconfig
18 +++ b/arch/mips/Kconfig
19 @@ -67,6 +67,8 @@ config BCM963XX
20 select HW_HAS_PCI
21 select DMA_NONCOHERENT
22 select IRQ_CPU
23 + select CEVT_R4K
24 + select CSRC_R4K
25 help
26 This is a fmaily of boards based on the Broadcom MIPS32
27
28 diff --git a/arch/mips/bcm963xx/time.c b/arch/mips/bcm963xx/time.c
29 index 8a5007e..9fae8fd 100644
30 --- a/arch/mips/bcm963xx/time.c
31 +++ b/arch/mips/bcm963xx/time.c
32 @@ -1,6 +1,7 @@
33 /*
34 <:copyright-gpl
35 Copyright 2004 Broadcom Corp. All Rights Reserved.
36 + Copyright (C) 2008 Axel Gembe <ago@bastart.eu.org>
37
38 This program is free software; you can distribute it and/or modify it
39 under the terms of the GNU General Public License (Version 2) as
40 @@ -40,50 +41,43 @@
41 #include <bcm_map_part.h>
42 #include <bcm_intr.h>
43
44 -static unsigned long r4k_offset; /* Amount to increment compare reg each time */
45 -static unsigned long r4k_cur; /* What counter should be at next timer irq */
46 -
47 -/* *********************************************************************
48 - * calculateCpuSpeed()
49 - * Calculate the BCM6348 CPU speed by reading the PLL strap register
50 - * and applying the following formula:
51 - * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1)
52 - * Input parameters:
53 - * none
54 - * Return value:
55 - * none
56 - ********************************************************************* */
57 -
58 +/*
59 + * calculateCpuSpeed()
60 + *
61 + * Calculate the BCM6348 CPU speed by reading the PLL strap register and applying
62 + * the following formula:
63 + *
64 + * cpu_clk = (.25 * 64MHz freq) * (N1 + 1) * (N2 + 2) / (M1_CPU + 1)
65 + */
66 static inline unsigned long __init calculateCpuSpeed(void)
67 {
68 - u32 pllStrap = PERF->PllStrap;
69 - int n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT;
70 - int n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT;
71 - int m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT;
72 + u32 pllStrap;
73 + int n1, n2, m1cpu;
74 +
75 + pllStrap = PERF->PllStrap;
76 + n1 = (pllStrap & PLL_N1_MASK) >> PLL_N1_SHFT;
77 + n2 = (pllStrap & PLL_N2_MASK) >> PLL_N2_SHFT;
78 + m1cpu = (pllStrap & PLL_M1_CPU_MASK) >> PLL_M1_CPU_SHFT;
79
80 return (16 * (n1 + 1) * (n2 + 2) / (m1cpu + 1)) * 1000000;
81 }
82
83
84 -static inline unsigned long __init cal_r4koff(void)
85 -{
86 - mips_hpt_frequency = calculateCpuSpeed() / 2;
87 - return (mips_hpt_frequency / HZ);
88 -}
89 -
90 void __init plat_time_init(void)
91 {
92 - unsigned int est_freq, flags;
93 - local_irq_save(flags);
94 + unsigned long cpu_clock;
95 +
96 + cpu_clock = calculateCpuSpeed();
97 +
98 + printk("CPU frequency %lu.%02lu MHz\n", cpu_clock / 1000000,
99 + (cpu_clock % 1000000) * 100 / 1000000);
100
101 - printk("calculating r4koff... ");
102 - r4k_offset = cal_r4koff();
103 - printk("%08lx(%d)\n", r4k_offset, (int)r4k_offset);
104 + mips_hpt_frequency = cpu_clock / 2;
105
106 - est_freq = 2 * r4k_offset * HZ;
107 - est_freq += 5000; /* round */
108 - est_freq -= est_freq % 10000;
109 - printk("CPU frequency %d.%02d MHz\n", est_freq / 1000000,
110 - (est_freq % 1000000) * 100 / 1000000);
111 - local_irq_restore(flags);
112 + /*
113 + * Use deterministic values for initial counter interrupt
114 + * so that calibrate delay avoids encountering a counter wrap.
115 + */
116 + write_c0_count(0);
117 + write_c0_compare(0xffff);
118 }
119 --
120 1.5.5.1
121