New Broadcom BCM63xx codebase, huge thanks to Maxime ;)
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-2.6.27 / 005-change_pci_code_to_emulate_a_fake_cardbus_adapter.patch
1 From 6891d3c1014cf56dc76ec583b69d341ea47984d6 Mon Sep 17 00:00:00 2001
2 From: Maxime Bizon <mbizon@freebox.fr>
3 Date: Fri, 18 Jul 2008 20:34:35 +0200
4 Subject: [PATCH] [MIPS] BCM63XX: Change PCI code to emulate a fake cardbus bridge.
5
6 Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
7 ---
8 arch/mips/pci/ops-bcm63xx.c | 288 +++++++++++++++++++++++++++++++++++++++++++
9 arch/mips/pci/pci-bcm63xx.c | 44 +++++++
10 2 files changed, 332 insertions(+), 0 deletions(-)
11
12 diff --git a/arch/mips/pci/ops-bcm63xx.c b/arch/mips/pci/ops-bcm63xx.c
13 index f8dce9d..822ae17 100644
14 --- a/arch/mips/pci/ops-bcm63xx.c
15 +++ b/arch/mips/pci/ops-bcm63xx.c
16 @@ -177,3 +177,291 @@ struct pci_ops bcm63xx_pci_ops = {
17 .read = bcm63xx_pci_read,
18 .write = bcm63xx_pci_write
19 };
20 +
21 +#ifdef CONFIG_CARDBUS
22 +/*
23 + * emulate configuration read access on a cardbus bridge
24 + */
25 +#define FAKE_CB_BRIDGE_SLOT 0x1e
26 +
27 +static int fake_cb_bridge_bus_number = -1;
28 +
29 +static struct {
30 + u16 pci_command;
31 + u8 cb_latency;
32 + u8 subordinate_busn;
33 + u8 cardbus_busn;
34 + u8 pci_busn;
35 + int bus_assigned;
36 + u16 bridge_control;
37 +
38 + u32 mem_base0;
39 + u32 mem_limit0;
40 + u32 mem_base1;
41 + u32 mem_limit1;
42 +
43 + u32 io_base0;
44 + u32 io_limit0;
45 + u32 io_base1;
46 + u32 io_limit1;
47 +} fake_cb_bridge_regs;
48 +
49 +static int fake_cb_bridge_read(int where, int size, u32 *val)
50 +{
51 + unsigned int reg;
52 + u32 data;
53 +
54 + data = 0;
55 + reg = where >> 2;
56 + switch (reg) {
57 + case (PCI_VENDOR_ID >> 2):
58 + case (PCI_CB_SUBSYSTEM_VENDOR_ID >> 2):
59 + /* create dummy vendor/device id from our cpu id */
60 + data = (bcm63xx_get_cpu_id() << 16) | PCI_VENDOR_ID_BROADCOM;
61 + break;
62 +
63 + case (PCI_COMMAND >> 2):
64 + data = (PCI_STATUS_DEVSEL_SLOW << 16);
65 + data |= fake_cb_bridge_regs.pci_command;
66 + break;
67 +
68 + case (PCI_CLASS_REVISION >> 2):
69 + data = (PCI_CLASS_BRIDGE_CARDBUS << 16);
70 + break;
71 +
72 + case (PCI_CACHE_LINE_SIZE >> 2):
73 + data = (PCI_HEADER_TYPE_CARDBUS << 16);
74 + break;
75 +
76 + case (PCI_INTERRUPT_LINE >> 2):
77 + /* bridge control */
78 + data = (fake_cb_bridge_regs.bridge_control << 16);
79 + /* pin:intA line:0xff */
80 + data |= (0x1 << 8) | 0xff;
81 + break;
82 +
83 + case (PCI_CB_PRIMARY_BUS >> 2):
84 + data = (fake_cb_bridge_regs.cb_latency << 24);
85 + data |= (fake_cb_bridge_regs.subordinate_busn << 16);
86 + data |= (fake_cb_bridge_regs.cardbus_busn << 8);
87 + data |= fake_cb_bridge_regs.pci_busn;
88 + break;
89 +
90 + case (PCI_CB_MEMORY_BASE_0 >> 2):
91 + data = fake_cb_bridge_regs.mem_base0;
92 + break;
93 +
94 + case (PCI_CB_MEMORY_LIMIT_0 >> 2):
95 + data = fake_cb_bridge_regs.mem_limit0;
96 + break;
97 +
98 + case (PCI_CB_MEMORY_BASE_1 >> 2):
99 + data = fake_cb_bridge_regs.mem_base1;
100 + break;
101 +
102 + case (PCI_CB_MEMORY_LIMIT_1 >> 2):
103 + data = fake_cb_bridge_regs.mem_limit1;
104 + break;
105 +
106 + case (PCI_CB_IO_BASE_0 >> 2):
107 + /* | 1 for 32bits io support */
108 + data = fake_cb_bridge_regs.io_base0 | 0x1;
109 + break;
110 +
111 + case (PCI_CB_IO_LIMIT_0 >> 2):
112 + data = fake_cb_bridge_regs.io_limit0;
113 + break;
114 +
115 + case (PCI_CB_IO_BASE_1 >> 2):
116 + /* | 1 for 32bits io support */
117 + data = fake_cb_bridge_regs.io_base1 | 0x1;
118 + break;
119 +
120 + case (PCI_CB_IO_LIMIT_1 >> 2):
121 + data = fake_cb_bridge_regs.io_limit1;
122 + break;
123 + }
124 +
125 + *val = postprocess_read(data, where, size);
126 + return PCIBIOS_SUCCESSFUL;
127 +}
128 +
129 +/*
130 + * emulate configuration write access on a cardbus bridge
131 + */
132 +static int fake_cb_bridge_write(int where, int size, u32 val)
133 +{
134 + unsigned int reg;
135 + u32 data, tmp;
136 + int ret;
137 +
138 + ret = fake_cb_bridge_read((where & ~0x3), 4, &data);
139 + if (ret != PCIBIOS_SUCCESSFUL)
140 + return ret;
141 +
142 + data = preprocess_write(data, val, where, size);
143 +
144 + reg = where >> 2;
145 + switch (reg) {
146 + case (PCI_COMMAND >> 2):
147 + fake_cb_bridge_regs.pci_command = (data & 0xffff);
148 + break;
149 +
150 + case (PCI_CB_PRIMARY_BUS >> 2):
151 + fake_cb_bridge_regs.cb_latency = (data >> 24) & 0xff;
152 + fake_cb_bridge_regs.subordinate_busn = (data >> 16) & 0xff;
153 + fake_cb_bridge_regs.cardbus_busn = (data >> 8) & 0xff;
154 + fake_cb_bridge_regs.pci_busn = data & 0xff;
155 + if (fake_cb_bridge_regs.cardbus_busn)
156 + fake_cb_bridge_regs.bus_assigned = 1;
157 + break;
158 +
159 + case (PCI_INTERRUPT_LINE >> 2):
160 + tmp = (data >> 16) & 0xffff;
161 + /* disable memory prefetch support */
162 + tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
163 + tmp &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
164 + fake_cb_bridge_regs.bridge_control = tmp;
165 + break;
166 +
167 + case (PCI_CB_MEMORY_BASE_0 >> 2):
168 + fake_cb_bridge_regs.mem_base0 = data;
169 + break;
170 +
171 + case (PCI_CB_MEMORY_LIMIT_0 >> 2):
172 + fake_cb_bridge_regs.mem_limit0 = data;
173 + break;
174 +
175 + case (PCI_CB_MEMORY_BASE_1 >> 2):
176 + fake_cb_bridge_regs.mem_base1 = data;
177 + break;
178 +
179 + case (PCI_CB_MEMORY_LIMIT_1 >> 2):
180 + fake_cb_bridge_regs.mem_limit1 = data;
181 + break;
182 +
183 + case (PCI_CB_IO_BASE_0 >> 2):
184 + fake_cb_bridge_regs.io_base0 = data;
185 + break;
186 +
187 + case (PCI_CB_IO_LIMIT_0 >> 2):
188 + fake_cb_bridge_regs.io_limit0 = data;
189 + break;
190 +
191 + case (PCI_CB_IO_BASE_1 >> 2):
192 + fake_cb_bridge_regs.io_base1 = data;
193 + break;
194 +
195 + case (PCI_CB_IO_LIMIT_1 >> 2):
196 + fake_cb_bridge_regs.io_limit1 = data;
197 + break;
198 + }
199 +
200 + return PCIBIOS_SUCCESSFUL;
201 +}
202 +
203 +static int bcm63xx_cb_read(struct pci_bus *bus, unsigned int devfn,
204 + int where, int size, u32 *val)
205 +{
206 + /* snoop access to slot 0x1e on root bus, we fake a cardbus
207 + * bridge at this location */
208 + if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
209 + fake_cb_bridge_bus_number = bus->number;
210 + return fake_cb_bridge_read(where, size, val);
211 + }
212 +
213 + /* a configuration cycle for the device behind the cardbus
214 + * bridge is actually done as a type 0 cycle on the primary
215 + * bus. This means that only one device can be on the cardbus
216 + * bus */
217 + if (fake_cb_bridge_regs.bus_assigned &&
218 + bus->number == fake_cb_bridge_regs.cardbus_busn &&
219 + PCI_SLOT(devfn) == 0)
220 + return bcm63xx_do_cfg_read(0, 0,
221 + PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
222 + where, size, val);
223 +
224 + return PCIBIOS_DEVICE_NOT_FOUND;
225 +}
226 +
227 +static int bcm63xx_cb_write(struct pci_bus *bus, unsigned int devfn,
228 + int where, int size, u32 val)
229 +{
230 + if (!bus->parent && PCI_SLOT(devfn) == FAKE_CB_BRIDGE_SLOT) {
231 + fake_cb_bridge_bus_number = bus->number;
232 + return fake_cb_bridge_write(where, size, val);
233 + }
234 +
235 + if (fake_cb_bridge_regs.bus_assigned &&
236 + bus->number == fake_cb_bridge_regs.cardbus_busn &&
237 + PCI_SLOT(devfn) == 0)
238 + return bcm63xx_do_cfg_write(0, 0,
239 + PCI_DEVFN(CARDBUS_PCI_IDSEL, 0),
240 + where, size, val);
241 +
242 + return PCIBIOS_DEVICE_NOT_FOUND;
243 +}
244 +
245 +struct pci_ops bcm63xx_cb_ops = {
246 + .read = bcm63xx_cb_read,
247 + .write = bcm63xx_cb_write,
248 +};
249 +
250 +/*
251 + * only one IO window, so it cannot be shared by PCI and cardbus, use
252 + * fixup to choose and detect unhandled configuration
253 + */
254 +static void bcm63xx_fixup(struct pci_dev *dev)
255 +{
256 + static int io_window = -1;
257 + int i, found, new_io_window;
258 + u32 val;
259 +
260 + /* look for any io resource */
261 + found = 0;
262 + for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
263 + if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
264 + found = 1;
265 + break;
266 + }
267 + }
268 +
269 + if (!found)
270 + return;
271 +
272 + /* skip our fake bus with only cardbus bridge on it */
273 + if (dev->bus->number == fake_cb_bridge_bus_number)
274 + return;
275 +
276 + /* find on which bus the device is */
277 + if (fake_cb_bridge_regs.bus_assigned &&
278 + dev->bus->number == fake_cb_bridge_regs.cardbus_busn &&
279 + PCI_SLOT(dev->devfn) == 0)
280 + new_io_window = 1;
281 + else
282 + new_io_window = 0;
283 +
284 + if (new_io_window == io_window)
285 + return;
286 +
287 + if (io_window != -1) {
288 + printk(KERN_ERR "bcm63xx: both PCI and cardbus devices "
289 + "need IO, which hardware cannot do\n");
290 + return;
291 + }
292 +
293 + printk(KERN_INFO "bcm63xx: PCI IO window assigned to %s\n",
294 + (new_io_window == 0) ? "PCI" : "cardbus");
295 +
296 + val = bcm_mpi_readl(MPI_L2PIOREMAP_REG);
297 + if (io_window)
298 + val |= MPI_L2PREMAP_IS_CARDBUS_MASK;
299 + else
300 + val &= ~MPI_L2PREMAP_IS_CARDBUS_MASK;
301 + bcm_mpi_writel(val, MPI_L2PIOREMAP_REG);
302 +
303 + io_window = new_io_window;
304 +}
305 +
306 +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, bcm63xx_fixup);
307 +#endif
308 diff --git a/arch/mips/pci/pci-bcm63xx.c b/arch/mips/pci/pci-bcm63xx.c
309 index 52bac8e..601700d 100644
310 --- a/arch/mips/pci/pci-bcm63xx.c
311 +++ b/arch/mips/pci/pci-bcm63xx.c
312 @@ -28,7 +28,11 @@ static struct resource bcm_pci_mem_resource = {
313 static struct resource bcm_pci_io_resource = {
314 .name = "bcm63xx PCI IO space",
315 .start = BCM_PCI_IO_BASE_PA,
316 +#ifdef CONFIG_CARDBUS
317 + .end = BCM_PCI_IO_HALF_PA,
318 +#else
319 .end = BCM_PCI_IO_END_PA,
320 +#endif
321 .flags = IORESOURCE_IO
322 };
323
324 @@ -38,6 +42,33 @@ struct pci_controller bcm63xx_controller = {
325 .mem_resource = &bcm_pci_mem_resource,
326 };
327
328 +/*
329 + * We handle cardbus via a fake Cardbus bridge, memory and io spaces
330 + * have to be clearly separated from PCI one since we have different
331 + * memory decoder.
332 + */
333 +#ifdef CONFIG_CARDBUS
334 +static struct resource bcm_cb_mem_resource = {
335 + .name = "bcm63xx Cardbus memory space",
336 + .start = BCM_CB_MEM_BASE_PA,
337 + .end = BCM_CB_MEM_END_PA,
338 + .flags = IORESOURCE_MEM
339 +};
340 +
341 +static struct resource bcm_cb_io_resource = {
342 + .name = "bcm63xx Cardbus IO space",
343 + .start = BCM_PCI_IO_HALF_PA + 1,
344 + .end = BCM_PCI_IO_END_PA,
345 + .flags = IORESOURCE_IO
346 +};
347 +
348 +struct pci_controller bcm63xx_cb_controller = {
349 + .pci_ops = &bcm63xx_cb_ops,
350 + .io_resource = &bcm_cb_io_resource,
351 + .mem_resource = &bcm_cb_mem_resource,
352 +};
353 +#endif
354 +
355 static u32 bcm63xx_int_cfg_readl(u32 reg)
356 {
357 u32 tmp;
358 @@ -98,8 +129,17 @@ static int __init bcm63xx_pci_init(void)
359 val |= (CARDBUS_PCI_IDSEL << PCMCIA_C1_CBIDSEL_SHIFT);
360 bcm_pcmcia_writel(val, PCMCIA_C1_REG);
361
362 +#ifdef CONFIG_CARDBUS
363 + /* setup local bus to PCI access (Cardbus memory) */
364 + val = BCM_CB_MEM_BASE_PA & MPI_L2P_BASE_MASK;
365 + bcm_mpi_writel(val, MPI_L2PMEMBASE2_REG);
366 + bcm_mpi_writel(~(BCM_CB_MEM_SIZE - 1), MPI_L2PMEMRANGE2_REG);
367 + val |= MPI_L2PREMAP_ENABLED_MASK | MPI_L2PREMAP_IS_CARDBUS_MASK;
368 + bcm_mpi_writel(val, MPI_L2PMEMREMAP2_REG);
369 +#else
370 /* disable second access windows */
371 bcm_mpi_writel(0, MPI_L2PMEMREMAP2_REG);
372 +#endif
373
374 /* setup local bus to PCI access (IO memory), we have only 1
375 * IO window for both PCI and cardbus, but it cannot handle
376 @@ -169,6 +209,10 @@ static int __init bcm63xx_pci_init(void)
377
378 register_pci_controller(&bcm63xx_controller);
379
380 +#ifdef CONFIG_CARDBUS
381 + register_pci_controller(&bcm63xx_cb_controller);
382 +#endif
383 +
384 /* mark memory space used for IO mapping as reserved */
385 request_mem_region(BCM_PCI_IO_BASE_PA, BCM_PCI_IO_SIZE,
386 "bcm63xx PCI IO space");
387 --
388 1.5.4.3
389