[brcm63xx] re-instate SPI support
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-2.6.32 / 240-spi.patch
1 --- a/arch/mips/bcm63xx/cpu.c
2 +++ b/arch/mips/bcm63xx/cpu.c
3 @@ -55,6 +55,7 @@ static const unsigned long bcm96338_regs
4
5 static const int bcm96338_irqs[] = {
6 [IRQ_TIMER] = BCM_6338_TIMER_IRQ,
7 + [IRQ_SPI] = BCM_6338_SPI_IRQ,
8 [IRQ_UART0] = BCM_6338_UART0_IRQ,
9 [IRQ_DSL] = BCM_6338_DSL_IRQ,
10 [IRQ_ENET0] = BCM_6338_ENET0_IRQ,
11 @@ -127,6 +128,7 @@ static const unsigned long bcm96348_regs
12
13 static const int bcm96348_irqs[] = {
14 [IRQ_TIMER] = BCM_6348_TIMER_IRQ,
15 + [IRQ_SPI] = BCM_6348_SPI_IRQ,
16 [IRQ_UART0] = BCM_6348_UART0_IRQ,
17 [IRQ_DSL] = BCM_6348_DSL_IRQ,
18 [IRQ_ENET0] = BCM_6348_ENET0_IRQ,
19 @@ -169,6 +171,7 @@ static const unsigned long bcm96358_regs
20
21 static const int bcm96358_irqs[] = {
22 [IRQ_TIMER] = BCM_6358_TIMER_IRQ,
23 + [IRQ_SPI] = BCM_6358_SPI_IRQ,
24 [IRQ_UART0] = BCM_6358_UART0_IRQ,
25 [IRQ_DSL] = BCM_6358_DSL_IRQ,
26 [IRQ_ENET0] = BCM_6358_ENET0_IRQ,
27 --- /dev/null
28 +++ b/arch/mips/bcm63xx/dev-spi.c
29 @@ -0,0 +1,60 @@
30 +/*
31 + * This file is subject to the terms and conditions of the GNU General Public
32 + * License. See the file "COPYING" in the main directory of this archive
33 + * for more details.
34 + *
35 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
36 + */
37 +
38 +#include <linux/init.h>
39 +#include <linux/kernel.h>
40 +#include <linux/platform_device.h>
41 +
42 +#include <bcm63xx_cpu.h>
43 +#include <bcm63xx_dev_spi.h>
44 +#include <bcm63xx_regs.h>
45 +
46 +static struct resource spi_resources[] = {
47 + {
48 + .start = -1, /* filled at runtime */
49 + .end = -1, /* filled at runtime */
50 + .flags = IORESOURCE_MEM,
51 + },
52 + {
53 + .start = -1, /* filled at runtime */
54 + .flags = IORESOURCE_IRQ,
55 + },
56 +};
57 +
58 +static struct bcm63xx_spi_pdata spi_pdata = {
59 + .bus_num = 0,
60 + .num_chipselect = 4,
61 + .speed_hz = 50000000, /* Fclk */
62 +};
63 +
64 +static struct platform_device bcm63xx_spi_device = {
65 + .name = "bcm63xx-spi",
66 + .id = 0,
67 + .num_resources = ARRAY_SIZE(spi_resources),
68 + .resource = spi_resources,
69 + .dev = {
70 + .platform_data = &spi_pdata,
71 + },
72 +};
73 +
74 +int __init bcm63xx_spi_register(void)
75 +{
76 + spi_resources[0].start = bcm63xx_regset_address(RSET_SPI);
77 + spi_resources[0].end = spi_resources[0].start;
78 + spi_resources[0].end += RSET_SPI_SIZE - 1;
79 + spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
80 +
81 + /* Fill in platform data */
82 + if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
83 + spi_pdata.fifo_size = SPI_BCM_6338_SPI_MSG_DATA_SIZE;
84 +
85 + if (BCMCPU_IS_6358())
86 + spi_pdata.fifo_size = SPI_BCM_6358_SPI_MSG_DATA_SIZE;
87 +
88 + return platform_device_register(&bcm63xx_spi_device);
89 +}
90 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
91 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
92 @@ -428,6 +428,7 @@ static inline unsigned long bcm63xx_regs
93 */
94 enum bcm63xx_irq {
95 IRQ_TIMER = 0,
96 + IRQ_SPI,
97 IRQ_UART0,
98 IRQ_DSL,
99 IRQ_UDC0,
100 @@ -493,6 +494,7 @@ enum bcm63xx_irq {
101 * 6348 irqs
102 */
103 #define BCM_6348_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
104 +#define BCM_6348_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
105 #define BCM_6348_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
106 #define BCM_6348_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
107 #define BCM_6348_UDC0_IRQ (IRQ_INTERNAL_BASE + 6)
108 @@ -517,6 +519,7 @@ enum bcm63xx_irq {
109 * 6358 irqs
110 */
111 #define BCM_6358_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
112 +#define BCM_6358_SPI_IRQ (IRQ_INTERNAL_BASE + 1)
113 #define BCM_6358_UART0_IRQ (IRQ_INTERNAL_BASE + 2)
114 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
115 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
116 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
117 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
118 @@ -769,5 +769,117 @@
119 #define DMIPSPLLCFG_N2_SHIFT 29
120 #define DMIPSPLLCFG_N2_MASK (0x7 << DMIPSPLLCFG_N2_SHIFT)
121
122 +/*************************************************************************
123 + * _REG relative to RSET_SPI
124 + *************************************************************************/
125 +
126 +/* BCM 6338 SPI core */
127 +#define SPI_BCM_6338_SPI_CMD 0x00 /* 16-bits register */
128 +#define SPI_BCM_6338_SPI_INT_STATUS 0x02
129 +#define SPI_BCM_6338_SPI_MASK_INT_ST 0x03
130 +#define SPI_BCM_6338_SPI_INT_MASK 0x04
131 +#define SPI_BCM_6338_SPI_ST 0x05
132 +#define SPI_BCM_6338_SPI_CLK_CFG 0x06
133 +#define SPI_BCM_6338_SPI_FILL_BYTE 0x07
134 +#define SPI_BCM_6338_SPI_MSG_TAIL 0x09
135 +#define SPI_BCM_6338_SPI_RX_TAIL 0x0b
136 +#define SPI_BCM_6338_SPI_MSG_CTL 0x40
137 +#define SPI_BCM_6338_SPI_MSG_DATA 0x41
138 +#define SPI_BCM_6338_SPI_MSG_DATA_SIZE 0x3f
139 +#define SPI_BCM_6338_SPI_RX_DATA 0x80
140 +#define SPI_BCM_6338_SPI_RX_DATA_SIZE 0x3f
141 +
142 +/* BCM 6348 SPI core */
143 +#define SPI_BCM_6348_SPI_MASK_INT_ST 0x00
144 +#define SPI_BCM_6348_SPI_INT_STATUS 0x01
145 +#define SPI_BCM_6348_SPI_CMD 0x02 /* 16-bits register */
146 +#define SPI_BCM_6348_SPI_FILL_BYTE 0x04
147 +#define SPI_BCM_6348_SPI_CLK_CFG 0x05
148 +#define SPI_BCM_6348_SPI_ST 0x06
149 +#define SPI_BCM_6348_SPI_INT_MASK 0x07
150 +#define SPI_BCM_6348_SPI_RX_TAIL 0x08
151 +#define SPI_BCM_6348_SPI_MSG_TAIL 0x10
152 +#define SPI_BCM_6348_SPI_MSG_DATA 0x40
153 +#define SPI_BCM_6348_SPI_MSG_CTL 0x42
154 +#define SPI_BCM_6348_SPI_MSG_DATA_SIZE 0x3f
155 +#define SPI_BCM_6348_SPI_RX_DATA 0x80
156 +#define SPI_BCM_6348_SPI_RX_DATA_SIZE 0x3f
157 +
158 +/* BCM 6358 SPI core */
159 +#define SPI_BCM_6358_MSG_CTL 0x00 /* 16-bits register */
160 +
161 +#define SPI_BCM_6358_SPI_MSG_DATA 0x02
162 +#define SPI_BCM_6358_SPI_MSG_DATA_SIZE 0x21e
163 +
164 +#define SPI_BCM_6358_SPI_RX_DATA 0x400
165 +#define SPI_BCM_6358_SPI_RX_DATA_SIZE 0x220
166 +
167 +#define SPI_BCM_6358_SPI_CMD 0x700 /* 16-bits register */
168 +
169 +#define SPI_BCM_6358_SPI_INT_STATUS 0x702
170 +#define SPI_BCM_6358_SPI_MASK_INT_ST 0x703
171 +
172 +#define SPI_BCM_6358_SPI_INT_MASK 0x704
173 +
174 +#define SPI_BCM_6358_SPI_STATUS 0x705
175 +
176 +#define SPI_BCM_6358_SPI_CLK_CFG 0x706
177 +
178 +#define SPI_BCM_6358_SPI_FILL_BYTE 0x707
179 +#define SPI_BCM_6358_SPI_MSG_TAIL 0x709
180 +#define SPI_BCM_6358_SPI_RX_TAIL 0x70B
181 +
182 +/* Shared SPI definitions */
183 +
184 +/* Message configuration */
185 +#define SPI_FD_RW 0x00
186 +#define SPI_HD_W 0x01
187 +#define SPI_HD_R 0x02
188 +#define SPI_BYTE_CNT_SHIFT 0
189 +#define SPI_MSG_TYPE_SHIFT 14
190 +
191 +/* Command */
192 +#define SPI_CMD_NOOP 0x01
193 +#define SPI_CMD_SOFT_RESET 0x02
194 +#define SPI_CMD_HARD_RESET 0x04
195 +#define SPI_CMD_START_IMMEDIATE 0x08
196 +#define SPI_CMD_COMMAND_SHIFT 0
197 +#define SPI_CMD_COMMAND_MASK 0x000f
198 +#define SPI_CMD_DEVICE_ID_SHIFT 4
199 +#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT 8
200 +#define SPI_CMD_ONE_BYTE_SHIFT 11
201 +#define SPI_CMD_ONE_WIRE_SHIFT 12
202 +#define SPI_DEV_ID_0 0
203 +#define SPI_DEV_ID_1 1
204 +#define SPI_DEV_ID_2 2
205 +#define SPI_DEV_ID_3 3
206 +
207 +/* Interrupt mask */
208 +#define SPI_INTR_CMD_DONE 0x01
209 +#define SPI_INTR_RX_OVERFLOW 0x02
210 +#define SPI_INTR_TX_UNDERFLOW 0x04
211 +#define SPI_INTR_TX_OVERFLOW 0x08
212 +#define SPI_INTR_RX_UNDERFLOW 0x10
213 +#define SPI_INTR_CLEAR_ALL 0x1f
214 +
215 +/* Status */
216 +#define SPI_RX_EMPTY 0x02
217 +#define SPI_CMD_BUSY 0x04
218 +#define SPI_SERIAL_BUSY 0x08
219 +
220 +/* Clock configuration */
221 +#define SPI_CLK_20MHZ 0x00
222 +#define SPI_CLK_0_391MHZ 0x01
223 +#define SPI_CLK_0_781MHZ 0x02 /* default */
224 +#define SPI_CLK_1_563MHZ 0x03
225 +#define SPI_CLK_3_125MHZ 0x04
226 +#define SPI_CLK_6_250MHZ 0x05
227 +#define SPI_CLK_12_50MHZ 0x06
228 +#define SPI_CLK_25MHZ 0x07
229 +#define SPI_CLK_MASK 0x07
230 +#define SPI_SSOFFTIME_MASK 0x38
231 +#define SPI_SSOFFTIME_SHIFT 3
232 +#define SPI_BYTE_SWAP 0x80
233 +
234 #endif /* BCM63XX_REGS_H_ */
235
236 --- /dev/null
237 +++ b/drivers/spi/bcm63xx_spi.c
238 @@ -0,0 +1,628 @@
239 +/*
240 + * Broadcom BCM63xx SPI controller support
241 + *
242 + * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
243 + *
244 + * This program is free software; you can redistribute it and/or
245 + * modify it under the terms of the GNU General Public License
246 + * as published by the Free Software Foundation; either version 2
247 + * of the License, or (at your option) any later version.
248 + *
249 + * This program is distributed in the hope that it will be useful,
250 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
251 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
252 + * GNU General Public License for more details.
253 + *
254 + * You should have received a copy of the GNU General Public License
255 + * along with this program; if not, write to the
256 + * Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
257 + */
258 +
259 +#include <linux/kernel.h>
260 +#include <linux/init.h>
261 +#include <linux/clk.h>
262 +#include <linux/module.h>
263 +#include <linux/platform_device.h>
264 +#include <linux/delay.h>
265 +#include <linux/interrupt.h>
266 +#include <linux/spi/spi.h>
267 +#include <linux/spi/spi_bitbang.h>
268 +#include <linux/gpio.h>
269 +#include <linux/completion.h>
270 +#include <linux/err.h>
271 +
272 +#include <bcm63xx_io.h>
273 +#include <bcm63xx_regs.h>
274 +#include <bcm63xx_dev_spi.h>
275 +
276 +#define PFX KBUILD_MODNAME
277 +#define DRV_VER "0.1.2"
278 +
279 +enum bcm63xx_regs_spi {
280 + SPI_CMD,
281 + SPI_INT_STATUS,
282 + SPI_INT_MASK_ST,
283 + SPI_INT_MASK,
284 + SPI_ST,
285 + SPI_CLK_CFG,
286 + SPI_FILL_BYTE,
287 + SPI_MSG_TAIL,
288 + SPI_RX_TAIL,
289 + SPI_MSG_CTL,
290 + SPI_MSG_DATA,
291 + SPI_RX_DATA,
292 +};
293 +
294 +/*
295 + * register offsets
296 + */
297 +static const unsigned long bcm96338_regs_spi[] = {
298 + [SPI_CMD] = SPI_BCM_6338_SPI_CMD,
299 + [SPI_INT_STATUS] = SPI_BCM_6338_SPI_INT_STATUS,
300 + [SPI_INT_MASK_ST] = SPI_BCM_6338_SPI_MASK_INT_ST,
301 + [SPI_INT_MASK] = SPI_BCM_6338_SPI_INT_MASK,
302 + [SPI_ST] = SPI_BCM_6338_SPI_ST,
303 + [SPI_CLK_CFG] = SPI_BCM_6338_SPI_CLK_CFG,
304 + [SPI_FILL_BYTE] = SPI_BCM_6338_SPI_FILL_BYTE,
305 + [SPI_MSG_TAIL] = SPI_BCM_6338_SPI_MSG_TAIL,
306 + [SPI_RX_TAIL] = SPI_BCM_6338_SPI_RX_TAIL,
307 + [SPI_MSG_CTL] = SPI_BCM_6338_SPI_MSG_CTL,
308 + [SPI_MSG_DATA] = SPI_BCM_6338_SPI_MSG_DATA,
309 + [SPI_RX_DATA] = SPI_BCM_6338_SPI_RX_DATA,
310 +};
311 +
312 +static const unsigned long bcm96348_regs_spi[] = {
313 + [SPI_CMD] = SPI_BCM_6348_SPI_CMD,
314 + [SPI_INT_STATUS] = SPI_BCM_6348_SPI_INT_STATUS,
315 + [SPI_INT_MASK_ST] = SPI_BCM_6348_SPI_MASK_INT_ST,
316 + [SPI_INT_MASK] = SPI_BCM_6348_SPI_INT_MASK,
317 + [SPI_ST] = SPI_BCM_6348_SPI_ST,
318 + [SPI_CLK_CFG] = SPI_BCM_6348_SPI_CLK_CFG,
319 + [SPI_FILL_BYTE] = SPI_BCM_6348_SPI_FILL_BYTE,
320 + [SPI_MSG_TAIL] = SPI_BCM_6348_SPI_MSG_TAIL,
321 + [SPI_RX_TAIL] = SPI_BCM_6348_SPI_RX_TAIL,
322 + [SPI_MSG_CTL] = SPI_BCM_6348_SPI_MSG_CTL,
323 + [SPI_MSG_DATA] = SPI_BCM_6348_SPI_MSG_DATA,
324 + [SPI_RX_DATA] = SPI_BCM_6348_SPI_RX_DATA,
325 +};
326 +
327 +static const unsigned long bcm96358_regs_spi[] = {
328 + [SPI_CMD] = SPI_BCM_6358_SPI_CMD,
329 + [SPI_INT_STATUS] = SPI_BCM_6358_SPI_INT_STATUS,
330 + [SPI_INT_MASK_ST] = SPI_BCM_6358_SPI_MASK_INT_ST,
331 + [SPI_INT_MASK] = SPI_BCM_6358_SPI_INT_MASK,
332 + [SPI_ST] = SPI_BCM_6358_SPI_STATUS,
333 + [SPI_CLK_CFG] = SPI_BCM_6358_SPI_CLK_CFG,
334 + [SPI_FILL_BYTE] = SPI_BCM_6358_SPI_FILL_BYTE,
335 + [SPI_MSG_TAIL] = SPI_BCM_6358_SPI_MSG_TAIL,
336 + [SPI_RX_TAIL] = SPI_BCM_6358_SPI_RX_TAIL,
337 + [SPI_MSG_CTL] = SPI_BCM_6358_MSG_CTL,
338 + [SPI_MSG_DATA] = SPI_BCM_6358_SPI_MSG_DATA,
339 + [SPI_RX_DATA] = SPI_BCM_6358_SPI_RX_DATA,
340 +};
341 +
342 +
343 +#ifdef BCMCPU_RUNTIME_DETECT
344 +static const unsigned long *bcm63xx_regs_spi;
345 +
346 +static __init void bcm63xx_spi_regs_init(void)
347 +{
348 + if (BCMCPU_IS_6338())
349 + bcm63xx_regs_spi = bcm96338_regs_spi;
350 + if (BCMCPU_IS_6348())
351 + bcm63xx_regs_spi = bcm96348_regs_spi;
352 + if (BCMCPU_IS_6358())
353 + bcm63xx_regs_spi = bcm96358_regs_spi;
354 +}
355 +#else
356 +static __init void bcm63xx_spi_regs_init(void) { }
357 +#endif
358 +
359 +static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
360 +{
361 +#ifdef BCMCPU_RUNTIME_DETECT
362 + return bcm63xx_regs_spi[reg];
363 +#else
364 +#ifdef CONFIG_BCM63XX_CPU_6338
365 +switch (reg) {
366 + case SPI_CMD:
367 + return SPI_BCM_6338_SPI_CMD;
368 + case SPI_INT_STATUS:
369 + return SPI_BCM_6338_SPI_INT_STATUS;
370 + case SPI_INT_MASK_ST:
371 + return SPI_BCM_6338_SPI_MASK_INT_ST;
372 + case SPI_INT_MASK:
373 + return SPI_BCM_6338_SPI_INT_MASK;
374 + case SPI_ST:
375 + return SPI_BCM_6338_SPI_ST;
376 + case SPI_CLK_CFG:
377 + return SPI_BCM_6338_SPI_CLK_CFG;
378 + case SPI_FILL_BYTE:
379 + return SPI_BCM_6338_SPI_FILL_BYTE;
380 + case SPI_MSG_TAIL:
381 + return SPI_BCM_6338_SPI_MSG_TAIL;
382 + case SPI_RX_TAIL:
383 + return SPI_BCM_6338_SPI_RX_TAIL;
384 + case SPI_MSG_CTL:
385 + return SPI_BCM_6338_SPI_MSG_CTL;
386 + case SPI_MSG_DATA:
387 + return SPI_BCM_6338_SPI_MSG_DATA;
388 + case SPI_RX_DATA:
389 + return SPI_BCM_6338_SPI_RX_DATA;
390 +}
391 +#endif
392 +#ifdef CONFIG_BCM63XX_CPU_6348
393 +switch (reg) {
394 + case SPI_CMD:
395 + return SPI_BCM_6348_SPI_CMD;
396 + case SPI_INT_MASK_ST:
397 + return SPI_BCM_6348_SPI_MASK_INT_ST;
398 + case SPI_INT_MASK:
399 + return SPI_BCM_6348_SPI_INT_MASK;
400 + case SPI_INT_STATUS:
401 + return SPI_BCM_6348_SPI_INT_STATUS;
402 + case SPI_ST:
403 + return SPI_BCM_6348_SPI_ST;
404 + case SPI_CLK_CFG:
405 + return SPI_BCM_6348_SPI_CLK_CFG;
406 + case SPI_FILL_BYTE:
407 + return SPI_BCM_6348_SPI_FILL_BYTE;
408 + case SPI_MSG_TAIL:
409 + return SPI_BCM_6348_SPI_MSG_TAIL;
410 + case SPI_RX_TAIL:
411 + return SPI_BCM_6348_SPI_RX_TAIL;
412 + case SPI_MSG_CTL:
413 + return SPI_BCM_6348_SPI_MSG_CTL;
414 + case SPI_MSG_DATA:
415 + return SPI_BCM_6348_SPI_MSG_DATA;
416 + case SPI_RX_DATA:
417 + return SPI_BCM_6348_SPI_RX_DATA;
418 +}
419 +#endif
420 +#ifdef CONFIG_BCM63XX_CPU_6358
421 +switch (reg) {
422 + case SPI_CMD:
423 + return SPI_BCM_6358_SPI_CMD;
424 + case SPI_INT_STATUS:
425 + return SPI_BCM_6358_SPI_INT_STATUS;
426 + case SPI_INT_MASK_ST:
427 + return SPI_BCM_6358_SPI_MASK_INT_ST;
428 + case SPI_INT_MASK:
429 + return SPI_BCM_6358_SPI_INT_MASK;
430 + case SPI_ST:
431 + return SPI_BCM_6358_SPI_STATUS;
432 + case SPI_CLK_CFG:
433 + return SPI_BCM_6358_SPI_CLK_CFG;
434 + case SPI_FILL_BYTE:
435 + return SPI_BCM_6358_SPI_FILL_BYTE;
436 + case SPI_MSG_TAIL:
437 + return SPI_BCM_6358_SPI_MSG_TAIL;
438 + case SPI_RX_TAIL:
439 + return SPI_BCM_6358_SPI_RX_TAIL;
440 + case SPI_MSG_CTL:
441 + return SPI_BCM_6358_MSG_CTL;
442 + case SPI_MSG_DATA:
443 + return SPI_BCM_6358_SPI_MSG_DATA;
444 + case SPI_RX_DATA:
445 + return SPI_BCM_6358_SPI_RX_DATA;
446 +}
447 +#endif
448 +#endif
449 + return 0;
450 +}
451 +
452 +/*
453 + * helpers for the SPI register sets
454 + */
455 +#define bcm_spi_readb(b,o) bcm_readb((b) + bcm63xx_spireg(o))
456 +#define bcm_spi_readw(b,o) bcm_readw((b) + bcm63xx_spireg(o))
457 +#define bcm_spi_writeb(v,b,o) bcm_writeb((v), (b) + bcm63xx_spireg(o))
458 +#define bcm_spi_writew(v,b,o) bcm_writew((v), (b) + bcm63xx_spireg(o))
459 +
460 +struct bcm63xx_spi {
461 + /* bitbang has to be first */
462 + struct spi_bitbang bitbang;
463 + struct completion done;
464 +
465 + void __iomem *regs;
466 + int irq;
467 +
468 + /* Platform data */
469 + u32 speed_hz;
470 + unsigned fifo_size;
471 +
472 + /* Data buffers */
473 + const unsigned char *tx_ptr;
474 + unsigned char *rx_ptr;
475 + int remaining_bytes;
476 +
477 + struct clk *clk;
478 + struct resource *ioarea;
479 + struct platform_device *pdev;
480 +};
481 +
482 +static void bcm63xx_spi_chipselect(struct spi_device *spi, int is_on)
483 +{
484 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
485 + u16 val;
486 +
487 + val = bcm_spi_readw(bs->regs, SPI_CMD);
488 + if (is_on == BITBANG_CS_INACTIVE)
489 + val |= SPI_CMD_NOOP;
490 + else if (is_on == BITBANG_CS_ACTIVE)
491 + val |= (1 << spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
492 +
493 + bcm_spi_writew(val, bs->regs, SPI_CMD);
494 +}
495 +
496 +static int bcm63xx_spi_setup_transfer(struct spi_device *spi,
497 + struct spi_transfer *t)
498 +{
499 + u8 bits_per_word;
500 + u8 clk_cfg;
501 + u32 hz;
502 + unsigned int div;
503 +
504 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
505 +
506 + bits_per_word = (t) ? t->bits_per_word : spi->bits_per_word;
507 + hz = (t) ? t->speed_hz : spi->max_speed_hz;
508 + if (bits_per_word != 8) {
509 + dev_err(&spi->dev, "%s, unsupported bits_per_word=%d\n",
510 + __func__, bits_per_word);
511 + return -EINVAL;
512 + }
513 +
514 + if (spi->chip_select > spi->master->num_chipselect) {
515 + dev_err(&spi->dev, "%s, unsupported slave %d\n",
516 + __func__, spi->chip_select);
517 + return -EINVAL;
518 + }
519 +
520 + /* Check clock setting */
521 + div = (bs->speed_hz / hz);
522 + switch (div) {
523 + case 2:
524 + clk_cfg = SPI_CLK_25MHZ;
525 + break;
526 + case 4:
527 + clk_cfg = SPI_CLK_12_50MHZ;
528 + break;
529 + case 8:
530 + clk_cfg = SPI_CLK_6_250MHZ;
531 + break;
532 + case 16:
533 + clk_cfg = SPI_CLK_3_125MHZ;
534 + break;
535 + case 32:
536 + clk_cfg = SPI_CLK_1_563MHZ;
537 + break;
538 + case 128:
539 + clk_cfg = SPI_CLK_0_781MHZ;
540 + break;
541 + case 64:
542 + default:
543 + /* Set to slowest mode for compatibility */
544 + clk_cfg = SPI_CLK_0_781MHZ;
545 + break;
546 + }
547 +
548 + bcm_spi_writeb(clk_cfg, bs->regs, SPI_CLK_CFG);
549 + dev_dbg(&spi->dev, "Setting clock register to %d (hz %d, cmd %02x)\n",
550 + div, hz, clk_cfg);
551 +
552 + return 0;
553 +}
554 +
555 +/* the spi->mode bits understood by this driver: */
556 +#define MODEBITS (SPI_CPOL | SPI_CPHA)
557 +
558 +static int bcm63xx_spi_setup(struct spi_device *spi)
559 +{
560 + struct spi_bitbang *bitbang;
561 + struct bcm63xx_spi *bs;
562 + int retval;
563 +
564 + bs = spi_master_get_devdata(spi->master);
565 + bitbang = &bs->bitbang;
566 +
567 + if (!spi->bits_per_word)
568 + spi->bits_per_word = 8;
569 +
570 + if (spi->mode & ~MODEBITS) {
571 + dev_err(&spi->dev, "%s, unsupported mode bits %x\n",
572 + __func__, spi->mode & ~MODEBITS);
573 + return -EINVAL;
574 + }
575 +
576 + retval = bcm63xx_spi_setup_transfer(spi, NULL);
577 + if (retval < 0) {
578 + dev_err(&spi->dev, "setup: unsupported mode bits %x\n",
579 + spi->mode & ~MODEBITS);
580 + return retval;
581 + }
582 +
583 + dev_dbg(&spi->dev, "%s, mode %d, %u bits/w, %u nsec/bit\n",
584 + __func__, spi->mode & MODEBITS, spi->bits_per_word, 0);
585 +
586 + return 0;
587 +}
588 +
589 +/* Fill the TX FIFO with as many bytes as possible */
590 +static void bcm63xx_spi_fill_tx_fifo(struct bcm63xx_spi *bs)
591 +{
592 + u8 tail;
593 +
594 + /* Fill the Tx FIFO with as many bytes as possible */
595 + tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
596 + while ((tail < bs->fifo_size) && (bs->remaining_bytes > 0)) {
597 + if (bs->tx_ptr)
598 + bcm_spi_writeb(*bs->tx_ptr++, bs->regs, SPI_MSG_DATA);
599 + else
600 + bcm_spi_writeb(0, bs->regs, SPI_MSG_DATA);
601 + bs->remaining_bytes--;
602 + tail = bcm_spi_readb(bs->regs, SPI_MSG_TAIL);
603 + }
604 +}
605 +
606 +static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
607 +{
608 + struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
609 + u8 msg_ctl;
610 + u16 cmd;
611 +
612 + dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
613 + t->tx_buf, t->rx_buf, t->len);
614 +
615 + /* Transmitter is inhibited */
616 + bs->tx_ptr = t->tx_buf;
617 + bs->rx_ptr = t->rx_buf;
618 + bs->remaining_bytes = t->len;
619 + init_completion(&bs->done);
620 +
621 + bcm63xx_spi_fill_tx_fifo(bs);
622 +
623 + /* Enable the command done interrupt which
624 + * we use to determine completion of a command */
625 + bcm_spi_writeb(SPI_INTR_CMD_DONE, bs->regs, SPI_INT_MASK);
626 +
627 + /* Fill in the Message control register */
628 + msg_ctl = bcm_spi_readb(bs->regs, SPI_MSG_CTL);
629 + msg_ctl |= (t->len << SPI_BYTE_CNT_SHIFT);
630 + msg_ctl |= (SPI_FD_RW << SPI_MSG_TYPE_SHIFT);
631 + bcm_spi_writeb(msg_ctl, bs->regs, SPI_MSG_CTL);
632 +
633 + /* Issue the transfer */
634 + cmd = bcm_spi_readb(bs->regs, SPI_CMD);
635 + cmd |= SPI_CMD_START_IMMEDIATE;
636 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
637 + bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
638 +
639 + wait_for_completion(&bs->done);
640 +
641 + /* Disable the CMD_DONE interrupt */
642 + bcm_spi_writeb(~(SPI_INTR_CMD_DONE), bs->regs, SPI_INT_MASK);
643 +
644 + return t->len - bs->remaining_bytes;
645 +}
646 +
647 +/* This driver supports single master mode only. Hence
648 + * CMD_DONE is the only interrupt we care about
649 + */
650 +static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
651 +{
652 + struct spi_master *master = (struct spi_master *)dev_id;
653 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
654 + u8 intr;
655 + u16 cmd;
656 +
657 + /* Read interupts and clear them immediately */
658 + intr = bcm_spi_readb(bs->regs, SPI_INT_STATUS);
659 + bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
660 +
661 + /* A tansfer completed */
662 + if (intr & SPI_INTR_CMD_DONE) {
663 + u8 rx_empty;
664 +
665 + rx_empty = bcm_spi_readb(bs->regs, SPI_ST);
666 + /* Read out all the data */
667 + while ((rx_empty & SPI_RX_EMPTY) == 0) {
668 + u8 data;
669 +
670 + data = bcm_spi_readb(bs->regs, SPI_RX_DATA);
671 + if (bs->rx_ptr)
672 + *bs->rx_ptr++ = data;
673 +
674 + rx_empty = bcm_spi_readb(bs->regs, SPI_RX_EMPTY);
675 + }
676 +
677 + /* See if there is more data to send */
678 + if (bs->remaining_bytes > 0) {
679 + bcm63xx_spi_fill_tx_fifo(bs);
680 +
681 + /* Start the transfer */
682 + cmd = bcm_spi_readb(bs->regs, SPI_CMD);
683 + cmd |= SPI_CMD_START_IMMEDIATE;
684 + cmd |= (0 << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
685 + bcm_spi_writeb(cmd, bs->regs, SPI_CMD);
686 + } else
687 + complete(&bs->done);
688 + }
689 +
690 + return IRQ_HANDLED;
691 +}
692 +
693 +
694 +static int __init bcm63xx_spi_probe(struct platform_device *pdev)
695 +{
696 + struct resource *r;
697 + struct bcm63xx_spi_pdata *pdata = pdev->dev.platform_data;
698 + int irq;
699 + struct spi_master *master;
700 + struct clk *clk;
701 + struct bcm63xx_spi *bs;
702 + int ret;
703 +
704 + r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
705 + if (!r) {
706 + ret = -ENXIO;
707 + goto out;
708 + }
709 +
710 + irq = platform_get_irq(pdev, 0);
711 + if (irq < 0) {
712 + ret = -ENXIO;
713 + goto out;
714 + }
715 +
716 + bcm63xx_spi_regs_init();
717 +
718 + clk = clk_get(&pdev->dev, "spi");
719 + if (IS_ERR(clk)) {
720 + dev_err(&pdev->dev, "No clock for device\n");
721 + ret = -ENODEV;
722 + goto out;
723 + }
724 +
725 + master = spi_alloc_master(&pdev->dev, sizeof(struct bcm63xx_spi));
726 + if (!master) {
727 + ret = -ENOMEM;
728 + goto out_free;
729 + }
730 +
731 + bs = spi_master_get_devdata(master);
732 + bs->bitbang.master = spi_master_get(master);
733 + bs->bitbang.chipselect = bcm63xx_spi_chipselect;
734 + bs->bitbang.setup_transfer = bcm63xx_spi_setup_transfer;
735 + bs->bitbang.txrx_bufs = bcm63xx_txrx_bufs;
736 + bs->bitbang.master->setup = bcm63xx_spi_setup;
737 + init_completion(&bs->done);
738 +
739 + platform_set_drvdata(pdev, master);
740 + bs->pdev = pdev;
741 +
742 + if (!request_mem_region(r->start,
743 + r->end - r->start, PFX)) {
744 + ret = -ENXIO;
745 + goto out_free;
746 + }
747 +
748 + bs->regs = ioremap_nocache(r->start, r->end - r->start);
749 + if (!bs->regs) {
750 + printk(KERN_ERR PFX " unable to ioremap regs\n");
751 + ret = -ENOMEM;
752 + goto out_free;
753 + }
754 + bs->irq = irq;
755 + bs->clk = clk;
756 + bs->fifo_size = pdata->fifo_size;
757 +
758 + ret = request_irq(irq, bcm63xx_spi_interrupt, 0,
759 + pdev->name, master);
760 + if (ret) {
761 + printk(KERN_ERR PFX " unable to request irq\n");
762 + goto out_unmap;
763 + }
764 +
765 + master->bus_num = pdata->bus_num;
766 + master->num_chipselect = pdata->num_chipselect;
767 + bs->speed_hz = pdata->speed_hz;
768 +
769 + /* Initialize hardware */
770 + clk_enable(bs->clk);
771 + bcm_spi_writeb(SPI_INTR_CLEAR_ALL, bs->regs, SPI_INT_MASK);
772 +
773 + dev_info(&pdev->dev, " at 0x%08x (irq %d, FIFOs size %d) v%s\n",
774 + r->start, irq, bs->fifo_size, DRV_VER);
775 +
776 + ret = spi_bitbang_start(&bs->bitbang);
777 + if (ret) {
778 + dev_err(&pdev->dev, "spi_bitbang_start FAILED\n");
779 + goto out_reset_hw;
780 + }
781 +
782 + return ret;
783 +
784 +out_reset_hw:
785 + clk_disable(clk);
786 + free_irq(irq, master);
787 +out_unmap:
788 + iounmap(bs->regs);
789 +out_free:
790 + clk_put(clk);
791 + spi_master_put(master);
792 +out:
793 + return ret;
794 +}
795 +
796 +static int __exit bcm63xx_spi_remove(struct platform_device *pdev)
797 +{
798 + struct spi_master *master = platform_get_drvdata(pdev);
799 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
800 +
801 + spi_bitbang_stop(&bs->bitbang);
802 + clk_disable(bs->clk);
803 + clk_put(bs->clk);
804 + free_irq(bs->irq, master);
805 + iounmap(bs->regs);
806 + platform_set_drvdata(pdev, 0);
807 + spi_master_put(bs->bitbang.master);
808 +
809 + return 0;
810 +}
811 +
812 +#ifdef CONFIG_PM
813 +static int bcm63xx_spi_suspend(struct platform_device *pdev, pm_message_t mesg)
814 +{
815 + struct spi_master *master = platform_get_drvdata(pdev);
816 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
817 +
818 + clk_disable(bs->clk);
819 +
820 + return 0;
821 +}
822 +
823 +static int bcm63xx_spi_resume(struct platform_device *pdev)
824 +{
825 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
826 + struct bcm63xx_spi *bs = spi_master_get_devdata(master);
827 +
828 + clk_enable(bs->clk);
829 +
830 + return 0;
831 +}
832 +#else
833 +#define bcm63xx_spi_suspend NULL
834 +#define bcm63xx_spi_resume NULL
835 +#endif
836 +
837 +static struct platform_driver bcm63xx_spi_driver = {
838 + .driver = {
839 + .name = "bcm63xx-spi",
840 + .owner = THIS_MODULE,
841 + },
842 + .probe = bcm63xx_spi_probe,
843 + .remove = bcm63xx_spi_remove,
844 + .suspend = bcm63xx_spi_suspend,
845 + .resume = bcm63xx_spi_resume,
846 +};
847 +
848 +
849 +static int __init bcm63xx_spi_init(void)
850 +{
851 + return platform_driver_register(&bcm63xx_spi_driver);
852 +}
853 +
854 +static void __exit bcm63xx_spi_exit(void)
855 +{
856 + platform_driver_unregister(&bcm63xx_spi_driver);
857 +}
858 +
859 +module_init(bcm63xx_spi_init);
860 +module_exit(bcm63xx_spi_exit);
861 +
862 +MODULE_ALIAS("platform:bcm63xx_spi");
863 +MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
864 +MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
865 +MODULE_LICENSE("GPL");
866 +MODULE_VERSION(DRV_VER);
867 --- a/drivers/spi/Kconfig
868 +++ b/drivers/spi/Kconfig
869 @@ -60,6 +60,13 @@ config SPI_ATMEL
870 This selects a driver for the Atmel SPI Controller, present on
871 many AT32 (AVR32) and AT91 (ARM) chips.
872
873 +config SPI_BCM63XX
874 + tristate "Broadcom BCM63xx SPI controller"
875 + depends on BCM63XX
876 + select SPI_BITBANG
877 + help
878 + This is the SPI controller master driver for Broadcom BCM63xx SoC.
879 +
880 config SPI_BFIN
881 tristate "SPI controller driver for ADI Blackfin5xx"
882 depends on BLACKFIN
883 --- a/drivers/spi/Makefile
884 +++ b/drivers/spi/Makefile
885 @@ -34,6 +34,7 @@ obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
886 obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
887 obj-$(CONFIG_SPI_SH_SCI) += spi_sh_sci.o
888 obj-$(CONFIG_SPI_STMP3XXX) += spi_stmp.o
889 +obj-$(CONFIG_SPI_BCM63XX) += bcm63xx_spi.o
890 # ... add above this line ...
891
892 # SPI protocol drivers (device/link on bus)
893 --- /dev/null
894 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
895 @@ -0,0 +1,15 @@
896 +#ifndef BCM63XX_DEV_SPI_H
897 +#define BCM63XX_DEV_SPI_H
898 +
899 +#include <linux/types.h>
900 +
901 +int __init bcm63xx_spi_register(void);
902 +
903 +struct bcm63xx_spi_pdata {
904 + unsigned int fifo_size;
905 + int bus_num;
906 + int num_chipselect;
907 + u32 speed_hz;
908 +};
909 +
910 +#endif /* BCM63XX_DEV_SPI_H */