kernel: fix bluetooth and zsmalloc for 3.14
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.13 / 324-MIPS-BCM63XX-protect-irq-register-accesses.patch
1 From 85257b702e1d4c6dcc839c737833c42ca53bae93 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sun, 21 Apr 2013 15:38:56 +0200
4 Subject: [PATCH 35/53] MIPS: BCM63XX: protect irq register accesses
5
6 ---
7 arch/mips/bcm63xx/irq.c | 26 ++++++++++++++++++++++++++
8 1 file changed, 26 insertions(+)
9
10 --- a/arch/mips/bcm63xx/irq.c
11 +++ b/arch/mips/bcm63xx/irq.c
12 @@ -12,6 +12,7 @@
13 #include <linux/interrupt.h>
14 #include <linux/module.h>
15 #include <linux/irq.h>
16 +#include <linux/spinlock.h>
17 #include <asm/irq_cpu.h>
18 #include <asm/mipsregs.h>
19 #include <bcm63xx_cpu.h>
20 @@ -20,6 +21,9 @@
21 #include <bcm63xx_irq.h>
22
23
24 +static DEFINE_SPINLOCK(ipic_lock);
25 +static DEFINE_SPINLOCK(epic_lock);
26 +
27 static u32 irq_stat_addr[2];
28 static u32 irq_mask_addr[2];
29 static void (*dispatch_internal)(int pin);
30 @@ -62,8 +66,10 @@ void __dispatch_internal_##width(int pin
31 bool irqs_pending = false; \
32 static int i[2]; \
33 int *next = &i[pin]; \
34 + unsigned long flags; \
35 \
36 /* read registers in reverse order */ \
37 + spin_lock_irqsave(&ipic_lock, flags); \
38 for (src = 0, tgt = (width / 32); src < (width / 32); src++) { \
39 u32 val; \
40 \
41 @@ -74,6 +80,7 @@ void __dispatch_internal_##width(int pin
42 if (val) \
43 irqs_pending = true; \
44 } \
45 + spin_unlock_irqrestore(&ipic_lock, flags); \
46 \
47 if (!irqs_pending) \
48 return; \
49 @@ -94,10 +101,13 @@ static void __internal_irq_mask_##width(
50 u32 val; \
51 unsigned reg = (irq / 32) ^ (width/32 - 1); \
52 unsigned bit = irq & 0x1f; \
53 + unsigned long flags; \
54 \
55 + spin_lock_irqsave(&ipic_lock, flags); \
56 val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
57 val &= ~(1 << bit); \
58 bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
59 + spin_unlock_irqrestore(&ipic_lock, flags); \
60 } \
61 \
62 static void __internal_irq_unmask_##width(unsigned int irq) \
63 @@ -105,10 +115,13 @@ static void __internal_irq_unmask_##widt
64 u32 val; \
65 unsigned reg = (irq / 32) ^ (width/32 - 1); \
66 unsigned bit = irq & 0x1f; \
67 + unsigned long flags; \
68 \
69 + spin_lock_irqsave(&ipic_lock, flags); \
70 val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32)); \
71 val |= (1 << bit); \
72 bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32)); \
73 + spin_unlock_irqrestore(&ipic_lock, flags); \
74 }
75
76 BUILD_IPIC_INTERNAL(32);
77 @@ -167,8 +180,10 @@ static void bcm63xx_external_irq_mask(st
78 {
79 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
80 u32 reg, regaddr;
81 + unsigned long flags;
82
83 regaddr = get_ext_irq_perf_reg(irq);
84 + spin_lock_irqsave(&epic_lock, flags);
85 reg = bcm_perf_readl(regaddr);
86
87 if (BCMCPU_IS_6348())
88 @@ -177,6 +192,8 @@ static void bcm63xx_external_irq_mask(st
89 reg &= ~EXTIRQ_CFG_MASK(irq % 4);
90
91 bcm_perf_writel(reg, regaddr);
92 + spin_unlock_irqrestore(&epic_lock, flags);
93 +
94 if (is_ext_irq_cascaded)
95 internal_irq_mask(irq + ext_irq_start);
96 }
97 @@ -185,8 +202,10 @@ static void bcm63xx_external_irq_unmask(
98 {
99 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
100 u32 reg, regaddr;
101 + unsigned long flags;
102
103 regaddr = get_ext_irq_perf_reg(irq);
104 + spin_lock_irqsave(&epic_lock, flags);
105 reg = bcm_perf_readl(regaddr);
106
107 if (BCMCPU_IS_6348())
108 @@ -195,6 +214,7 @@ static void bcm63xx_external_irq_unmask(
109 reg |= EXTIRQ_CFG_MASK(irq % 4);
110
111 bcm_perf_writel(reg, regaddr);
112 + spin_unlock_irqrestore(&epic_lock, flags);
113
114 if (is_ext_irq_cascaded)
115 internal_irq_unmask(irq + ext_irq_start);
116 @@ -204,8 +224,10 @@ static void bcm63xx_external_irq_clear(s
117 {
118 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
119 u32 reg, regaddr;
120 + unsigned long flags;
121
122 regaddr = get_ext_irq_perf_reg(irq);
123 + spin_lock_irqsave(&epic_lock, flags);
124 reg = bcm_perf_readl(regaddr);
125
126 if (BCMCPU_IS_6348())
127 @@ -214,6 +236,7 @@ static void bcm63xx_external_irq_clear(s
128 reg |= EXTIRQ_CFG_CLEAR(irq % 4);
129
130 bcm_perf_writel(reg, regaddr);
131 + spin_unlock_irqrestore(&epic_lock, flags);
132 }
133
134 static int bcm63xx_external_irq_set_type(struct irq_data *d,
135 @@ -222,6 +245,7 @@ static int bcm63xx_external_irq_set_type
136 unsigned int irq = d->irq - IRQ_EXTERNAL_BASE;
137 u32 reg, regaddr;
138 int levelsense, sense, bothedge;
139 + unsigned long flags;
140
141 flow_type &= IRQ_TYPE_SENSE_MASK;
142
143 @@ -256,6 +280,7 @@ static int bcm63xx_external_irq_set_type
144 }
145
146 regaddr = get_ext_irq_perf_reg(irq);
147 + spin_lock_irqsave(&epic_lock, flags);
148 reg = bcm_perf_readl(regaddr);
149 irq %= 4;
150
151 @@ -300,6 +325,7 @@ static int bcm63xx_external_irq_set_type
152 }
153
154 bcm_perf_writel(reg, regaddr);
155 + spin_unlock_irqrestore(&epic_lock, flags);
156
157 irqd_set_trigger_type(d, flow_type);
158 if (flow_type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))