kernel: fix bluetooth and zsmalloc for 3.14
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.13 / 347-MIPS-BCM6318-USB-support.patch
1 --- a/arch/mips/bcm63xx/usb-common.c
2 +++ b/arch/mips/bcm63xx/usb-common.c
3 @@ -109,6 +109,27 @@ void bcm63xx_usb_priv_ohci_cfg_set(void)
4 reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
5 reg |= USBH_PRIV_SETUP_IOC_MASK;
6 bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
7 + } else if (BCMCPU_IS_6318()) {
8 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
9 + reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
10 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
11 +
12 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
13 + reg &= ~USBH_PRIV_SWAP_OHCI_ENDN_MASK;
14 + reg |= USBH_PRIV_SWAP_OHCI_DATA_MASK;
15 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);
16 +
17 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);
18 + reg |= USBH_PRIV_SETUP_IOC_MASK;
19 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
20 +
21 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
22 + reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
23 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
24 +
25 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
26 + reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;
27 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);
28 }
29
30 spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
31 @@ -144,6 +165,27 @@ void bcm63xx_usb_priv_ehci_cfg_set(void)
32 reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6368_REG);
33 reg |= USBH_PRIV_SETUP_IOC_MASK;
34 bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6368_REG);
35 + } else if (BCMCPU_IS_6318()) {
36 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
37 + reg |= USBH_PRIV_PLL_CTRL1_SUSP_EN;
38 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
39 +
40 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SWAP_6318_REG);
41 + reg &= ~USBH_PRIV_SWAP_EHCI_ENDN_MASK;
42 + reg |= USBH_PRIV_SWAP_EHCI_DATA_MASK;
43 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SWAP_6318_REG);
44 +
45 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SETUP_6318_REG);
46 + reg |= USBH_PRIV_SETUP_IOC_MASK;
47 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SETUP_6318_REG);
48 +
49 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_PLL_CTRL1_6318_REG);
50 + reg &= ~USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN;
51 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_PLL_CTRL1_6318_REG);
52 +
53 + reg = bcm_rset_readl(RSET_USBH_PRIV, USBH_PRIV_SIM_CTRL_6318_REG);
54 + reg |= USBH_PRIV_SIM_CTRL_LADDR_SEL;
55 + bcm_rset_writel(RSET_USBH_PRIV, reg, USBH_PRIV_SIM_CTRL_6318_REG);
56 }
57
58 spin_unlock_irqrestore(&usb_priv_reg_lock, flags);
59 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
60 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
61 @@ -800,6 +800,12 @@
62 #define GPIO_MODE_6368_SPI_SSN4 (1 << 30)
63 #define GPIO_MODE_6368_SPI_SSN5 (1 << 31)
64
65 +#define GPIO_PINMUX_SEL0_6318 0x1c
66 +#define GPIO_PINMUX_SEL0_GPIO13_SHIFT 26
67 +#define GPIO_PINMUX_SEL0_GPIO13_MASK (0x3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
68 +#define GPIO_PINMUX_SEL0_GPIO13_PWRON (1 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
69 +#define GPIO_PINMUX_SEL0_GPIO13_LED (2 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
70 +#define GPIO_PINMUX_SEL0_GPIO13_GPIO (3 << GPIO_PINMUX_SEL0_GPIO13_SHIFT)
71
72 #define GPIO_PINMUX_OTHR_REG 0x24
73 #define GPIO_PINMUX_OTHR_6328_USB_SHIFT 12
74 @@ -1118,6 +1124,7 @@
75
76 #define USBH_PRIV_SWAP_6358_REG 0x0
77 #define USBH_PRIV_SWAP_6368_REG 0x1c
78 +#define USBH_PRIV_SWAP_6318_REG 0x0c
79
80 #define USBH_PRIV_SWAP_USBD_SHIFT 6
81 #define USBH_PRIV_SWAP_USBD_MASK (1 << USBH_PRIV_SWAP_USBD_SHIFT)
82 @@ -1143,6 +1150,13 @@
83 #define USBH_PRIV_SETUP_IOC_SHIFT 4
84 #define USBH_PRIV_SETUP_IOC_MASK (1 << USBH_PRIV_SETUP_IOC_SHIFT)
85
86 +#define USBH_PRIV_SETUP_6318_REG 0x00
87 +#define USBH_PRIV_PLL_CTRL1_6318_REG 0x04
88 +#define USBH_PRIV_PLL_CTRL1_SUSP_EN (1 << 27)
89 +#define USBH_PRIV_PLL_CTRL1_IDDQ_PWRDN (1 << 31)
90 +#define USBH_PRIV_SIM_CTRL_6318_REG 0x20
91 +#define USBH_PRIV_SIM_CTRL_LADDR_SEL (1 << 5)
92 +
93
94 /*************************************************************************
95 * _REG relative to RSET_USBD
96 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
97 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
98 @@ -914,6 +914,15 @@ void __init board_prom_init(void)
99 }
100
101 bcm_gpio_writel(val, GPIO_MODE_REG);
102 +
103 +#if IS_ENABLED(CONFIG_USB)
104 + if (BCMCPU_IS_6318() && (board.has_ehci0 || board.has_ohci0)) {
105 + val = bcm_gpio_readl(GPIO_PINMUX_SEL0_6318);
106 + val &= ~GPIO_PINMUX_SEL0_GPIO13_MASK;
107 + val |= GPIO_PINMUX_SEL0_GPIO13_PWRON;
108 + bcm_gpio_writel(val, GPIO_PINMUX_SEL0_6318);
109 + }
110 +#endif
111 }
112
113 /*
114 --- a/arch/mips/bcm63xx/Kconfig
115 +++ b/arch/mips/bcm63xx/Kconfig
116 @@ -22,6 +22,8 @@ config BCM63XX_CPU_6318
117 bool "support 6318 CPU"
118 select SYS_HAS_CPU_BMIPS32_3300
119 select HW_HAS_PCI
120 + select BCM63XX_OHCI
121 + select BCM63XX_EHCI
122
123 config BCM63XX_CPU_6328
124 bool "support 6328 CPU"