target/linux/brcm63xx/patches-3.14/030-MIPS-Always-use-IRQ-domains-for-CPU-IRQs.patch

   1 From 0f84c305351c993e4307e1e8c128d44760314e31 Mon Sep 17 00:00:00 2001
   2 From: Andrew Bresticker <abrestic@chromium.org>
   3 Date: Thu, 18 Sep 2014 14:47:07 -0700
   4 Subject: [PATCH 1/3] MIPS: Always use IRQ domains for CPU IRQs
   5
   6 Use an IRQ domain for the 8 CPU IRQs in both the DT and non-DT cases.
   7
   8 Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
   9 Reviewed-by: Qais Yousef <qais.yousef@imgtec.com>
  10 Tested-by: Qais Yousef <qais.yousef@imgtec.com>
  11 Cc: Thomas Gleixner <tglx@linutronix.de>
  12 Cc: Jason Cooper <jason@lakedaemon.net>
  13 Cc: Andrew Bresticker <abrestic@chromium.org>
  14 Cc: Jeffrey Deans <jeffrey.deans@imgtec.com>
  15 Cc: Markos Chandras <markos.chandras@imgtec.com>
  16 Cc: Paul Burton <paul.burton@imgtec.com>
  17 Cc: Qais Yousef <qais.yousef@imgtec.com>
  18 Cc: Jonas Gorski <jogo@openwrt.org>
  19 Cc: John Crispin <blogic@openwrt.org>
  20 Cc: David Daney <ddaney.cavm@gmail.com>
  21 Cc: linux-mips@linux-mips.org
  22 Cc: linux-kernel@vger.kernel.org
  23 Patchwork: https://patchwork.linux-mips.org/patch/7799/
  24 Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
  25 ---
  26  arch/mips/Kconfig          |    1 +
  27  arch/mips/kernel/irq_cpu.c |   36 +++++++++++-------------------------
  28  2 files changed, 12 insertions(+), 25 deletions(-)
  29
  30 --- a/arch/mips/Kconfig
  31 +++ b/arch/mips/Kconfig
  32 @@ -1026,6 +1026,7 @@ config MIPS_HUGE_TLB_SUPPORT
  33
  34  config IRQ_CPU
  35         bool
  36 +       select IRQ_DOMAIN
  37
  38  config IRQ_CPU_RM7K
  39         bool
  40 --- a/arch/mips/kernel/irq_cpu.c
  41 +++ b/arch/mips/kernel/irq_cpu.c
  42 @@ -98,28 +98,6 @@ static struct irq_chip mips_mt_cpu_irq_c
  43         .irq_enable     = unmask_mips_irq,
  44  };
  45
  46 -void __init mips_cpu_irq_init(void)
  47 -{
  48 -       int irq_base = MIPS_CPU_IRQ_BASE;
  49 -       int i;
  50 -
  51 -       /* Mask interrupts. */
  52 -       clear_c0_status(ST0_IM);
  53 -       clear_c0_cause(CAUSEF_IP);
  54 -
  55 -       /* Software interrupts are used for MT/CMT IPI */
  56 -       for (i = irq_base; i < irq_base + 2; i++)
  57 -               irq_set_chip_and_handler(i, cpu_has_mipsmt ?
  58 -                                        &mips_mt_cpu_irq_controller :
  59 -                                        &mips_cpu_irq_controller,
  60 -                                        handle_percpu_irq);
  61 -
  62 -       for (i = irq_base + 2; i < irq_base + 8; i++)
  63 -               irq_set_chip_and_handler(i, &mips_cpu_irq_controller,
  64 -                                        handle_percpu_irq);
  65 -}
  66 -
  67 -#ifdef CONFIG_IRQ_DOMAIN
  68  static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
  69                              irq_hw_number_t hw)
  70  {
  71 @@ -142,8 +120,7 @@ static const struct irq_domain_ops mips_
  72         .xlate = irq_domain_xlate_onecell,
  73  };
  74
  75 -int __init mips_cpu_intc_init(struct device_node *of_node,
  76 -                             struct device_node *parent)
  77 +static void __init __mips_cpu_irq_init(struct device_node *of_node)
  78  {
  79         struct irq_domain *domain;
  80
  81 @@ -155,7 +132,16 @@ int __init mips_cpu_intc_init(struct dev
  82                                        &mips_cpu_intc_irq_domain_ops, NULL);
  83         if (!domain)
  84                 panic("Failed to add irqdomain for MIPS CPU");
  85 +}
  86
  87 +void __init mips_cpu_irq_init(void)
  88 +{
  89 +       __mips_cpu_irq_init(NULL);
  90 +}
  91 +
  92 +int __init mips_cpu_intc_init(struct device_node *of_node,
  93 +                             struct device_node *parent)
  94 +{
  95 +       __mips_cpu_irq_init(of_node);
  96         return 0;
  97  }
  98 -#endif /* CONFIG_IRQ_DOMAIN */