target/linux/brcm63xx/patches-3.14/320-irqchip-add-support-for-bcm6345-style-l2-irq-control.patch

   1 From 4d3886359d6f6ac475e143d5f3e3b389542a0510 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 30 Nov 2014 14:53:12 +0100
   4 Subject: [PATCH 17/20] irqchip: add support for bcm6345-style l2 irq
   5  controller
   6
   7 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
   8 ---
   9  .../interrupt-controller/brcm,bcm6345-l2-intc.txt  |   25 ++
  10  drivers/irqchip/Kconfig                            |    4 +
  11  drivers/irqchip/Makefile                           |    1 +
  12  drivers/irqchip/irq-bcm6345-l2.c                   |  320 ++++++++++++++++++++
  13  include/linux/irqchip/irq-bcm6345-l2-intc.h        |   16 +
  14  5 files changed, 366 insertions(+)
  15  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
  16  create mode 100644 drivers/irqchip/irq-bcm6345-l2.c
  17  create mode 100644 include/linux/irqchip/irq-bcm6345-l2-intc.h
  18
  19 --- /dev/null
  20 +++ b/Documentation/devicetree/bindings/interrupt-controller/brcm,bcm6345-l2-intc.txt
  21 @@ -0,0 +1,25 @@
  22 +Broadcom BCM6345 Level 2 interrupt controller
  23 +
  24 +Required properties:
  25 +
  26 +- compatible: should be "brcm,bcm6345-l2-intc"
  27 +- reg: specifies the base physical address and size of the registers;
  28 +  multiple regs may be specified, and must match the amount of parent interrupts
  29 +- interrupt-controller: identifies the node as an interrupt controller
  30 +- #interrupt-cells: specifies the number of cells needed to encode an interrupt
  31 +  source, should be 1
  32 +- interrupt-parent: specifies the phandle to the parent interrupt controller
  33 +  this one is cascaded from
  34 +- interrupts: specifies the interrupt line(s) in the interrupt-parent controller
  35 +  node, valid values depend on the type of parent interrupt controller
  36 +
  37 +Example:
  38 +
  39 +periph_intc: interrupt-controller@f0406800 {
  40 +       compatible = "brcm,bcm6345-l2-intc";
  41 +       interrupt-parent = <&mips_intc>;
  42 +       #interrupt-cells = <1>;
  43 +       reg = <0x10000020 0x10> <0x10000030 0x10>;
  44 +       interrupt-controller;
  45 +       interrupts = <2>, <3>;
  46 +};
  47 --- a/drivers/irqchip/Kconfig
  48 +++ b/drivers/irqchip/Kconfig
  49 @@ -30,6 +30,10 @@ config ARM_VIC_NR
  50           The maximum number of VICs available in the system, for
  51           power management.
  52
  53 +config BCM6345_L2_IRQ
  54 +       bool
  55 +       select IRQ_DOMAIN
  56 +
  57  config DW_APB_ICTL
  58         bool
  59         select IRQ_DOMAIN
  60 --- a/drivers/irqchip/Makefile
  61 +++ b/drivers/irqchip/Makefile
  62 @@ -6,6 +6,7 @@ obj-$(CONFIG_ARCH_MMP)                  += irq-mmp.o
  63  obj-$(CONFIG_ARCH_MVEBU)               += irq-armada-370-xp.o
  64  obj-$(CONFIG_ARCH_MXS)                 += irq-mxs.o
  65  obj-$(CONFIG_ARCH_S3C24XX)             += irq-s3c24xx.o
  66 +obj-$(CONFIG_BCM6345_L2_IRQ)           += irq-bcm6345-l2.o
  67  obj-$(CONFIG_DW_APB_ICTL)              += irq-dw-apb-ictl.o
  68  obj-$(CONFIG_METAG)                    += irq-metag-ext.o
  69  obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)   += irq-metag.o
  70 --- /dev/null
  71 +++ b/drivers/irqchip/irq-bcm6345-l2.c
  72 @@ -0,0 +1,320 @@
  73 +/*
  74 + * This file is subject to the terms and conditions of the GNU General Public
  75 + * License.  See the file "COPYING" in the main directory of this archive
  76 + * for more details.
  77 + *
  78 + * Copyright (C) 2014 Jonas Gorski <jogo@openwrt.org>
  79 + */
  80 +
  81 +#include <linux/ioport.h>
  82 +#include <linux/irq.h>
  83 +#include <linux/irqchip/chained_irq.h>
  84 +#include <linux/irqchip/irq-bcm6345-l2-intc.h>
  85 +#include <linux/kernel.h>
  86 +#include <linux/of.h>
  87 +#include <linux/of_irq.h>
  88 +#include <linux/of_address.h>
  89 +#include <linux/slab.h>
  90 +#include <linux/spinlock.h>
  91 +
  92 +#ifdef CONFIG_BCM63XX
  93 +#include <asm/mach-bcm63xx/bcm63xx_irq.h>
  94 +
  95 +#define VIRQ_BASE      IRQ_INTERNAL_BASE
  96 +#else
  97 +#define VIRQ_BASE      0
  98 +#endif
  99 +
 100 +#include "irqchip.h"
 101 +
 102 +#define MAX_WORDS      4
 103 +#define MAX_PARENT_IRQS        2
 104 +#define IRQS_PER_WORD  32
 105 +
 106 +struct intc_block {
 107 +       int parent_irq;
 108 +       void __iomem *base;
 109 +       void __iomem *en_reg[MAX_WORDS];
 110 +       void __iomem *status_reg[MAX_WORDS];
 111 +       u32 mask_cache[MAX_WORDS];
 112 +};
 113 +
 114 +struct intc_data {
 115 +       struct irq_chip chip;
 116 +       struct intc_block block[MAX_PARENT_IRQS];
 117 +
 118 +       int num_words;
 119 +
 120 +       struct irq_domain *domain;
 121 +       spinlock_t lock;
 122 +};
 123 +
 124 +static void bcm6345_l2_intc_irq_handle(unsigned int irq, struct irq_desc *desc)
 125 +{
 126 +       struct intc_data *data = irq_desc_get_handler_data(desc);
 127 +       struct irq_chip *chip = irq_desc_get_chip(desc);
 128 +       struct intc_block *block;
 129 +       unsigned int idx;
 130 +
 131 +       chained_irq_enter(chip, desc);
 132 +
 133 +       for (idx = 0; idx < MAX_PARENT_IRQS; idx++)
 134 +               if (irq == data->block[idx].parent_irq)
 135 +                       block = &data->block[idx];
 136 +
 137 +       for (idx = 0; idx < data->num_words; idx++) {
 138 +               int base = idx * IRQS_PER_WORD;
 139 +               unsigned long pending;
 140 +               int hw_irq;
 141 +
 142 +               raw_spin_lock(data->lock);
 143 +               pending = __raw_readl(block->en_reg[idx]) &
 144 +                         __raw_readl(block->status_reg[idx]);
 145 +               raw_spin_unlock(data->lock);
 146 +
 147 +               for_each_set_bit(hw_irq, &pending, IRQS_PER_WORD) {
 148 +                       generic_handle_irq(irq_find_mapping(data->domain, base + hw_irq));
 149 +               }
 150 +       }
 151 +
 152 +       chained_irq_exit(chip, desc);
 153 +}
 154 +
 155 +static void bcm6345_l2_intc_irq_mask(struct irq_data *data)
 156 +{
 157 +       unsigned int i, reg, bit;
 158 +       struct intc_data *priv = data->domain->host_data;
 159 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 160 +
 161 +       reg = hwirq / IRQS_PER_WORD;
 162 +       bit = hwirq % IRQS_PER_WORD;
 163 +
 164 +       raw_spin_lock(priv->lock);
 165 +       for (i = 0; i < MAX_PARENT_IRQS; i++) {
 166 +               struct intc_block *block = &priv->block[i];
 167 +               u32 val;
 168 +
 169 +               if (!block->parent_irq)
 170 +                       break;
 171 +
 172 +               val = __raw_readl(block->en_reg[reg]);
 173 +               __raw_writel(val & ~BIT(bit), block->en_reg[reg]);
 174 +       }
 175 +       raw_spin_unlock(priv->lock);
 176 +}
 177 +
 178 +static void bcm6345_l2_intc_irq_unmask(struct irq_data *data)
 179 +{
 180 +       unsigned int i, reg, bit;
 181 +       struct intc_data *priv = data->domain->host_data;
 182 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 183 +
 184 +       reg = hwirq / IRQS_PER_WORD;
 185 +       bit = hwirq % IRQS_PER_WORD;
 186 +
 187 +       raw_spin_lock(priv->lock);
 188 +       for (i = 0; i < MAX_PARENT_IRQS; i++) {
 189 +               struct intc_block *block = &priv->block[i];
 190 +               u32 val;
 191 +
 192 +               if (!block->parent_irq)
 193 +                       break;
 194 +
 195 +               val = __raw_readl(block->en_reg[reg]);
 196 +
 197 +               if (block->mask_cache[reg] & BIT(bit))
 198 +                       val |= BIT(bit);
 199 +               else
 200 +                       val &= ~BIT(bit);
 201 +
 202 +               __raw_writel(val, block->en_reg[reg]);
 203 +
 204 +       }
 205 +       raw_spin_unlock(priv->lock);
 206 +}
 207 +
 208 +#ifdef CONFIG_SMP
 209 +static int bcm6345_l2_intc_set_affinity(struct irq_data *data,
 210 +                                       const struct cpumask *mask,
 211 +                                       bool force)
 212 +{
 213 +       irq_hw_number_t hwirq = irqd_to_hwirq(data);
 214 +       struct intc_data *priv = data->domain->host_data;
 215 +       unsigned int i, reg, bit;
 216 +       int cpu;
 217 +
 218 +       reg = hwirq / IRQS_PER_WORD;
 219 +       bit = hwirq % IRQS_PER_WORD;
 220 +
 221 +       /* we could route to more than one cpu, but performance
 222 +          suffers, so fix it to one.
 223 +        */
 224 +       cpu = cpumask_any_and(mask, cpu_online_mask);
 225 +       if (cpu >= nr_cpu_ids)
 226 +               return -EINVAL;
 227 +
 228 +       if (cpu >= MAX_PARENT_IRQS)
 229 +               return -EINVAL;
 230 +
 231 +       if (!priv->block[cpu].parent_irq)
 232 +               return -EINVAL;
 233 +
 234 +       raw_spin_lock(priv->lock);
 235 +       for (i = 0; i < MAX_PARENT_IRQS; i++) {
 236 +               if (i == cpu)
 237 +                       priv->block[i].mask_cache[reg] |= BIT(bit);
 238 +               else
 239 +                       priv->block[i].mask_cache[reg] &= ~BIT(bit);
 240 +       }
 241 +       raw_spin_unlock(priv->lock);
 242 +
 243 +       return 0;
 244 +}
 245 +#endif
 246 +
 247 +static int bcm6345_l2_map(struct irq_domain *d, unsigned int irq,
 248 +                         irq_hw_number_t hw)
 249 +{
 250 +       struct intc_data *priv = d->host_data;
 251 +
 252 +       irq_set_chip_and_handler(irq, &priv->chip, handle_level_irq);
 253 +
 254 +       return 0;
 255 +}
 256 +
 257 +static const struct irq_domain_ops bcm6345_l2_domain_ops = {
 258 +       .xlate = irq_domain_xlate_onecell,
 259 +       .map = bcm6345_l2_map,
 260 +};
 261 +
 262 +static int __init __bcm6345_l2_intc_init(struct device_node *node,
 263 +                                        int num_blocks, int *irq,
 264 +                                        void __iomem **base, int num_words)
 265 +{
 266 +       struct intc_data *data;
 267 +       unsigned int i, w, status_offset;
 268 +
 269 +       data = kzalloc(sizeof(*data), GFP_KERNEL);
 270 +       if (!data)
 271 +               return -ENOMEM;
 272 +
 273 +       status_offset = num_words * sizeof(u32);
 274 +
 275 +       for (i = 0; i < num_blocks; i++) {
 276 +               struct intc_block *block = &data->block[i];
 277 +
 278 +               block->parent_irq = irq[i];
 279 +               block->base = base[i];
 280 +
 281 +               for (w = 0; w < num_words; w++) {
 282 +                       int word_offset = sizeof(u32) * ((num_words - w) - 1);
 283 +
 284 +                       block->en_reg[w] = base[i] + word_offset;
 285 +                       block->status_reg[w] = base[i] + status_offset;
 286 +                       block->status_reg[w] += word_offset;
 287 +
 288 +                       /* route all interrups to line 0 by default */
 289 +                       if (i == 0)
 290 +                               block->mask_cache[w] = 0xffffffff;
 291 +               }
 292 +
 293 +               irq_set_handler_data(block->parent_irq, data);
 294 +               irq_set_chained_handler(block->parent_irq,
 295 +                                       bcm6345_l2_intc_irq_handle);
 296 +       }
 297 +
 298 +       data->num_words = num_words;
 299 +
 300 +       data->chip.name = "bcm6345-l2-intc";
 301 +       data->chip.irq_mask = bcm6345_l2_intc_irq_mask;
 302 +       data->chip.irq_unmask = bcm6345_l2_intc_irq_unmask;
 303 +
 304 +#ifdef CONFIG_SMP
 305 +       if (num_blocks > 1)
 306 +               data->chip.set_affinity = bcm6345_l2_intc_set_affinity;
 307 +#endif
 308 +
 309 +       data->domain = irq_domain_add_simple(node, IRQS_PER_WORD * num_words,
 310 +                                            VIRQ_BASE, &bcm6345_l2_domain_ops,
 311 +                                            data);
 312 +       if (!data->domain) {
 313 +               kfree(data);
 314 +               return -EINVAL;
 315 +       }
 316 +
 317 +       return 0;
 318 +}
 319 +
 320 +void __init bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
 321 +                                int num_words)
 322 +{
 323 +       __bcm6345_l2_intc_init(NULL, num_blocks, irq, base, num_words);
 324 +}
 325 +
 326 +#ifdef CONFIG_OF
 327 +static int __init bcm6345_l2_intc_of_init(struct device_node *node,
 328 +                                         struct device_node *parent)
 329 +{
 330 +       struct resource res;
 331 +       int num_irqs, ret = -EINVAL;
 332 +       int irqs[MAX_PARENT_IRQS] = { 0 };
 333 +       void __iomem *bases[MAX_PARENT_IRQS] = { NULL };
 334 +       int words = 0;
 335 +       int i;
 336 +
 337 +       num_irqs = of_irq_count(node);
 338 +
 339 +       if (num_irqs < 1 || num_irqs > MAX_PARENT_IRQS)
 340 +               return -EINVAL;
 341 +
 342 +       for (i = 0; i < num_irqs; i++) {
 343 +               resource_size_t size;
 344 +
 345 +               irqs[i] = irq_of_parse_and_map(node, i);
 346 +               if (!irqs[i])
 347 +                       goto out_unmap;
 348 +
 349 +               if (of_address_to_resource(node, i, &res)) {
 350 +                       goto out_unmap;
 351 +               }
 352 +
 353 +               size = resource_size(&res);
 354 +               switch (size) {
 355 +                       case 8:
 356 +                       case 16:
 357 +                       case 32:
 358 +                               size = size / 8;
 359 +                               break;
 360 +                       default:
 361 +                               goto out_unmap;
 362 +               }
 363 +
 364 +               if (words && words != size) {
 365 +                       ret = -EINVAL;
 366 +                       goto out_unmap;
 367 +               }
 368 +               words = size;
 369 +
 370 +               bases[i] = of_iomap(node, i);
 371 +               if (!bases[i]) {
 372 +                       ret = -ENOMEM;
 373 +                       goto out_unmap;
 374 +               }
 375 +       }
 376 +
 377 +       ret = __bcm6345_l2_intc_init(node, num_irqs, irqs, bases, words);
 378 +       if (!ret)
 379 +               return 0;
 380 +
 381 +out_unmap:
 382 +       for (i = 0; i < num_irqs; i++) {
 383 +               iounmap(bases[i]);
 384 +               irq_dispose_mapping(irqs[i]);
 385 +       }
 386 +
 387 +       return ret;
 388 +}
 389 +
 390 +IRQCHIP_DECLARE(bcm6345_l2_intc, "brcm,bcm6345-l2-intc",
 391 +               bcm6345_l2_intc_of_init);
 392 +#endif
 393 --- /dev/null
 394 +++ b/include/linux/irqchip/irq-bcm6345-l2-intc.h
 395 @@ -0,0 +1,16 @@
 396 +/*
 397 + * This file is subject to the terms and conditions of the GNU General Public
 398 + * License.  See the file "COPYING" in the main directory of this archive
 399 + * for more details.
 400 + *
 401 + * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
 402 + * Copyright (C) 2008 Nicolas Schichan <nschichan@freebox.fr>
 403 + */
 404 +
 405 +#ifndef __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
 406 +#define __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H
 407 +
 408 +void bcm6345_l2_intc_init(int num_blocks, int *irq, void __iomem **base,
 409 +                         int num_words);
 410 +
 411 +#endif /* __INCLUDE_LINUX_IRQCHIP_IRQ_BCM6345_L2_INTC_H */