target/linux/brcm63xx/patches-3.14/321-MIPS-BCM63XX-append-irq-line-number-to-irq_-stat-mas.patch

   1 From 1003fb4a5ee9fcff518f20eefdee1a9bf500af7e Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Thu, 25 Apr 2013 00:24:06 +0200
   4 Subject: [PATCH 32/53] MIPS: BCM63XX: append irq line number to
   5  irq_{stat,mask}*
   6
   7 The SMP capable irq controllers have two interupt output pins which are
   8 controlled through separate registers, so make the variables arrays.
   9
  10 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  11 ---
  12  arch/mips/bcm63xx/irq.c                           | 51 ++++++++++++-----------
  13  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 16 +++----
  14  2 files changed, 34 insertions(+), 33 deletions(-)
  15
  16 --- a/arch/mips/bcm63xx/irq.c
  17 +++ b/arch/mips/bcm63xx/irq.c
  18 @@ -19,7 +19,8 @@
  19  #include <bcm63xx_io.h>
  20  #include <bcm63xx_irq.h>
  21
  22 -static u32 irq_stat_addr, irq_mask_addr;
  23 +static u32 irq_stat_addr[2];
  24 +static u32 irq_mask_addr[2];
  25  static void (*dispatch_internal)(void);
  26  static int is_ext_irq_cascaded;
  27  static unsigned int ext_irq_count;
  28 @@ -64,8 +65,8 @@ void __dispatch_internal_##width(void)
  29         for (src = 0, tgt = (width / 32); src < (width / 32); src++) {  \
  30                 u32 val;                                                \
  31                                                                         \
  32 -               val = bcm_readl(irq_stat_addr + src * sizeof(u32));     \
  33 -               val &= bcm_readl(irq_mask_addr + src * sizeof(u32));    \
  34 +               val = bcm_readl(irq_stat_addr[0] + src * sizeof(u32));  \
  35 +               val &= bcm_readl(irq_mask_addr[0] + src * sizeof(u32)); \
  36                 pending[--tgt] = val;                                   \
  37                                                                         \
  38                 if (val)                                                \
  39 @@ -92,9 +93,9 @@ static void __internal_irq_mask_##width(
  40         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  41         unsigned bit = irq & 0x1f;                                      \
  42                                                                         \
  43 -       val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
  44 +       val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  45         val &= ~(1 << bit);                                             \
  46 -       bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
  47 +       bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  48  }                                                                      \
  49                                                                         \
  50  static void __internal_irq_unmask_##width(unsigned int irq)            \
  51 @@ -103,9 +104,9 @@ static void __internal_irq_unmask_##widt
  52         unsigned reg = (irq / 32) ^ (width/32 - 1);                     \
  53         unsigned bit = irq & 0x1f;                                      \
  54                                                                         \
  55 -       val = bcm_readl(irq_mask_addr + reg * sizeof(u32));             \
  56 +       val = bcm_readl(irq_mask_addr[0] + reg * sizeof(u32));          \
  57         val |= (1 << bit);                                              \
  58 -       bcm_writel(val, irq_mask_addr + reg * sizeof(u32));             \
  59 +       bcm_writel(val, irq_mask_addr[0] + reg * sizeof(u32));          \
  60  }
  61
  62  BUILD_IPIC_INTERNAL(32);
  63 @@ -339,20 +340,20 @@ static void bcm63xx_init_irq(void)
  64  {
  65         int irq_bits;
  66
  67 -       irq_stat_addr = bcm63xx_regset_address(RSET_PERF);
  68 -       irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
  69 +       irq_stat_addr[0] = bcm63xx_regset_address(RSET_PERF);
  70 +       irq_mask_addr[0] = bcm63xx_regset_address(RSET_PERF);
  71
  72         switch (bcm63xx_get_cpu_id()) {
  73         case BCM3368_CPU_ID:
  74 -               irq_stat_addr += PERF_IRQSTAT_3368_REG;
  75 -               irq_mask_addr += PERF_IRQMASK_3368_REG;
  76 +               irq_stat_addr[0] += PERF_IRQSTAT_3368_REG;
  77 +               irq_mask_addr[0] += PERF_IRQMASK_3368_REG;
  78                 irq_bits = 32;
  79                 ext_irq_count = 4;
  80                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_3368;
  81                 break;
  82         case BCM6328_CPU_ID:
  83 -               irq_stat_addr += PERF_IRQSTAT_6328_REG;
  84 -               irq_mask_addr += PERF_IRQMASK_6328_REG;
  85 +               irq_stat_addr[0] += PERF_IRQSTAT_6328_REG(0);
  86 +               irq_mask_addr[0] += PERF_IRQMASK_6328_REG(0);
  87                 irq_bits = 64;
  88                 ext_irq_count = 4;
  89                 is_ext_irq_cascaded = 1;
  90 @@ -361,29 +362,29 @@ static void bcm63xx_init_irq(void)
  91                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
  92                 break;
  93         case BCM6338_CPU_ID:
  94 -               irq_stat_addr += PERF_IRQSTAT_6338_REG;
  95 -               irq_mask_addr += PERF_IRQMASK_6338_REG;
  96 +               irq_stat_addr[0] += PERF_IRQSTAT_6338_REG;
  97 +               irq_mask_addr[0] += PERF_IRQMASK_6338_REG;
  98                 irq_bits = 32;
  99                 ext_irq_count = 4;
 100                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6338;
 101                 break;
 102         case BCM6345_CPU_ID:
 103 -               irq_stat_addr += PERF_IRQSTAT_6345_REG;
 104 -               irq_mask_addr += PERF_IRQMASK_6345_REG;
 105 +               irq_stat_addr[0] += PERF_IRQSTAT_6345_REG;
 106 +               irq_mask_addr[0] += PERF_IRQMASK_6345_REG;
 107                 irq_bits = 32;
 108                 ext_irq_count = 4;
 109                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6345;
 110                 break;
 111         case BCM6348_CPU_ID:
 112 -               irq_stat_addr += PERF_IRQSTAT_6348_REG;
 113 -               irq_mask_addr += PERF_IRQMASK_6348_REG;
 114 +               irq_stat_addr[0] += PERF_IRQSTAT_6348_REG;
 115 +               irq_mask_addr[0] += PERF_IRQMASK_6348_REG;
 116                 irq_bits = 32;
 117                 ext_irq_count = 4;
 118                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6348;
 119                 break;
 120         case BCM6358_CPU_ID:
 121 -               irq_stat_addr += PERF_IRQSTAT_6358_REG;
 122 -               irq_mask_addr += PERF_IRQMASK_6358_REG;
 123 +               irq_stat_addr[0] += PERF_IRQSTAT_6358_REG(0);
 124 +               irq_mask_addr[0] += PERF_IRQMASK_6358_REG(0);
 125                 irq_bits = 32;
 126                 ext_irq_count = 4;
 127                 is_ext_irq_cascaded = 1;
 128 @@ -392,8 +393,8 @@ static void bcm63xx_init_irq(void)
 129                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
 130                 break;
 131         case BCM6362_CPU_ID:
 132 -               irq_stat_addr += PERF_IRQSTAT_6362_REG;
 133 -               irq_mask_addr += PERF_IRQMASK_6362_REG;
 134 +               irq_stat_addr[0] += PERF_IRQSTAT_6362_REG(0);
 135 +               irq_mask_addr[0] += PERF_IRQMASK_6362_REG(0);
 136                 irq_bits = 64;
 137                 ext_irq_count = 4;
 138                 is_ext_irq_cascaded = 1;
 139 @@ -402,8 +403,8 @@ static void bcm63xx_init_irq(void)
 140                 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
 141                 break;
 142         case BCM6368_CPU_ID:
 143 -               irq_stat_addr += PERF_IRQSTAT_6368_REG;
 144 -               irq_mask_addr += PERF_IRQMASK_6368_REG;
 145 +               irq_stat_addr[0] += PERF_IRQSTAT_6368_REG(0);
 146 +               irq_mask_addr[0] += PERF_IRQMASK_6368_REG(0);
 147                 irq_bits = 64;
 148                 ext_irq_count = 6;
 149                 is_ext_irq_cascaded = 1;
 150 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 151 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
 152 @@ -215,23 +215,23 @@
 153
 154  /* Interrupt Mask register */
 155  #define PERF_IRQMASK_3368_REG          0xc
 156 -#define PERF_IRQMASK_6328_REG          0x20
 157 +#define PERF_IRQMASK_6328_REG(x)       (0x20 + (x) * 0x10)
 158  #define PERF_IRQMASK_6338_REG          0xc
 159  #define PERF_IRQMASK_6345_REG          0xc
 160  #define PERF_IRQMASK_6348_REG          0xc
 161 -#define PERF_IRQMASK_6358_REG          0xc
 162 -#define PERF_IRQMASK_6362_REG          0x20
 163 -#define PERF_IRQMASK_6368_REG          0x20
 164 +#define PERF_IRQMASK_6358_REG(x)       (0xc + (x) * 0x2c)
 165 +#define PERF_IRQMASK_6362_REG(x)       (0x20 + (x) * 0x10)
 166 +#define PERF_IRQMASK_6368_REG(x)       (0x20 + (x) * 0x10)
 167
 168  /* Interrupt Status register */
 169  #define PERF_IRQSTAT_3368_REG          0x10
 170 -#define PERF_IRQSTAT_6328_REG          0x28
 171 +#define PERF_IRQSTAT_6328_REG(x)       (0x28 + (x) * 0x10)
 172  #define PERF_IRQSTAT_6338_REG          0x10
 173  #define PERF_IRQSTAT_6345_REG          0x10
 174  #define PERF_IRQSTAT_6348_REG          0x10
 175 -#define PERF_IRQSTAT_6358_REG          0x10
 176 -#define PERF_IRQSTAT_6362_REG          0x28
 177 -#define PERF_IRQSTAT_6368_REG          0x28
 178 +#define PERF_IRQSTAT_6358_REG(x)       (0x10 + (x) * 0x2c)
 179 +#define PERF_IRQSTAT_6362_REG(x)       (0x28 + (x) * 0x10)
 180 +#define PERF_IRQSTAT_6368_REG(x)       (0x28 + (x) * 0x10)
 181
 182  /* External Interrupt Configuration register */
 183  #define PERF_EXTIRQ_CFG_REG_3368       0x14