brcm63xx: update development kernel to linux 3.14
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.14 / 411-MIPS-BCM63XX-Register-SPI-flash-if-present.patch
1 From d135d94b3d1fe599d13e7198d5f502912d694c13 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Sun, 3 Jul 2011 15:00:38 +0200
4 Subject: [PATCH 29/60] MIPS: BCM63XX: Register SPI flash if present
5
6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
7 ---
8 arch/mips/bcm63xx/dev-flash.c | 33 +++++++++++++++++++-
9 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 2 +
10 2 files changed, 33 insertions(+), 2 deletions(-)
11
12 --- a/arch/mips/bcm63xx/dev-flash.c
13 +++ b/arch/mips/bcm63xx/dev-flash.c
14 @@ -16,9 +16,12 @@
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/partitions.h>
17 #include <linux/mtd/physmap.h>
18 +#include <linux/spi/spi.h>
19 +#include <linux/spi/flash.h>
20
21 #include <bcm63xx_cpu.h>
22 #include <bcm63xx_dev_flash.h>
23 +#include <bcm63xx_dev_hsspi.h>
24 #include <bcm63xx_regs.h>
25 #include <bcm63xx_io.h>
26
27 @@ -57,6 +60,21 @@ static struct platform_device mtd_dev =
28 },
29 };
30
31 +static struct flash_platform_data bcm63xx_flash_data = {
32 + .part_probe_types = bcm63xx_part_types,
33 +};
34 +
35 +static struct spi_board_info bcm63xx_spi_flash_info[] = {
36 + {
37 + .bus_num = 0,
38 + .chip_select = 0,
39 + .mode = 0,
40 + .max_speed_hz = 781000,
41 + .modalias = "m25p80",
42 + .platform_data = &bcm63xx_flash_data,
43 + },
44 +};
45 +
46 static int __init bcm63xx_detect_flash_type(void)
47 {
48 u32 val;
49 @@ -64,9 +82,15 @@ static int __init bcm63xx_detect_flash_t
50 switch (bcm63xx_get_cpu_id()) {
51 case BCM6318_CPU_ID:
52 /* only support serial flash */
53 + bcm63xx_spi_flash_info[0].max_speed_hz = 62500000;
54 return BCM63XX_FLASH_TYPE_SERIAL;
55 case BCM6328_CPU_ID:
56 val = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
57 + if (val & STRAPBUS_6328_HSSPI_CLK_FAST)
58 + bcm63xx_spi_flash_info[0].max_speed_hz = 33333334;
59 + else
60 + bcm63xx_spi_flash_info[0].max_speed_hz = 16666667;
61 +
62 if (val & STRAPBUS_6328_BOOT_SEL_SERIAL)
63 return BCM63XX_FLASH_TYPE_SERIAL;
64 else
65 @@ -85,12 +109,20 @@ static int __init bcm63xx_detect_flash_t
66 return BCM63XX_FLASH_TYPE_SERIAL;
67 case BCM6362_CPU_ID:
68 val = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
69 + if (val & STRAPBUS_6362_HSSPI_CLK_FAST)
70 + bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
71 + else
72 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
73 +
74 if (val & STRAPBUS_6362_BOOT_SEL_SERIAL)
75 return BCM63XX_FLASH_TYPE_SERIAL;
76 else
77 return BCM63XX_FLASH_TYPE_NAND;
78 case BCM6368_CPU_ID:
79 val = bcm_gpio_readl(GPIO_STRAPBUS_REG);
80 + if (val & STRAPBUS_6368_SPI_CLK_FAST)
81 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
82 +
83 switch (val & STRAPBUS_6368_BOOT_SEL_MASK) {
84 case STRAPBUS_6368_BOOT_SEL_NAND:
85 return BCM63XX_FLASH_TYPE_NAND;
86 @@ -101,6 +133,11 @@ static int __init bcm63xx_detect_flash_t
87 }
88 case BCM63268_CPU_ID:
89 val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
90 + if (val & STRAPBUS_63268_HSSPI_CLK_FAST)
91 + bcm63xx_spi_flash_info[0].max_speed_hz = 50000000;
92 + else
93 + bcm63xx_spi_flash_info[0].max_speed_hz = 20000000;
94 +
95 if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
96 return BCM63XX_FLASH_TYPE_SERIAL;
97 else
98 @@ -167,8 +204,15 @@ int __init bcm63xx_flash_register(void)
99
100 return platform_device_register(&mtd_dev);
101 case BCM63XX_FLASH_TYPE_SERIAL:
102 - pr_warn("unsupported serial flash detected\n");
103 - return -ENODEV;
104 + if (BCMCPU_IS_6318() || BCMCPU_IS_6328() || BCMCPU_IS_6362() ||
105 + BCMCPU_IS_63268())
106 + bcm63xx_spi_flash_info[0].bus_num = 1;
107 +
108 + if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
109 + bcm63xx_flash_data.max_transfer_len = SPI_6358_MSG_DATA_SIZE;
110 +
111 + return spi_register_board_info(bcm63xx_spi_flash_info,
112 + ARRAY_SIZE(bcm63xx_spi_flash_info));
113 case BCM63XX_FLASH_TYPE_NAND:
114 pr_warn("unsupported NAND flash detected\n");
115 return -ENODEV;
116 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
117 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
118 @@ -707,6 +707,7 @@
119 #define GPIO_STRAPBUS_REG 0x40
120 #define STRAPBUS_6358_BOOT_SEL_PARALLEL (1 << 1)
121 #define STRAPBUS_6358_BOOT_SEL_SERIAL (0 << 1)
122 +#define STRAPBUS_6368_SPI_CLK_FAST (1 << 6)
123 #define STRAPBUS_6368_BOOT_SEL_MASK 0x3
124 #define STRAPBUS_6368_BOOT_SEL_NAND 0
125 #define STRAPBUS_6368_BOOT_SEL_SERIAL 1
126 @@ -1577,6 +1578,7 @@
127 #define IDDQ_CTRL_63268_USBH (1 << 4)
128
129 #define MISC_STRAPBUS_6328_REG 0x240
130 +#define STRAPBUS_6328_HSSPI_CLK_FAST (1 << 4)
131 #define STRAPBUS_6328_FCVO_SHIFT 7
132 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
133 #define STRAPBUS_6328_BOOT_SEL_SERIAL (1 << 28)