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[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.3 / 312-MIPS-BCM63XX-add-basic-BCM6328-CPU-support.patch
1 From e7fd2a00f5d6c5e50976ed931c26fdbfbbacf835 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Tue, 14 Jun 2011 21:14:39 +0200
4 Subject: [PATCH 40/79] MIPS: BCM63XX: add basic BCM6328 CPU support
5
6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
7 ---
8 arch/mips/bcm63xx/Kconfig | 4 +
9 arch/mips/bcm63xx/boards/board_bcm963xx.c | 11 ++-
10 arch/mips/bcm63xx/cpu.c | 43 +++++++++
11 arch/mips/bcm63xx/dev-spi.c | 2 +-
12 arch/mips/bcm63xx/irq.c | 21 +++++
13 arch/mips/bcm63xx/prom.c | 4 +-
14 arch/mips/bcm63xx/setup.c | 13 ++-
15 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 101 +++++++++++++++++++++
16 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
17 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 44 +++++++++
18 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
19 11 files changed, 238 insertions(+), 8 deletions(-)
20
21 --- a/arch/mips/bcm63xx/Kconfig
22 +++ b/arch/mips/bcm63xx/Kconfig
23 @@ -1,6 +1,10 @@
24 menu "CPU support"
25 depends on BCM63XX
26
27 +config BCM63XX_CPU_6328
28 + bool "support 6328 CPU"
29 + select HW_HAS_PCI
30 +
31 config BCM63XX_CPU_6338
32 bool "support 6338 CPU"
33 select HW_HAS_PCI
34 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
35 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
36 @@ -760,9 +760,14 @@ void __init board_prom_init(void)
37 char cfe_version[32];
38 u32 val;
39
40 - /* read base address of boot chip select (0) */
41 - val = bcm_mpi_readl(MPI_CSBASE_REG(0));
42 - val &= MPI_CSBASE_BASE_MASK;
43 + /* read base address of boot chip select (0)
44 + * 6328 does not have MPI but boots from a fixed address */
45 + if (BCMCPU_IS_6328())
46 + val = 0x18000000;
47 + else {
48 + val = bcm_mpi_readl(MPI_CSBASE_REG(0));
49 + val &= MPI_CSBASE_BASE_MASK;
50 + }
51 boot_addr = (u8 *)KSEG1ADDR(val);
52
53 /* dump cfe version */
54 --- a/arch/mips/bcm63xx/cpu.c
55 +++ b/arch/mips/bcm63xx/cpu.c
56 @@ -29,6 +29,14 @@ static u16 bcm63xx_cpu_rev;
57 static unsigned int bcm63xx_cpu_freq;
58 static unsigned int bcm63xx_memory_size;
59
60 +static const unsigned long bcm6328_regs_base[] = {
61 + __GEN_CPU_REGS_TABLE(6328)
62 +};
63 +
64 +static const int bcm6328_irqs[] = {
65 + __GEN_CPU_IRQ_TABLE(6328)
66 +};
67 +
68 static const unsigned long bcm6338_regs_base[] = {
69 __GEN_CPU_REGS_TABLE(6338)
70 };
71 @@ -99,6 +107,33 @@ unsigned int bcm63xx_get_memory_size(voi
72 static unsigned int detect_cpu_clock(void)
73 {
74 switch (bcm63xx_get_cpu_id()) {
75 + case BCM6328_CPU_ID:
76 + {
77 + unsigned int tmp, mips_pll_fcvo;
78 +
79 + tmp = bcm_misc_readl(MISC_STRAPBUS_6328_REG);
80 + mips_pll_fcvo = (tmp & STRAPBUS_6328_FCVO_MASK)
81 + >> STRAPBUS_6328_FCVO_SHIFT;
82 +
83 + switch (mips_pll_fcvo) {
84 + case 0x12:
85 + case 0x14:
86 + case 0x19:
87 + return 160000000;
88 + case 0x1c:
89 + return 192000000;
90 + case 0x13:
91 + case 0x15:
92 + return 200000000;
93 + case 0x1a:
94 + return 384000000;
95 + case 0x16:
96 + return 400000000;
97 + default:
98 + return 320000000;
99 + }
100 +
101 + }
102 case BCM6338_CPU_ID:
103 /* BCM6338 has a fixed 240 Mhz frequency */
104 return 240000000;
105 @@ -170,6 +205,9 @@ static unsigned int detect_memory_size(v
106 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
107 u32 val;
108
109 + if (BCMCPU_IS_6328())
110 + return bcm_ddr_readl(DDR_CSEND_REG) << 24;
111 +
112 if (BCMCPU_IS_6345()) {
113 val = bcm_sdram_readl(SDRAM_MBASE_REG);
114 return (val * 8 * 1024 * 1024);
115 @@ -237,6 +275,11 @@ void __init bcm63xx_cpu_init(void)
116 u16 chip_id = bcm_readw(BCM_6368_PERF_BASE);
117
118 switch (chip_id) {
119 + case BCM6328_CPU_ID:
120 + expected_cpu_id = BCM6328_CPU_ID;
121 + bcm63xx_regs_base = bcm6328_regs_base;
122 + bcm63xx_irqs = bcm6328_irqs;
123 + break;
124 case BCM6368_CPU_ID:
125 expected_cpu_id = BCM6368_CPU_ID;
126 bcm63xx_regs_base = bcm6368_regs_base;
127 --- a/arch/mips/bcm63xx/dev-spi.c
128 +++ b/arch/mips/bcm63xx/dev-spi.c
129 @@ -87,7 +87,7 @@ int __init bcm63xx_spi_register(void)
130 {
131 struct clk *periph_clk;
132
133 - if (BCMCPU_IS_6345())
134 + if (BCMCPU_IS_6328() || BCMCPU_IS_6345())
135 return -ENODEV;
136
137 periph_clk = clk_get(NULL, "periph");
138 --- a/arch/mips/bcm63xx/irq.c
139 +++ b/arch/mips/bcm63xx/irq.c
140 @@ -27,6 +27,17 @@ static void __internal_irq_unmask_32(uns
141 static void __internal_irq_unmask_64(unsigned int irq) __maybe_unused;
142
143 #ifndef BCMCPU_RUNTIME_DETECT
144 +#ifdef CONFIG_BCM63XX_CPU_6328
145 +#define irq_stat_reg PERF_IRQSTAT_6328_REG
146 +#define irq_mask_reg PERF_IRQMASK_6328_REG
147 +#define irq_bits 64
148 +#define is_ext_irq_cascaded 1
149 +#define ext_irq_start (BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE)
150 +#define ext_irq_end (BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE)
151 +#define ext_irq_count 4
152 +#define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6328
153 +#define ext_irq_cfg_reg2 0
154 +#endif
155 #ifdef CONFIG_BCM63XX_CPU_6338
156 #define irq_stat_reg PERF_IRQSTAT_6338_REG
157 #define irq_mask_reg PERF_IRQMASK_6338_REG
158 @@ -118,6 +129,16 @@ static void bcm63xx_init_irq(void)
159 irq_mask_addr = bcm63xx_regset_address(RSET_PERF);
160
161 switch (bcm63xx_get_cpu_id()) {
162 + case BCM6328_CPU_ID:
163 + irq_stat_addr += PERF_IRQSTAT_6328_REG;
164 + irq_mask_addr += PERF_IRQMASK_6328_REG;
165 + irq_bits = 64;
166 + ext_irq_count = 4;
167 + is_ext_irq_cascaded = 1;
168 + ext_irq_start = BCM_6328_EXT_IRQ0 - IRQ_INTERNAL_BASE;
169 + ext_irq_end = BCM_6328_EXT_IRQ3 - IRQ_INTERNAL_BASE;
170 + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6328;
171 + break;
172 case BCM6338_CPU_ID:
173 irq_stat_addr += PERF_IRQSTAT_6338_REG;
174 irq_mask_addr += PERF_IRQMASK_6338_REG;
175 --- a/arch/mips/bcm63xx/prom.c
176 +++ b/arch/mips/bcm63xx/prom.c
177 @@ -26,7 +26,9 @@ void __init prom_init(void)
178 bcm_wdt_writel(WDT_STOP_2, WDT_CTL_REG);
179
180 /* disable all hardware blocks clock for now */
181 - if (BCMCPU_IS_6338())
182 + if (BCMCPU_IS_6328())
183 + mask = CKCTL_6328_ALL_SAFE_EN;
184 + else if (BCMCPU_IS_6338())
185 mask = CKCTL_6338_ALL_SAFE_EN;
186 else if (BCMCPU_IS_6345())
187 mask = CKCTL_6345_ALL_SAFE_EN;
188 --- a/arch/mips/bcm63xx/setup.c
189 +++ b/arch/mips/bcm63xx/setup.c
190 @@ -68,6 +68,9 @@ void bcm63xx_machine_reboot(void)
191
192 /* mask and clear all external irq */
193 switch (bcm63xx_get_cpu_id()) {
194 + case BCM6328_CPU_ID:
195 + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6328;
196 + break;
197 case BCM6338_CPU_ID:
198 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6338;
199 break;
200 @@ -101,9 +104,13 @@ void bcm63xx_machine_reboot(void)
201 bcm6348_a1_reboot();
202
203 printk(KERN_INFO "triggering watchdog soft-reset...\n");
204 - reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
205 - reg |= SYS_PLL_SOFT_RESET;
206 - bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
207 + if (BCMCPU_IS_6328()) {
208 + bcm_wdt_writel(1, WDT_SOFTRESET_REG);
209 + } else {
210 + reg = bcm_perf_readl(PERF_SYS_PLL_CTL_REG);
211 + reg |= SYS_PLL_SOFT_RESET;
212 + bcm_perf_writel(reg, PERF_SYS_PLL_CTL_REG);
213 + }
214 while (1)
215 ;
216 }
217 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
218 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
219 @@ -9,6 +9,7 @@
220 * compile time if only one CPU support is enabled (idea stolen from
221 * arm mach-types)
222 */
223 +#define BCM6328_CPU_ID 0x6328
224 #define BCM6338_CPU_ID 0x6338
225 #define BCM6345_CPU_ID 0x6345
226 #define BCM6348_CPU_ID 0x6348
227 @@ -20,6 +21,19 @@ u16 __bcm63xx_get_cpu_id(void);
228 u16 bcm63xx_get_cpu_rev(void);
229 unsigned int bcm63xx_get_cpu_freq(void);
230
231 +#ifdef CONFIG_BCM63XX_CPU_6328
232 +# ifdef bcm63xx_get_cpu_id
233 +# undef bcm63xx_get_cpu_id
234 +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
235 +# define BCMCPU_RUNTIME_DETECT
236 +# else
237 +# define bcm63xx_get_cpu_id() BCM6328_CPU_ID
238 +# endif
239 +# define BCMCPU_IS_6328() (bcm63xx_get_cpu_id() == BCM6328_CPU_ID)
240 +#else
241 +# define BCMCPU_IS_6328() (0)
242 +#endif
243 +
244 #ifdef CONFIG_BCM63XX_CPU_6338
245 # ifdef bcm63xx_get_cpu_id
246 # undef bcm63xx_get_cpu_id
247 @@ -157,6 +171,49 @@ enum bcm63xx_regs_set {
248 #define RSET_TRNG_SIZE 20
249
250 /*
251 + * 6328 register sets base address
252 + */
253 +#define BCM_6328_DSL_LMEM_BASE (0xdeadbeef)
254 +#define BCM_6328_PERF_BASE (0xb0000000)
255 +#define BCM_6328_TIMER_BASE (0xb0000040)
256 +#define BCM_6328_WDT_BASE (0xb000005c)
257 +#define BCM_6328_UART0_BASE (0xb0000100)
258 +#define BCM_6328_UART1_BASE (0xb0000120)
259 +#define BCM_6328_GPIO_BASE (0xb0000080)
260 +#define BCM_6328_SPI_BASE (0xdeadbeef)
261 +#define BCM_6328_UDC0_BASE (0xdeadbeef)
262 +#define BCM_6328_USBDMA_BASE (0xdeadbeef)
263 +#define BCM_6328_OHCI0_BASE (0xdeadbeef)
264 +#define BCM_6328_OHCI_PRIV_BASE (0xdeadbeef)
265 +#define BCM_6328_USBH_PRIV_BASE (0xdeadbeef)
266 +#define BCM_6328_MPI_BASE (0xdeadbeef)
267 +#define BCM_6328_PCMCIA_BASE (0xdeadbeef)
268 +#define BCM_6328_SDRAM_REGS_BASE (0xdeadbeef)
269 +#define BCM_6328_DSL_BASE (0xb0001900)
270 +#define BCM_6328_UBUS_BASE (0xdeadbeef)
271 +#define BCM_6328_ENET0_BASE (0xdeadbeef)
272 +#define BCM_6328_ENET1_BASE (0xdeadbeef)
273 +#define BCM_6328_ENETDMA_BASE (0xb000d800)
274 +#define BCM_6328_ENETDMAC_BASE (0xb000da00)
275 +#define BCM_6328_ENETDMAS_BASE (0xb000dc00)
276 +#define BCM_6328_ENETSW_BASE (0xb0e00000)
277 +#define BCM_6328_EHCI0_BASE (0x10002500)
278 +#define BCM_6328_SDRAM_BASE (0xdeadbeef)
279 +#define BCM_6328_MEMC_BASE (0xdeadbeef)
280 +#define BCM_6328_DDR_BASE (0xb0003000)
281 +#define BCM_6328_M2M_BASE (0xdeadbeef)
282 +#define BCM_6328_ATM_BASE (0xdeadbeef)
283 +#define BCM_6328_XTM_BASE (0xdeadbeef)
284 +#define BCM_6328_XTMDMA_BASE (0xb000b800)
285 +#define BCM_6328_XTMDMAC_BASE (0xdeadbeef)
286 +#define BCM_6328_XTMDMAS_BASE (0xdeadbeef)
287 +#define BCM_6328_PCM_BASE (0xb000a800)
288 +#define BCM_6328_PCMDMA_BASE (0xdeadbeef)
289 +#define BCM_6328_PCMDMAC_BASE (0xdeadbeef)
290 +#define BCM_6328_PCMDMAS_BASE (0xdeadbeef)
291 +#define BCM_6328_TRNG_BASE (0xdeadbeef)
292 +#define BCM_6328_MISC_BASE (0xb0001800)
293 +/*
294 * 6338 register sets base address
295 */
296 #define BCM_6338_DSL_LMEM_BASE (0xfff00000)
297 @@ -466,6 +523,9 @@ static inline unsigned long bcm63xx_regs
298 #ifdef BCMCPU_RUNTIME_DETECT
299 return bcm63xx_regs_base[set];
300 #else
301 +#ifdef CONFIG_BCM63XX_CPU_6328
302 + __GEN_RSET(6328)
303 +#endif
304 #ifdef CONFIG_BCM63XX_CPU_6338
305 __GEN_RSET(6338)
306 #endif
307 @@ -520,6 +580,47 @@ enum bcm63xx_irq {
308 };
309
310 /*
311 + * 6328 irqs
312 + */
313 +#define BCM_6328_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
314 +
315 +#define BCM_6328_TIMER_IRQ (IRQ_INTERNAL_BASE + 31)
316 +#define BCM_6328_SPI_IRQ 0
317 +#define BCM_6328_UART0_IRQ (IRQ_INTERNAL_BASE + 28)
318 +#define BCM_6328_UART1_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
319 +#define BCM_6328_DSL_IRQ (IRQ_INTERNAL_BASE + 4)
320 +#define BCM_6328_UDC0_IRQ 0
321 +#define BCM_6328_ENET0_IRQ 0
322 +#define BCM_6328_ENET1_IRQ 0
323 +#define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
324 +#define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
325 +#define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
326 +#define BCM_6328_PCMCIA_IRQ 0
327 +#define BCM_6328_ENET0_RXDMA_IRQ 0
328 +#define BCM_6328_ENET0_TXDMA_IRQ 0
329 +#define BCM_6328_ENET1_RXDMA_IRQ 0
330 +#define BCM_6328_ENET1_TXDMA_IRQ 0
331 +#define BCM_6328_PCI_IRQ (IRQ_INTERNAL_BASE + 23)
332 +#define BCM_6328_ATM_IRQ 0
333 +#define BCM_6328_ENETSW_RXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 0)
334 +#define BCM_6328_ENETSW_RXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 1)
335 +#define BCM_6328_ENETSW_RXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 2)
336 +#define BCM_6328_ENETSW_RXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 3)
337 +#define BCM_6328_ENETSW_TXDMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 4)
338 +#define BCM_6328_ENETSW_TXDMA1_IRQ (BCM_6328_HIGH_IRQ_BASE + 5)
339 +#define BCM_6328_ENETSW_TXDMA2_IRQ (BCM_6328_HIGH_IRQ_BASE + 6)
340 +#define BCM_6328_ENETSW_TXDMA3_IRQ (BCM_6328_HIGH_IRQ_BASE + 7)
341 +#define BCM_6328_XTM_IRQ (BCM_6328_HIGH_IRQ_BASE + 31)
342 +#define BCM_6328_XTM_DMA0_IRQ (BCM_6328_HIGH_IRQ_BASE + 11)
343 +
344 +#define BCM_6328_PCM_DMA0_IRQ (IRQ_INTERNAL_BASE + 2)
345 +#define BCM_6328_PCM_DMA1_IRQ (IRQ_INTERNAL_BASE + 3)
346 +#define BCM_6328_EXT_IRQ0 (IRQ_INTERNAL_BASE + 24)
347 +#define BCM_6328_EXT_IRQ1 (IRQ_INTERNAL_BASE + 25)
348 +#define BCM_6328_EXT_IRQ2 (IRQ_INTERNAL_BASE + 26)
349 +#define BCM_6328_EXT_IRQ3 (IRQ_INTERNAL_BASE + 27)
350 +
351 +/*
352 * 6338 irqs
353 */
354 #define BCM_6338_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
355 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
356 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
357 @@ -9,6 +9,8 @@ int __init bcm63xx_gpio_init(void);
358 static inline unsigned long bcm63xx_gpio_count(void)
359 {
360 switch (bcm63xx_get_cpu_id()) {
361 + case BCM6328_CPU_ID:
362 + return 32;
363 case BCM6358_CPU_ID:
364 return 40;
365 case BCM6338_CPU_ID:
366 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
367 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
368 @@ -15,6 +15,30 @@
369 /* Clock Control register */
370 #define PERF_CKCTL_REG 0x4
371
372 +#define CKCTL_6328_PHYMIPS_EN (1 << 0)
373 +#define CKCTL_6328_ADSL_QPROC_EN (1 << 1)
374 +#define CKCTL_6328_ADSL_AFE_EN (1 << 2)
375 +#define CKCTL_6328_ADSL_EN (1 << 3)
376 +#define CKCTL_6328_MIPS_EN (1 << 4)
377 +#define CKCTL_6328_SAR_EN (1 << 5)
378 +#define CKCTL_6328_PCM_EN (1 << 6)
379 +#define CKCTL_6328_USBD_EN (1 << 7)
380 +#define CKCTL_6328_USBH_EN (1 << 8)
381 +#define CKCTL_6328_HSSPI_EN (1 << 9)
382 +#define CKCTL_6328_PCIE_EN (1 << 10)
383 +#define CKCTL_6328_ROBOSW_EN (1 << 11)
384 +
385 +#define CKCTL_6328_ALL_SAFE_EN (CKCTL_6328_PHYMIPS_EN | \
386 + CKCTL_6328_ADSL_QPROC_EN | \
387 + CKCTL_6328_ADSL_AFE_EN | \
388 + CKCTL_6328_ADSL_EN | \
389 + CKCTL_6328_SAR_EN | \
390 + CKCTL_6328_PCM_EN | \
391 + CKCTL_6328_USBD_EN | \
392 + CKCTL_6328_USBH_EN | \
393 + CKCTL_6328_ROBOSW_EN | \
394 + CKCTL_6328_PCIE_EN)
395 +
396 #define CKCTL_6338_ADSLPHY_EN (1 << 0)
397 #define CKCTL_6338_MPI_EN (1 << 1)
398 #define CKCTL_6338_DRAM_EN (1 << 2)
399 @@ -119,6 +143,7 @@
400 #define SYS_PLL_SOFT_RESET 0x1
401
402 /* Interrupt Mask register */
403 +#define PERF_IRQMASK_6328_REG 0x20
404 #define PERF_IRQMASK_6338_REG 0xc
405 #define PERF_IRQMASK_6345_REG 0xc
406 #define PERF_IRQMASK_6348_REG 0xc
407 @@ -126,6 +151,7 @@
408 #define PERF_IRQMASK_6368_REG 0x20
409
410 /* Interrupt Status register */
411 +#define PERF_IRQSTAT_6328_REG 0x28
412 #define PERF_IRQSTAT_6338_REG 0x10
413 #define PERF_IRQSTAT_6345_REG 0x10
414 #define PERF_IRQSTAT_6348_REG 0x10
415 @@ -133,6 +159,7 @@
416 #define PERF_IRQSTAT_6368_REG 0x28
417
418 /* External Interrupt Configuration register */
419 +#define PERF_EXTIRQ_CFG_REG_6328 0x18
420 #define PERF_EXTIRQ_CFG_REG_6338 0x14
421 #define PERF_EXTIRQ_CFG_REG_6345 0x14
422 #define PERF_EXTIRQ_CFG_REG_6348 0x14
423 @@ -163,8 +190,21 @@
424
425 /* Soft Reset register */
426 #define PERF_SOFTRESET_REG 0x28
427 +#define PERF_SOFTRESET_6328_REG 0x10
428 #define PERF_SOFTRESET_6368_REG 0x10
429
430 +#define SOFTRESET_6328_SPI_MASK (1 << 0)
431 +#define SOFTRESET_6328_EPHY_MASK (1 << 1)
432 +#define SOFTRESET_6328_SAR_MASK (1 << 2)
433 +#define SOFTRESET_6328_ENETSW_MASK (1 << 3)
434 +#define SOFTRESET_6328_USBS_MASK (1 << 4)
435 +#define SOFTRESET_6328_USBH_MASK (1 << 5)
436 +#define SOFTRESET_6328_PCM_MASK (1 << 6)
437 +#define SOFTRESET_6328_PCIE_CORE_MASK (1 << 7)
438 +#define SOFTRESET_6328_PCIE_MASK (1 << 8)
439 +#define SOFTRESET_6328_PCIE_EXT_MASK (1 << 9)
440 +#define SOFTRESET_6328_PCIE_HARD_MASK (1 << 10)
441 +
442 #define SOFTRESET_6338_SPI_MASK (1 << 0)
443 #define SOFTRESET_6338_ENET_MASK (1 << 2)
444 #define SOFTRESET_6338_USBH_MASK (1 << 3)
445 @@ -308,6 +348,8 @@
446 /* Watchdog reset length register */
447 #define WDT_RSTLEN_REG 0x8
448
449 +/* Watchdog soft reset register (BCM6328 only) */
450 +#define WDT_SOFTRESET_REG 0xc
451
452 /*************************************************************************
453 * _REG relative to RSET_UARTx
454 @@ -934,6 +976,8 @@
455 * _REG relative to RSET_DDR
456 *************************************************************************/
457
458 +#define DDR_CSEND_REG 0x8
459 +
460 #define DDR_DMIPSPLLCFG_REG 0x18
461 #define DMIPSPLLCFG_M1_SHIFT 0
462 #define DMIPSPLLCFG_M1_MASK (0xff << DMIPSPLLCFG_M1_SHIFT)
463 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
464 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
465 @@ -18,6 +18,7 @@ static inline int is_bcm63xx_internal_re
466 if (offset >= 0xfff00000)
467 return 1;
468 break;
469 + case BCM6328_CPU_ID:
470 case BCM6368_CPU_ID:
471 if (offset >= 0xb0000000 && offset < 0xb1000000)
472 return 1;
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