[brcm63xx] add preliminary support for 3.6 kernel
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.6 / 309-MIPS-BCM63XX-add-HSSPI-register-definitions.patch
1 From 70f970222bc1096689ae1bffeb9ed09a7c4bed07 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Sat, 12 Nov 2011 12:19:55 +0100
4 Subject: [PATCH 28/60] MIPS: BCM63XX: add HSSPI register definitions
5
6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
7 ---
8 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 18 ++++++++
9 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 47 +++++++++++++++++++++
10 2 files changed, 65 insertions(+), 0 deletions(-)
11
12 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
13 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
14 @@ -116,6 +116,7 @@ enum bcm63xx_regs_set {
15 RSET_UART1,
16 RSET_GPIO,
17 RSET_SPI,
18 + RSET_HSSPI,
19 RSET_UDC0,
20 RSET_OHCI0,
21 RSET_OHCI_PRIV,
22 @@ -159,6 +160,7 @@ enum bcm63xx_regs_set {
23 #define RSET_ENETDMA_SIZE 2048
24 #define RSET_ENETSW_SIZE 65536
25 #define RSET_UART_SIZE 24
26 +#define RSET_HSSPI_SIZE 1536
27 #define RSET_UDC_SIZE 256
28 #define RSET_OHCI_SIZE 256
29 #define RSET_EHCI_SIZE 256
30 @@ -182,6 +184,7 @@ enum bcm63xx_regs_set {
31 #define BCM_6328_UART1_BASE (0xb0000120)
32 #define BCM_6328_GPIO_BASE (0xb0000080)
33 #define BCM_6328_SPI_BASE (0xdeadbeef)
34 +#define BCM_6328_HSSPI_BASE (0xb0001000)
35 #define BCM_6328_UDC0_BASE (0xdeadbeef)
36 #define BCM_6328_USBDMA_BASE (0xdeadbeef)
37 #define BCM_6328_OHCI0_BASE (0xdeadbeef)
38 @@ -227,6 +230,7 @@ enum bcm63xx_regs_set {
39 #define BCM_6338_UART1_BASE (0xdeadbeef)
40 #define BCM_6338_GPIO_BASE (0xfffe0400)
41 #define BCM_6338_SPI_BASE (0xfffe0c00)
42 +#define BCM_6338_HSSPI_BASE (0xdeadbeef)
43 #define BCM_6338_UDC0_BASE (0xdeadbeef)
44 #define BCM_6338_USBDMA_BASE (0xfffe2400)
45 #define BCM_6338_OHCI0_BASE (0xdeadbeef)
46 @@ -273,6 +277,7 @@ enum bcm63xx_regs_set {
47 #define BCM_6345_UART1_BASE (0xdeadbeef)
48 #define BCM_6345_GPIO_BASE (0xfffe0400)
49 #define BCM_6345_SPI_BASE (0xdeadbeef)
50 +#define BCM_6345_HSSPI_BASE (0xdeadbeef)
51 #define BCM_6345_UDC0_BASE (0xdeadbeef)
52 #define BCM_6345_USBDMA_BASE (0xfffe2800)
53 #define BCM_6345_ENET0_BASE (0xfffe1800)
54 @@ -318,6 +323,7 @@ enum bcm63xx_regs_set {
55 #define BCM_6348_UART1_BASE (0xdeadbeef)
56 #define BCM_6348_GPIO_BASE (0xfffe0400)
57 #define BCM_6348_SPI_BASE (0xfffe0c00)
58 +#define BCM_6348_HSSPI_BASE (0xdeadbeef)
59 #define BCM_6348_UDC0_BASE (0xfffe1000)
60 #define BCM_6348_OHCI0_BASE (0xfffe1b00)
61 #define BCM_6348_OHCI_PRIV_BASE (0xfffe1c00)
62 @@ -361,6 +367,7 @@ enum bcm63xx_regs_set {
63 #define BCM_6358_UART1_BASE (0xfffe0120)
64 #define BCM_6358_GPIO_BASE (0xfffe0080)
65 #define BCM_6358_SPI_BASE (0xfffe0800)
66 +#define BCM_6358_HSSPI_BASE (0xdeadbeef)
67 #define BCM_6358_UDC0_BASE (0xfffe0800)
68 #define BCM_6358_OHCI0_BASE (0xfffe1400)
69 #define BCM_6358_OHCI_PRIV_BASE (0xdeadbeef)
70 @@ -405,6 +412,7 @@ enum bcm63xx_regs_set {
71 #define BCM_6368_UART1_BASE (0xb0000120)
72 #define BCM_6368_GPIO_BASE (0xb0000080)
73 #define BCM_6368_SPI_BASE (0xb0000800)
74 +#define BCM_6368_HSSPI_BASE (0xdeadbeef)
75 #define BCM_6368_UDC0_BASE (0xdeadbeef)
76 #define BCM_6368_OHCI0_BASE (0xb0001600)
77 #define BCM_6368_OHCI_PRIV_BASE (0xdeadbeef)
78 @@ -454,6 +462,7 @@ extern const unsigned long *bcm63xx_regs
79 __GEN_RSET_BASE(__cpu, UART1) \
80 __GEN_RSET_BASE(__cpu, GPIO) \
81 __GEN_RSET_BASE(__cpu, SPI) \
82 + __GEN_RSET_BASE(__cpu, HSSPI) \
83 __GEN_RSET_BASE(__cpu, UDC0) \
84 __GEN_RSET_BASE(__cpu, OHCI0) \
85 __GEN_RSET_BASE(__cpu, OHCI_PRIV) \
86 @@ -495,6 +504,7 @@ extern const unsigned long *bcm63xx_regs
87 [RSET_UART1] = BCM_## __cpu ##_UART1_BASE, \
88 [RSET_GPIO] = BCM_## __cpu ##_GPIO_BASE, \
89 [RSET_SPI] = BCM_## __cpu ##_SPI_BASE, \
90 + [RSET_HSSPI] = BCM_## __cpu ##_HSSPI_BASE, \
91 [RSET_UDC0] = BCM_## __cpu ##_UDC0_BASE, \
92 [RSET_OHCI0] = BCM_## __cpu ##_OHCI0_BASE, \
93 [RSET_OHCI_PRIV] = BCM_## __cpu ##_OHCI_PRIV_BASE, \
94 @@ -567,6 +577,7 @@ enum bcm63xx_irq {
95 IRQ_ENET0,
96 IRQ_ENET1,
97 IRQ_ENET_PHY,
98 + IRQ_HSSPI,
99 IRQ_OHCI0,
100 IRQ_EHCI0,
101 IRQ_ENET0_RXDMA,
102 @@ -602,6 +613,7 @@ enum bcm63xx_irq {
103 #define BCM_6328_ENET0_IRQ 0
104 #define BCM_6328_ENET1_IRQ 0
105 #define BCM_6328_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
106 +#define BCM_6328_HSSPI_IRQ (IRQ_INTERNAL_BASE + 29)
107 #define BCM_6328_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
108 #define BCM_6328_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
109 #define BCM_6328_PCMCIA_IRQ 0
110 @@ -640,6 +652,7 @@ enum bcm63xx_irq {
111 #define BCM_6338_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
112 #define BCM_6338_ENET1_IRQ 0
113 #define BCM_6338_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
114 +#define BCM_6338_HSSPI_IRQ 0
115 #define BCM_6338_OHCI0_IRQ 0
116 #define BCM_6338_EHCI0_IRQ 0
117 #define BCM_6338_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
118 @@ -671,6 +684,7 @@ enum bcm63xx_irq {
119 #define BCM_6345_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
120 #define BCM_6345_ENET1_IRQ 0
121 #define BCM_6345_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 12)
122 +#define BCM_6345_HSSPI_IRQ 0
123 #define BCM_6345_OHCI0_IRQ 0
124 #define BCM_6345_EHCI0_IRQ 0
125 #define BCM_6345_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 13 + 1)
126 @@ -702,6 +716,7 @@ enum bcm63xx_irq {
127 #define BCM_6348_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
128 #define BCM_6348_ENET1_IRQ (IRQ_INTERNAL_BASE + 7)
129 #define BCM_6348_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
130 +#define BCM_6348_HSSPI_IRQ 0
131 #define BCM_6348_OHCI0_IRQ (IRQ_INTERNAL_BASE + 12)
132 #define BCM_6348_EHCI0_IRQ 0
133 #define BCM_6348_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 20)
134 @@ -733,6 +748,7 @@ enum bcm63xx_irq {
135 #define BCM_6358_ENET0_IRQ (IRQ_INTERNAL_BASE + 8)
136 #define BCM_6358_ENET1_IRQ (IRQ_INTERNAL_BASE + 6)
137 #define BCM_6358_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 9)
138 +#define BCM_6358_HSSPI_IRQ 0
139 #define BCM_6358_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
140 #define BCM_6358_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
141 #define BCM_6358_ENET0_RXDMA_IRQ (IRQ_INTERNAL_BASE + 15)
142 @@ -773,6 +789,7 @@ enum bcm63xx_irq {
143 #define BCM_6368_ENET0_IRQ 0
144 #define BCM_6368_ENET1_IRQ 0
145 #define BCM_6368_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 15)
146 +#define BCM_6368_HSSPI_IRQ 0
147 #define BCM_6368_OHCI0_IRQ (IRQ_INTERNAL_BASE + 5)
148 #define BCM_6368_EHCI0_IRQ (IRQ_INTERNAL_BASE + 7)
149 #define BCM_6368_PCMCIA_IRQ 0
150 @@ -813,6 +830,7 @@ extern const int *bcm63xx_irqs;
151 [IRQ_ENET0] = BCM_## __cpu ##_ENET0_IRQ, \
152 [IRQ_ENET1] = BCM_## __cpu ##_ENET1_IRQ, \
153 [IRQ_ENET_PHY] = BCM_## __cpu ##_ENET_PHY_IRQ, \
154 + [IRQ_HSSPI] = BCM_## __cpu ##_HSSPI_IRQ, \
155 [IRQ_OHCI0] = BCM_## __cpu ##_OHCI0_IRQ, \
156 [IRQ_EHCI0] = BCM_## __cpu ##_EHCI0_IRQ, \
157 [IRQ_ENET0_RXDMA] = BCM_## __cpu ##_ENET0_RXDMA_IRQ, \
158 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
159 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
160 @@ -1231,4 +1231,51 @@
161
162 #define PCIE_DEVICE_OFFSET 0x8000
163
164 +/*************************************************************************
165 + * _REG relative to RSET_HSSPI
166 + *************************************************************************/
167 +
168 +#define HSSPI_GLOBAL_CTRL_REG 0x0
169 +#define GLOBAL_CTRL_CLK_POLARITY (1 << 17)
170 +#define GLOBAL_CTRL_CLK_GATE_SSOFF (1 << 16)
171 +
172 +#define HSSPI_GLOBAL_EXT_TRIGGER_REG 0x4
173 +
174 +#define HSSPI_INT_STATUS_REG 0x8
175 +#define HSSPI_INT_STATUS_MASKED_REG 0xc
176 +#define HSSPI_INT_MASK_REG 0x10
177 +
178 +#define HSSPI_PING0_CMD_DONE (1 << 0)
179 +
180 +#define HSSPI_INT_CLEAR_ALL 0xff001f1f
181 +
182 +#define HSSPI_PINGPONG_COMMAND_REG(x) (0x80 + (x) * 0x40)
183 +#define PINGPONG_CMD_COMMAND_MASK 0xf
184 +#define PINGPONG_COMMAND_NOOP 0
185 +#define PINGPONG_COMMAND_START_NOW 1
186 +#define PINGPONG_COMMAND_START_TRIGGER 2
187 +#define PINGPONG_COMMAND_HALT 3
188 +#define PINGPONG_COMMAND_FLUSH 4
189 +#define PINGPONG_CMD_PROFILE_SHIFT 8
190 +#define PINGPONG_CMD_SS_SHIFT 12
191 +
192 +#define HSSPI_PINGPONG_STATUS_REG(x) (0x84 + (x) * 0x40)
193 +
194 +#define HSSPI_PROFILE_CLK_CTRL_REG(x) (0x100 + (x) * 0x20)
195 +#define CLK_CTRL_ACCUM_RST_ON_LOOP (1 << 15)
196 +
197 +#define HSSPI_PROFILE_SIGNAL_CTRL_REG(x) (0x104 + (x) * 0x20)
198 +#define SIGNAL_CTRL_LATCH_RISING (1 << 12)
199 +#define SIGNAL_CTRL_LAUNCH_RISING (1 << 13)
200 +#define SIGNAL_CTRL_ASYNC_INPUT_PATH (1 << 16)
201 +
202 +#define HSSPI_PROFILE_MODE_CTRL_REG(x) (0x108 + (x) * 0x20)
203 +#define MODE_CTRL_MULTIDATA_RD_STRT_SHIFT 8
204 +#define MODE_CTRL_MULTIDATA_WR_STRT_SHIFT 12
205 +#define MODE_CTRL_MULTIDATA_RD_SIZE_SHIFT 16
206 +#define MODE_CTRL_MULTIDATA_WR_SIZE_SHIFT 18
207 +#define MODE_CTRL_PREPENDBYTE_CNT_SHIFT 24
208 +
209 +#define HSSPI_FIFO_REG(x) (0x200 + (x) * 0x200)
210 +
211 #endif /* BCM63XX_REGS_H_ */