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[brcm63xx] make default version 3.7.6
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.6 / 312-MIPS-BCM63XX-add-basic-BCM6362-support.patch
1 From 27ebbb819b1f92d52309276b29b7a56e362e5c4d Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jonas.gorski@gmail.com>
3 Date: Mon, 21 Nov 2011 00:48:52 +0100
4 Subject: [PATCH 54/84] MIPS: BCM63XX: add basic BCM6362 support
5
6 Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
7 ---
8 arch/mips/bcm63xx/Kconfig | 4 +
9 arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
10 arch/mips/bcm63xx/cpu.c | 52 ++++++++-
11 arch/mips/bcm63xx/irq.c | 19 +++
12 arch/mips/bcm63xx/prom.c | 2 +
13 arch/mips/bcm63xx/setup.c | 3 +
14 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 139 +++++++++++++++++++++
15 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
16 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 59 +++++++++
17 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
18 10 files changed, 281 insertions(+), 2 deletions(-)
19
20 --- a/arch/mips/bcm63xx/Kconfig
21 +++ b/arch/mips/bcm63xx/Kconfig
22 @@ -25,6 +25,10 @@ config BCM63XX_CPU_6358
23 bool "support 6358 CPU"
24 select HW_HAS_PCI
25
26 +config BCM63XX_CPU_6362
27 + bool "support 6362 CPU"
28 + select HW_HAS_PCI
29 +
30 config BCM63XX_CPU_6368
31 bool "support 6368 CPU"
32 select HW_HAS_PCI
33 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
34 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
35 @@ -809,7 +809,7 @@ void __init board_prom_init(void)
36 /* read base address of boot chip select (0)
37 * 6328 does not have MPI but boots from a fixed address
38 */
39 - if (BCMCPU_IS_6328())
40 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
41 val = 0x18000000;
42 else {
43 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
44 --- a/arch/mips/bcm63xx/cpu.c
45 +++ b/arch/mips/bcm63xx/cpu.c
46 @@ -71,6 +71,15 @@ static const int bcm6358_irqs[] = {
47
48 };
49
50 +static const unsigned long bcm6362_regs_base[] = {
51 + __GEN_CPU_REGS_TABLE(6362)
52 +};
53 +
54 +static const int bcm6362_irqs[] = {
55 + __GEN_CPU_IRQ_TABLE(6362)
56 +
57 +};
58 +
59 static const unsigned long bcm6368_regs_base[] = {
60 __GEN_CPU_REGS_TABLE(6368)
61 };
62 @@ -169,6 +178,42 @@ static unsigned int detect_cpu_clock(voi
63 return (16 * 1000000 * n1 * n2) / m1;
64 }
65
66 + case BCM6362_CPU_ID:
67 + {
68 + unsigned int tmp, mips_pll_fcvo;
69 +
70 + tmp = bcm_misc_readl(MISC_STRAPBUS_6362_REG);
71 + mips_pll_fcvo = (tmp & STRAPBUS_6362_FCVO_MASK)
72 + >> STRAPBUS_6362_FCVO_SHIFT;
73 + switch (mips_pll_fcvo) {
74 + case 0x03:
75 + case 0x0b:
76 + case 0x13:
77 + case 0x1b:
78 + return 240000000;
79 + case 0x04:
80 + case 0x0c:
81 + case 0x14:
82 + case 0x1c:
83 + return 160000000;
84 + case 0x05:
85 + case 0x0e:
86 + case 0x16:
87 + case 0x1e:
88 + case 0x1f:
89 + return 400000000;
90 + case 0x06:
91 + return 440000000;
92 + case 0x07:
93 + case 0x17:
94 + return 384000000;
95 + case 0x15:
96 + case 0x1d:
97 + return 200000000;
98 + default:
99 + return 320000000;
100 + }
101 + }
102 case BCM6368_CPU_ID:
103 {
104 unsigned int tmp, p1, p2, ndiv, m1;
105 @@ -205,7 +250,7 @@ static unsigned int detect_memory_size(v
106 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
107 u32 val;
108
109 - if (BCMCPU_IS_6328())
110 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
111 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
112
113 if (BCMCPU_IS_6345()) {
114 @@ -280,6 +325,11 @@ void __init bcm63xx_cpu_init(void)
115 bcm63xx_regs_base = bcm6328_regs_base;
116 bcm63xx_irqs = bcm6328_irqs;
117 break;
118 + case BCM6362_CPU_ID:
119 + expected_cpu_id = BCM6362_CPU_ID;
120 + bcm63xx_regs_base = bcm6362_regs_base;
121 + bcm63xx_irqs = bcm6362_irqs;
122 + break;
123 case BCM6368_CPU_ID:
124 expected_cpu_id = BCM6368_CPU_ID;
125 bcm63xx_regs_base = bcm6368_regs_base;
126 --- a/arch/mips/bcm63xx/irq.c
127 +++ b/arch/mips/bcm63xx/irq.c
128 @@ -82,6 +82,14 @@ static void __internal_irq_unmask_64(uns
129 #define ext_irq_cfg_reg1 PERF_EXTIRQ_CFG_REG_6358
130 #define ext_irq_cfg_reg2 0
131 #endif
132 +#ifdef CONFIG_BCM63XX_CPU_6362
133 +#define irq_stat_reg PERF_IRQSTAT_6362_REG
134 +#define irq_mask_reg PERF_IRQMASK_6362_REG
135 +#define irq_bits 64
136 +#define is_ext_irq_cascaded 1
137 +#define ext_irq_start (BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE)
138 +#define ext_irq_end (BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE)
139 +#endif
140 #ifdef CONFIG_BCM63XX_CPU_6368
141 #define irq_stat_reg PERF_IRQSTAT_6368_REG
142 #define irq_mask_reg PERF_IRQMASK_6368_REG
143 @@ -170,6 +178,16 @@ static void bcm63xx_init_irq(void)
144 ext_irq_end = BCM_6358_EXT_IRQ3 - IRQ_INTERNAL_BASE;
145 ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6358;
146 break;
147 + case BCM6362_CPU_ID:
148 + irq_stat_addr += PERF_IRQSTAT_6362_REG;
149 + irq_mask_addr += PERF_IRQMASK_6362_REG;
150 + irq_bits = 64;
151 + ext_irq_count = 4;
152 + is_ext_irq_cascaded = 1;
153 + ext_irq_start = BCM_6362_EXT_IRQ0 - IRQ_INTERNAL_BASE;
154 + ext_irq_end = BCM_6362_EXT_IRQ3 - IRQ_INTERNAL_BASE;
155 + ext_irq_cfg_reg1 = PERF_EXTIRQ_CFG_REG_6362;
156 + break;
157 case BCM6368_CPU_ID:
158 irq_stat_addr += PERF_IRQSTAT_6368_REG;
159 irq_mask_addr += PERF_IRQMASK_6368_REG;
160 @@ -457,6 +475,7 @@ static int bcm63xx_external_irq_set_type
161 case BCM6338_CPU_ID:
162 case BCM6345_CPU_ID:
163 case BCM6358_CPU_ID:
164 + case BCM6362_CPU_ID:
165 case BCM6368_CPU_ID:
166 if (levelsense)
167 reg |= EXTIRQ_CFG_LEVELSENSE(irq);
168 --- a/arch/mips/bcm63xx/prom.c
169 +++ b/arch/mips/bcm63xx/prom.c
170 @@ -36,6 +36,8 @@ void __init prom_init(void)
171 mask = CKCTL_6348_ALL_SAFE_EN;
172 else if (BCMCPU_IS_6358())
173 mask = CKCTL_6358_ALL_SAFE_EN;
174 + else if (BCMCPU_IS_6362())
175 + mask = CKCTL_6362_ALL_SAFE_EN;
176 else if (BCMCPU_IS_6368())
177 mask = CKCTL_6368_ALL_SAFE_EN;
178 else
179 --- a/arch/mips/bcm63xx/setup.c
180 +++ b/arch/mips/bcm63xx/setup.c
181 @@ -83,6 +83,9 @@ void bcm63xx_machine_reboot(void)
182 case BCM6358_CPU_ID:
183 perf_regs[0] = PERF_EXTIRQ_CFG_REG_6358;
184 break;
185 + case BCM6362_CPU_ID:
186 + perf_regs[0] = PERF_EXTIRQ_CFG_REG_6362;
187 + break;
188 }
189
190 for (i = 0; i < 2; i++) {
191 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
192 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
193 @@ -14,6 +14,7 @@
194 #define BCM6345_CPU_ID 0x6345
195 #define BCM6348_CPU_ID 0x6348
196 #define BCM6358_CPU_ID 0x6358
197 +#define BCM6362_CPU_ID 0x6362
198 #define BCM6368_CPU_ID 0x6368
199
200 void __init bcm63xx_cpu_init(void);
201 @@ -86,6 +87,20 @@ unsigned int bcm63xx_get_cpu_freq(void);
202 # define BCMCPU_IS_6358() (0)
203 #endif
204
205 +#ifdef CONFIG_BCM63XX_CPU_6362
206 +# ifdef bcm63xx_get_cpu_id
207 +# undef bcm63xx_get_cpu_id
208 +# define bcm63xx_get_cpu_id() __bcm63xx_get_cpu_id()
209 +# define BCMCPU_RUNTIME_DETECT
210 +# else
211 +# define bcm63xx_get_cpu_id() BCM6362_CPU_ID
212 +# endif
213 +# define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
214 +#else
215 +# define BCMCPU_IS_6362() (0)
216 +#endif
217 +
218 +
219 #ifdef CONFIG_BCM63XX_CPU_6368
220 # ifdef bcm63xx_get_cpu_id
221 # undef bcm63xx_get_cpu_id
222 @@ -402,6 +417,62 @@ enum bcm63xx_regs_set {
223
224
225 /*
226 + * 6362 register sets base address
227 + */
228 +#define BCM_6362_DSL_LMEM_BASE (0xdeadbeef)
229 +#define BCM_6362_PERF_BASE (0xb0000000)
230 +#define BCM_6362_TIMER_BASE (0xb0000040)
231 +#define BCM_6362_WDT_BASE (0xb000005c)
232 +#define BCM_6362_UART0_BASE (0xb0000100)
233 +#define BCM_6362_UART1_BASE (0xb0000120)
234 +#define BCM_6362_GPIO_BASE (0xb0000080)
235 +#define BCM_6362_SPI_BASE (0xb0000800)
236 +#define BCM_6362_HSSPI_BASE (0xb0001000)
237 +#define BCM_6362_UDC0_BASE (0xdeadbeef)
238 +#define BCM_6362_USBDMA_BASE (0xb000c000)
239 +#define BCM_6362_OHCI0_BASE (0xb0002600)
240 +#define BCM_6362_OHCI_PRIV_BASE (0xdeadbeef)
241 +#define BCM_6362_USBH_PRIV_BASE (0xb0002700)
242 +#define BCM_6362_USBD_BASE (0xb0002400)
243 +#define BCM_6362_MPI_BASE (0xdeadbeef)
244 +#define BCM_6362_PCMCIA_BASE (0xdeadbeef)
245 +#define BCM_6362_PCIE_BASE (0xb0e40000)
246 +#define BCM_6362_SDRAM_REGS_BASE (0xdeadbeef)
247 +#define BCM_6362_DSL_BASE (0xdeadbeef)
248 +#define BCM_6362_UBUS_BASE (0xdeadbeef)
249 +#define BCM_6362_ENET0_BASE (0xdeadbeef)
250 +#define BCM_6362_ENET1_BASE (0xdeadbeef)
251 +#define BCM_6362_ENETDMA_BASE (0xb000d800)
252 +#define BCM_6362_ENETDMAC_BASE (0xb000da00)
253 +#define BCM_6362_ENETDMAS_BASE (0xb000dc00)
254 +#define BCM_6362_ENETSW_BASE (0xb0e00000)
255 +#define BCM_6362_EHCI0_BASE (0xb0002500)
256 +#define BCM_6362_SDRAM_BASE (0xdeadbeef)
257 +#define BCM_6362_MEMC_BASE (0xdeadbeef)
258 +#define BCM_6362_DDR_BASE (0xb0003000)
259 +#define BCM_6362_M2M_BASE (0xdeadbeef)
260 +#define BCM_6362_ATM_BASE (0xdeadbeef)
261 +#define BCM_6362_XTM_BASE (0xb0007800)
262 +#define BCM_6362_XTMDMA_BASE (0xb000b800)
263 +#define BCM_6362_XTMDMAC_BASE (0xdeadbeef)
264 +#define BCM_6362_XTMDMAS_BASE (0xdeadbeef)
265 +#define BCM_6362_PCM_BASE (0xb000a800)
266 +#define BCM_6362_PCMDMA_BASE (0xdeadbeef)
267 +#define BCM_6362_PCMDMAC_BASE (0xdeadbeef)
268 +#define BCM_6362_PCMDMAS_BASE (0xdeadbeef)
269 +#define BCM_6362_RNG_BASE (0xdeadbeef)
270 +#define BCM_6362_MISC_BASE (0xb0001800)
271 +
272 +#define BCM_6362_NAND_REG_BASE (0xb0000200)
273 +#define BCM_6362_NAND_CACHE_BASE (0xb0000600)
274 +#define BCM_6362_LED_BASE (0xb0001900)
275 +#define BCM_6362_IPSEC_BASE (0xb0002800)
276 +#define BCM_6362_IPSEC_DMA_BASE (0xb000d000)
277 +#define BCM_6362_WLAN_CHIPCOMMON_BASE (0xb0004000)
278 +#define BCM_6362_WLAN_D11_BASE (0xb0005000)
279 +#define BCM_6362_WLAN_SHIM_BASE (0xb0007000)
280 +
281 +/*
282 * 6368 register sets base address
283 */
284 #define BCM_6368_DSL_LMEM_BASE (0xdeadbeef)
285 @@ -557,6 +628,9 @@ static inline unsigned long bcm63xx_regs
286 #ifdef CONFIG_BCM63XX_CPU_6358
287 __GEN_RSET(6358)
288 #endif
289 +#ifdef CONFIG_BCM63XX_CPU_6362
290 + __GEN_RSET(6362)
291 +#endif
292 #ifdef CONFIG_BCM63XX_CPU_6368
293 __GEN_RSET(6368)
294 #endif
295 @@ -777,6 +851,71 @@ enum bcm63xx_irq {
296 #define BCM_6358_EXT_IRQ3 (IRQ_INTERNAL_BASE + 28)
297
298 /*
299 + * 6362 irqs
300 + */
301 +#define BCM_6362_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
302 +
303 +#define BCM_6362_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
304 +#define BCM_6362_SPI_IRQ (IRQ_INTERNAL_BASE + 2)
305 +#define BCM_6362_UART0_IRQ (IRQ_INTERNAL_BASE + 3)
306 +#define BCM_6362_UART1_IRQ (IRQ_INTERNAL_BASE + 4)
307 +#define BCM_6362_DSL_IRQ (IRQ_INTERNAL_BASE + 28)
308 +#define BCM_6362_UDC0_IRQ 0
309 +#define BCM_6362_ENET0_IRQ 0
310 +#define BCM_6362_ENET1_IRQ 0
311 +#define BCM_6362_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 14)
312 +#define BCM_6362_HSSPI_IRQ (IRQ_INTERNAL_BASE + 5)
313 +#define BCM_6362_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
314 +#define BCM_6362_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
315 +#define BCM_6362_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
316 +#define BCM_6362_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 20)
317 +#define BCM_6362_USBD_TXDMA0_IRQ (IRQ_INTERNAL_BASE + 21)
318 +#define BCM_6362_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 22)
319 +#define BCM_6362_USBD_TXDMA1_IRQ (IRQ_INTERNAL_BASE + 23)
320 +#define BCM_6362_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 24)
321 +#define BCM_6362_USBD_TXDMA2_IRQ (IRQ_INTERNAL_BASE + 25)
322 +#define BCM_6362_PCMCIA_IRQ 0
323 +#define BCM_6362_ENET0_RXDMA_IRQ 0
324 +#define BCM_6362_ENET0_TXDMA_IRQ 0
325 +#define BCM_6362_ENET1_RXDMA_IRQ 0
326 +#define BCM_6362_ENET1_TXDMA_IRQ 0
327 +#define BCM_6362_PCI_IRQ (IRQ_INTERNAL_BASE + 30)
328 +#define BCM_6362_ATM_IRQ 0
329 +#define BCM_6362_ENETSW_RXDMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 0)
330 +#define BCM_6362_ENETSW_RXDMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 1)
331 +#define BCM_6362_ENETSW_RXDMA2_IRQ (BCM_6362_HIGH_IRQ_BASE + 2)
332 +#define BCM_6362_ENETSW_RXDMA3_IRQ (BCM_6362_HIGH_IRQ_BASE + 3)
333 +#define BCM_6362_ENETSW_TXDMA0_IRQ 0
334 +#define BCM_6362_ENETSW_TXDMA1_IRQ 0
335 +#define BCM_6362_ENETSW_TXDMA2_IRQ 0
336 +#define BCM_6362_ENETSW_TXDMA3_IRQ 0
337 +#define BCM_6362_XTM_IRQ 0
338 +#define BCM_6362_XTM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 12)
339 +
340 +#define BCM_6362_RING_OSC_IRQ (IRQ_INTERNAL_BASE + 1)
341 +#define BCM_6362_WLAN_GPIO_IRQ (IRQ_INTERNAL_BASE + 6)
342 +#define BCM_6362_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
343 +#define BCM_6362_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
344 +#define BCM_6362_NAND_IRQ (IRQ_INTERNAL_BASE + 12)
345 +#define BCM_6362_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
346 +#define BCM_6362_DG_IRQ (IRQ_INTERNAL_BASE + 15)
347 +#define BCM_6362_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
348 +#define BCM_6362_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
349 +#define BCM_6362_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
350 +#define BCM_6362_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
351 +#define BCM_6362_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
352 +#define BCM_6362_IPSEC_DMA1_IRQ (IRQ_INTERNAL_BASE + 27)
353 +#define BCM_6362_FAP0_IRQ (IRQ_INTERNAL_BASE + 29)
354 +#define BCM_6362_PCM_DMA0_IRQ (BCM_6362_HIGH_IRQ_BASE + 4)
355 +#define BCM_6362_PCM_DMA1_IRQ (BCM_6362_HIGH_IRQ_BASE + 5)
356 +#define BCM_6362_DECT0_IRQ (BCM_6362_HIGH_IRQ_BASE + 6)
357 +#define BCM_6362_DECT1_IRQ (BCM_6362_HIGH_IRQ_BASE + 7)
358 +#define BCM_6362_EXT_IRQ0 (BCM_6362_HIGH_IRQ_BASE + 8)
359 +#define BCM_6362_EXT_IRQ1 (BCM_6362_HIGH_IRQ_BASE + 9)
360 +#define BCM_6362_EXT_IRQ2 (BCM_6362_HIGH_IRQ_BASE + 10)
361 +#define BCM_6362_EXT_IRQ3 (BCM_6362_HIGH_IRQ_BASE + 11)
362 +
363 +/*
364 * 6368 irqs
365 */
366 #define BCM_6368_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
367 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
368 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
369 @@ -17,6 +17,8 @@ static inline unsigned long bcm63xx_gpio
370 return 8;
371 case BCM6345_CPU_ID:
372 return 16;
373 + case BCM6362_CPU_ID:
374 + return 48;
375 case BCM6368_CPU_ID:
376 return 38;
377 case BCM6348_CPU_ID:
378 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
379 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
380 @@ -107,6 +107,39 @@
381 CKCTL_6358_USBSU_EN | \
382 CKCTL_6358_EPHY_EN)
383
384 +#define CKCTL_6362_ADSL_QPROC_EN (1 << 1)
385 +#define CKCTL_6362_ADSL_AFE_EN (1 << 2)
386 +#define CKCTL_6362_ADSL_EN (1 << 3)
387 +#define CKCTL_6362_MIPS_EN (1 << 4)
388 +#define CKCTL_6362_WLAN_OCP_EN (1 << 5)
389 +#define CKCTL_6362_SWPKT_USB_EN (1 << 7)
390 +#define CKCTL_6362_SWPKT_SAR_EN (1 << 8)
391 +#define CKCTL_6362_SAR_EN (1 << 9)
392 +#define CKCTL_6362_ROBOSW_EN (1 << 10)
393 +#define CKCTL_6362_PCM_EN (1 << 11)
394 +#define CKCTL_6362_USBD_EN (1 << 12)
395 +#define CKCTL_6362_USBH_EN (1 << 13)
396 +#define CKCTL_6362_IPSEC_EN (1 << 14)
397 +#define CKCTL_6362_SPI_EN (1 << 15)
398 +#define CKCTL_6362_HSSPI_EN (1 << 16)
399 +#define CKCTL_6362_PCIE_EN (1 << 17)
400 +#define CKCTL_6362_FAP_EN (1 << 18)
401 +#define CKCTL_6362_PHYMIPS_EN (1 << 19)
402 +#define CKCTL_6362_NAND_EN (1 << 20)
403 +
404 +#define CKCTL_6362_ALL_SAFE_EN (CKCTL_6362_PHYMIPS_EN | \
405 + CKCTL_6362_ADSL_QPROC_EN | \
406 + CKCTL_6362_ADSL_AFE_EN | \
407 + CKCTL_6362_ADSL_EN | \
408 + CKCTL_6362_SAR_EN | \
409 + CKCTL_6362_PCM_EN | \
410 + CKCTL_6362_IPSEC_EN | \
411 + CKCTL_6362_USBD_EN | \
412 + CKCTL_6362_USBH_EN | \
413 + CKCTL_6362_ROBOSW_EN | \
414 + CKCTL_6362_PCIE_EN)
415 +
416 +
417 #define CKCTL_6368_VDSL_QPROC_EN (1 << 2)
418 #define CKCTL_6368_VDSL_AFE_EN (1 << 3)
419 #define CKCTL_6368_VDSL_BONDING_EN (1 << 4)
420 @@ -148,6 +181,7 @@
421 #define PERF_IRQMASK_6345_REG 0xc
422 #define PERF_IRQMASK_6348_REG 0xc
423 #define PERF_IRQMASK_6358_REG 0xc
424 +#define PERF_IRQMASK_6362_REG 0x20
425 #define PERF_IRQMASK_6368_REG 0x20
426
427 /* Interrupt Status register */
428 @@ -156,6 +190,7 @@
429 #define PERF_IRQSTAT_6345_REG 0x10
430 #define PERF_IRQSTAT_6348_REG 0x10
431 #define PERF_IRQSTAT_6358_REG 0x10
432 +#define PERF_IRQSTAT_6362_REG 0x28
433 #define PERF_IRQSTAT_6368_REG 0x28
434
435 /* External Interrupt Configuration register */
436 @@ -164,6 +199,7 @@
437 #define PERF_EXTIRQ_CFG_REG_6345 0x14
438 #define PERF_EXTIRQ_CFG_REG_6348 0x14
439 #define PERF_EXTIRQ_CFG_REG_6358 0x14
440 +#define PERF_EXTIRQ_CFG_REG_6362 0x18
441 #define PERF_EXTIRQ_CFG_REG_6368 0x18
442
443 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
444 @@ -191,6 +227,7 @@
445 /* Soft Reset register */
446 #define PERF_SOFTRESET_REG 0x28
447 #define PERF_SOFTRESET_6328_REG 0x10
448 +#define PERF_SOFTRESET_6362_REG 0x10
449 #define PERF_SOFTRESET_6368_REG 0x10
450
451 #define SOFTRESET_6328_SPI_MASK (1 << 0)
452 @@ -244,6 +281,22 @@
453 SOFTRESET_6348_ACLC_MASK | \
454 SOFTRESET_6348_ADSLMIPSPLL_MASK)
455
456 +#define SOFTRESET_6362_SPI_MASK (1 << 0)
457 +#define SOFTRESET_6362_IPSEC_MASK (1 << 1)
458 +#define SOFTRESET_6362_EPHY_MASK (1 << 2)
459 +#define SOFTRESET_6362_SAR_MASK (1 << 3)
460 +#define SOFTRESET_6362_ENETSW_MASK (1 << 4)
461 +#define SOFTRESET_6362_USBS_MASK (1 << 5)
462 +#define SOFTRESET_6362_USBH_MASK (1 << 6)
463 +#define SOFTRESET_6362_PCM_MASK (1 << 7)
464 +#define SOFTRESET_6362_PCIE_CORE_MASK (1 << 8)
465 +#define SOFTRESET_6362_PCIE_MASK (1 << 9)
466 +#define SOFTRESET_6362_PCIE_EXT_MASK (1 << 10)
467 +#define SOFTRESET_6362_WLAN_SHIM_MASK (1 << 11)
468 +#define SOFTRESET_6362_DDR_PHY_MASK (1 << 12)
469 +#define SOFTRESET_6362_FAP_MASK (1 << 13)
470 +#define SOFTRESET_6362_WLAN_UBUS_MASK (1 << 14)
471 +
472 #define SOFTRESET_6368_SPI_MASK (1 << 0)
473 #define SOFTRESET_6368_MPI_MASK (1 << 3)
474 #define SOFTRESET_6368_EPHY_MASK (1 << 6)
475 @@ -1182,6 +1235,12 @@
476 #define SERDES_PCIE_EN (1 << 0)
477 #define SERDES_PCIE_EXD_EN (1 << 15)
478
479 +#define MISC_STRAPBUS_6362_REG 0x14
480 +#define STRAPBUS_6362_FCVO_SHIFT 1
481 +#define STRAPBUS_6362_FCVO_MASK (0x1f << STRAPBUS_6362_FCVO_SHIFT)
482 +#define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
483 +#define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
484 +
485 #define MISC_STRAPBUS_6328_REG 0x240
486 #define STRAPBUS_6328_FCVO_SHIFT 7
487 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
488 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
489 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
490 @@ -19,6 +19,7 @@ static inline int is_bcm63xx_internal_re
491 return 1;
492 break;
493 case BCM6328_CPU_ID:
494 + case BCM6362_CPU_ID:
495 case BCM6368_CPU_ID:
496 if (offset >= 0xb0000000 && offset < 0xb1000000)
497 return 1;
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