bcm63xx: add 3.9 support
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.9 / 022-MIPS-BCM63XX-remove-duplicate-spi-register-definitio.patch
1 From e1a3ace7260fad338a76595b116a6bf5b5627aa2 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Thu, 7 Mar 2013 12:20:10 +0100
4 Subject: [PATCH 1/7] MIPS: BCM63XX: remove duplicate spi register definitions
5
6 BCM6338 and BCM6348, and BCM6358 and everything after that share the
7 same register layout. To not have to redefine them for each new chip
8 and keep the code size small, only use the definitions for the first
9 chip with the certain layout.
10
11 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
12 ---
13 arch/mips/bcm63xx/dev-spi.c | 24 +++---------
14 .../include/asm/mach-bcm63xx/bcm63xx_dev_spi.h | 10 +----
15 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 40 +-------------------
16 3 files changed, 10 insertions(+), 64 deletions(-)
17
18 --- a/arch/mips/bcm63xx/dev-spi.c
19 +++ b/arch/mips/bcm63xx/dev-spi.c
20 @@ -22,10 +22,6 @@
21 /*
22 * register offsets
23 */
24 -static const unsigned long bcm6338_regs_spi[] = {
25 - __GEN_SPI_REGS_TABLE(6338)
26 -};
27 -
28 static const unsigned long bcm6348_regs_spi[] = {
29 __GEN_SPI_REGS_TABLE(6348)
30 };
31 @@ -34,23 +30,15 @@ static const unsigned long bcm6358_regs_
32 __GEN_SPI_REGS_TABLE(6358)
33 };
34
35 -static const unsigned long bcm6368_regs_spi[] = {
36 - __GEN_SPI_REGS_TABLE(6368)
37 -};
38 -
39 const unsigned long *bcm63xx_regs_spi;
40 EXPORT_SYMBOL(bcm63xx_regs_spi);
41
42 static __init void bcm63xx_spi_regs_init(void)
43 {
44 - if (BCMCPU_IS_6338())
45 - bcm63xx_regs_spi = bcm6338_regs_spi;
46 - if (BCMCPU_IS_6348())
47 + if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
48 bcm63xx_regs_spi = bcm6348_regs_spi;
49 - if (BCMCPU_IS_6358())
50 + if (BCMCPU_IS_6358() || BCMCPU_IS_6368())
51 bcm63xx_regs_spi = bcm6358_regs_spi;
52 - if (BCMCPU_IS_6368())
53 - bcm63xx_regs_spi = bcm6368_regs_spi;
54 }
55 #else
56 static __init void bcm63xx_spi_regs_init(void) { }
57 @@ -93,10 +81,10 @@ int __init bcm63xx_spi_register(void)
58 spi_resources[1].start = bcm63xx_get_irq_number(IRQ_SPI);
59
60 if (BCMCPU_IS_6338() || BCMCPU_IS_6348()) {
61 - spi_resources[0].end += BCM_6338_RSET_SPI_SIZE - 1;
62 - spi_pdata.fifo_size = SPI_6338_MSG_DATA_SIZE;
63 - spi_pdata.msg_type_shift = SPI_6338_MSG_TYPE_SHIFT;
64 - spi_pdata.msg_ctl_width = SPI_6338_MSG_CTL_WIDTH;
65 + spi_resources[0].end += BCM_6348_RSET_SPI_SIZE - 1;
66 + spi_pdata.fifo_size = SPI_6348_MSG_DATA_SIZE;
67 + spi_pdata.msg_type_shift = SPI_6348_MSG_TYPE_SHIFT;
68 + spi_pdata.msg_ctl_width = SPI_6348_MSG_CTL_WIDTH;
69 }
70
71 if (BCMCPU_IS_6358() || BCMCPU_IS_6368()) {
72 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
73 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_spi.h
74 @@ -71,18 +71,12 @@ static inline unsigned long bcm63xx_spir
75
76 return bcm63xx_regs_spi[reg];
77 #else
78 -#ifdef CONFIG_BCM63XX_CPU_6338
79 - __GEN_SPI_RSET(6338)
80 -#endif
81 -#ifdef CONFIG_BCM63XX_CPU_6348
82 +#if defined(CONFIG_BCM63XX_CPU_6338) || defined(CONFIG_BCM63XX_CPU_6348)
83 __GEN_SPI_RSET(6348)
84 #endif
85 -#ifdef CONFIG_BCM63XX_CPU_6358
86 +#if defined(CONFIG_BCM63XX_CPU_6358) || defined(CONFIG_BCM63XX_CPU_6368)
87 __GEN_SPI_RSET(6358)
88 #endif
89 -#ifdef CONFIG_BCM63XX_CPU_6368
90 - __GEN_SPI_RSET(6368)
91 -#endif
92 #endif
93 return 0;
94 }
95 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
96 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
97 @@ -1223,24 +1223,7 @@
98 * _REG relative to RSET_SPI
99 *************************************************************************/
100
101 -/* BCM 6338 SPI core */
102 -#define SPI_6338_CMD 0x00 /* 16-bits register */
103 -#define SPI_6338_INT_STATUS 0x02
104 -#define SPI_6338_INT_MASK_ST 0x03
105 -#define SPI_6338_INT_MASK 0x04
106 -#define SPI_6338_ST 0x05
107 -#define SPI_6338_CLK_CFG 0x06
108 -#define SPI_6338_FILL_BYTE 0x07
109 -#define SPI_6338_MSG_TAIL 0x09
110 -#define SPI_6338_RX_TAIL 0x0b
111 -#define SPI_6338_MSG_CTL 0x40 /* 8-bits register */
112 -#define SPI_6338_MSG_CTL_WIDTH 8
113 -#define SPI_6338_MSG_DATA 0x41
114 -#define SPI_6338_MSG_DATA_SIZE 0x3f
115 -#define SPI_6338_RX_DATA 0x80
116 -#define SPI_6338_RX_DATA_SIZE 0x3f
117 -
118 -/* BCM 6348 SPI core */
119 +/* BCM 6338/6348 SPI core */
120 #define SPI_6348_CMD 0x00 /* 16-bits register */
121 #define SPI_6348_INT_STATUS 0x02
122 #define SPI_6348_INT_MASK_ST 0x03
123 @@ -1257,7 +1240,7 @@
124 #define SPI_6348_RX_DATA 0x80
125 #define SPI_6348_RX_DATA_SIZE 0x3f
126
127 -/* BCM 6358 SPI core */
128 +/* BCM 6358/6368 SPI core */
129 #define SPI_6358_MSG_CTL 0x00 /* 16-bits register */
130 #define SPI_6358_MSG_CTL_WIDTH 16
131 #define SPI_6358_MSG_DATA 0x02
132 @@ -1274,23 +1257,6 @@
133 #define SPI_6358_MSG_TAIL 0x709
134 #define SPI_6358_RX_TAIL 0x70B
135
136 -/* BCM 6358 SPI core */
137 -#define SPI_6368_MSG_CTL 0x00 /* 16-bits register */
138 -#define SPI_6368_MSG_CTL_WIDTH 16
139 -#define SPI_6368_MSG_DATA 0x02
140 -#define SPI_6368_MSG_DATA_SIZE 0x21e
141 -#define SPI_6368_RX_DATA 0x400
142 -#define SPI_6368_RX_DATA_SIZE 0x220
143 -#define SPI_6368_CMD 0x700 /* 16-bits register */
144 -#define SPI_6368_INT_STATUS 0x702
145 -#define SPI_6368_INT_MASK_ST 0x703
146 -#define SPI_6368_INT_MASK 0x704
147 -#define SPI_6368_ST 0x705
148 -#define SPI_6368_CLK_CFG 0x706
149 -#define SPI_6368_FILL_BYTE 0x707
150 -#define SPI_6368_MSG_TAIL 0x709
151 -#define SPI_6368_RX_TAIL 0x70B
152 -
153 /* Shared SPI definitions */
154
155 /* Message configuration */
156 @@ -1298,10 +1264,8 @@
157 #define SPI_HD_W 0x01
158 #define SPI_HD_R 0x02
159 #define SPI_BYTE_CNT_SHIFT 0
160 -#define SPI_6338_MSG_TYPE_SHIFT 6
161 #define SPI_6348_MSG_TYPE_SHIFT 6
162 #define SPI_6358_MSG_TYPE_SHIFT 14
163 -#define SPI_6368_MSG_TYPE_SHIFT 14
164
165 /* Command */
166 #define SPI_CMD_NOOP 0x00