target/linux/brcm63xx/patches-3.9/027-MIPS-BCM63XX-enable-pcie-for-BCM6362.patch

   1 From ec6f1e53b22d01e628b79b99f7a33960034e97e7 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Mon, 21 Nov 2011 00:53:26 +0100
   4 Subject: [PATCH 6/7] MIPS: BCM63XX: enable pcie for BCM6362
   5
   6 The PCIe controller is almost the same as the BCM6328 one, with only
   7 the SERDES register being at a different location.
   8
   9 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  10 ---
  11  arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h |    3 ++-
  12  arch/mips/pci/pci-bcm63xx.c                       |   11 +++++++++--
  13  2 files changed, 11 insertions(+), 3 deletions(-)
  14
  15 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  16 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
  17 @@ -1365,7 +1365,8 @@
  18  /*************************************************************************
  19   * _REG relative to RSET_MISC
  20   *************************************************************************/
  21 -#define MISC_SERDES_CTRL_REG           0x0
  22 +#define MISC_SERDES_CTRL_6328_REG      0x0
  23 +#define MISC_SERDES_CTRL_6362_REG      0x4
  24  #define SERDES_PCIE_EN                 (1 << 0)
  25  #define SERDES_PCIE_EXD_EN             (1 << 15)
  26
  27 --- a/arch/mips/pci/pci-bcm63xx.c
  28 +++ b/arch/mips/pci/pci-bcm63xx.c
  29 @@ -121,11 +121,17 @@ void __iomem *pci_iospace_start;
  30  static void __init bcm63xx_reset_pcie(void)
  31  {
  32         u32 val;
  33 +       u32 reg;
  34
  35         /* enable SERDES */
  36 -       val = bcm_misc_readl(MISC_SERDES_CTRL_REG);
  37 +       if (BCMCPU_IS_6328())
  38 +               reg = MISC_SERDES_CTRL_6328_REG;
  39 +       else
  40 +               reg = MISC_SERDES_CTRL_6362_REG;
  41 +
  42 +       val = bcm_misc_readl(reg);
  43         val |= SERDES_PCIE_EN | SERDES_PCIE_EXD_EN;
  44 -       bcm_misc_writel(val, MISC_SERDES_CTRL_REG);
  45 +       bcm_misc_writel(val, reg);
  46
  47         /* reset the PCIe core */
  48         bcm63xx_core_set_reset(BCM63XX_RESET_PCIE, 1);
  49 @@ -330,6 +336,7 @@ static int __init bcm63xx_pci_init(void)
  50
  51         switch (bcm63xx_get_cpu_id()) {
  52         case BCM6328_CPU_ID:
  53 +       case BCM6362_CPU_ID:
  54                 return bcm63xx_register_pcie();
  55         case BCM6348_CPU_ID:
  56         case BCM6358_CPU_ID: