bcm63xx: update patches
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.9 / 047-bcm63xx_enet-add-support-for-Broadcom-BCM63xx-integr.patch
1 From 85b2e40acd7b33409a0d889cd3d0b964c9df4b13 Mon Sep 17 00:00:00 2001
2 From: Maxime Bizon <mbizon@freebox.fr>
3 Date: Tue, 4 Jun 2013 20:53:35 +0000
4 Subject: [PATCH 3/3] bcm63xx_enet: add support for Broadcom BCM63xx
5 integrated gigabit switch
6
7 Newer Broadcom BCM63xx SoCs: 6328, 6362 and 6368 have an integrated switch
8 which needs to be driven slightly differently from the traditional
9 external switches. This patch introduces changes in arch/mips/bcm63xx in order
10 to:
11
12 - register a bcm63xx_enetsw driver instead of bcm63xx_enet driver
13 - update DMA channels configuration & state RAM base addresses
14 - add a new platform data configuration knob to define the number of
15 ports per switch/device and force link on some ports
16 - define the required switch registers
17
18 On the driver side, the following changes are required:
19
20 - the switch ports need to be polled to ensure the link is up and
21 running and RX/TX can properly work
22 - basic switch configuration needs to be performed for the switch to
23 forward packets to the CPU
24 - update the MIB counters since the integrated
25
26 Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
27 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
28 ---
29 arch/mips/bcm63xx/boards/board_bcm963xx.c | 4 +
30 arch/mips/bcm63xx/dev-enet.c | 113 ++-
31 .../include/asm/mach-bcm63xx/bcm63xx_dev_enet.h | 28 +
32 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 50 +
33 .../mips/include/asm/mach-bcm63xx/board_bcm963xx.h | 2 +
34 drivers/net/ethernet/broadcom/bcm63xx_enet.c | 995 +++++++++++++++++++-
35 drivers/net/ethernet/broadcom/bcm63xx_enet.h | 71 ++
36 7 files changed, 1205 insertions(+), 58 deletions(-)
37
38 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
39 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
40 @@ -890,6 +890,10 @@ int __init board_register_devices(void)
41 !bcm63xx_nvram_get_mac_address(board.enet1.mac_addr))
42 bcm63xx_enet_register(1, &board.enet1);
43
44 + if (board.has_enetsw &&
45 + !bcm63xx_nvram_get_mac_address(board.enetsw.mac_addr))
46 + bcm63xx_enetsw_register(&board.enetsw);
47 +
48 if (board.has_usbd)
49 bcm63xx_usbd_register(&board.usbd);
50
51 --- a/arch/mips/bcm63xx/dev-enet.c
52 +++ b/arch/mips/bcm63xx/dev-enet.c
53 @@ -104,6 +104,64 @@ static struct platform_device bcm63xx_en
54 },
55 };
56
57 +static struct resource enetsw_res[] = {
58 + {
59 + /* start & end filled at runtime */
60 + .flags = IORESOURCE_MEM,
61 + },
62 + {
63 + /* start filled at runtime */
64 + .flags = IORESOURCE_IRQ,
65 + },
66 + {
67 + /* start filled at runtime */
68 + .flags = IORESOURCE_IRQ,
69 + },
70 +};
71 +
72 +static struct bcm63xx_enetsw_platform_data enetsw_pd;
73 +
74 +static struct platform_device bcm63xx_enetsw_device = {
75 + .name = "bcm63xx_enetsw",
76 + .num_resources = ARRAY_SIZE(enetsw_res),
77 + .resource = enetsw_res,
78 + .dev = {
79 + .platform_data = &enetsw_pd,
80 + },
81 +};
82 +
83 +static int __init register_shared(void)
84 +{
85 + int ret, chan_count;
86 +
87 + if (shared_device_registered)
88 + return 0;
89 +
90 + shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
91 + shared_res[0].end = shared_res[0].start;
92 + shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
93 +
94 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
95 + chan_count = 32;
96 + else
97 + chan_count = 16;
98 +
99 + shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
100 + shared_res[1].end = shared_res[1].start;
101 + shared_res[1].end += RSET_ENETDMAC_SIZE(chan_count) - 1;
102 +
103 + shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
104 + shared_res[2].end = shared_res[2].start;
105 + shared_res[2].end += RSET_ENETDMAS_SIZE(chan_count) - 1;
106 +
107 + ret = platform_device_register(&bcm63xx_enet_shared_device);
108 + if (ret)
109 + return ret;
110 + shared_device_registered = 1;
111 +
112 + return 0;
113 +}
114 +
115 int __init bcm63xx_enet_register(int unit,
116 const struct bcm63xx_enet_platform_data *pd)
117 {
118 @@ -117,24 +175,9 @@ int __init bcm63xx_enet_register(int uni
119 if (unit == 1 && BCMCPU_IS_6338())
120 return -ENODEV;
121
122 - if (!shared_device_registered) {
123 - shared_res[0].start = bcm63xx_regset_address(RSET_ENETDMA);
124 - shared_res[0].end = shared_res[0].start;
125 - shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
126 -
127 - shared_res[1].start = bcm63xx_regset_address(RSET_ENETDMAC);
128 - shared_res[1].end = shared_res[1].start;
129 - shared_res[1].end += RSET_ENETDMAC_SIZE(16) - 1;
130 -
131 - shared_res[2].start = bcm63xx_regset_address(RSET_ENETDMAS);
132 - shared_res[2].end = shared_res[2].start;
133 - shared_res[2].end += RSET_ENETDMAS_SIZE(16) - 1;
134 -
135 - ret = platform_device_register(&bcm63xx_enet_shared_device);
136 - if (ret)
137 - return ret;
138 - shared_device_registered = 1;
139 - }
140 + ret = register_shared();
141 + if (ret)
142 + return ret;
143
144 if (unit == 0) {
145 enet0_res[0].start = bcm63xx_regset_address(RSET_ENET0);
146 @@ -175,3 +218,37 @@ int __init bcm63xx_enet_register(int uni
147 return ret;
148 return 0;
149 }
150 +
151 +int __init
152 +bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd)
153 +{
154 + int ret;
155 +
156 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
157 + return -ENODEV;
158 +
159 + ret = register_shared();
160 + if (ret)
161 + return ret;
162 +
163 + enetsw_res[0].start = bcm63xx_regset_address(RSET_ENETSW);
164 + enetsw_res[0].end = enetsw_res[0].start;
165 + enetsw_res[0].end += RSET_ENETSW_SIZE - 1;
166 + enetsw_res[1].start = bcm63xx_get_irq_number(IRQ_ENETSW_RXDMA0);
167 + enetsw_res[2].start = bcm63xx_get_irq_number(IRQ_ENETSW_TXDMA0);
168 + if (!enetsw_res[2].start)
169 + enetsw_res[2].start = -1;
170 +
171 + memcpy(bcm63xx_enetsw_device.dev.platform_data, pd, sizeof(*pd));
172 +
173 + if (BCMCPU_IS_6328())
174 + enetsw_pd.num_ports = ENETSW_PORTS_6328;
175 + else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
176 + enetsw_pd.num_ports = ENETSW_PORTS_6368;
177 +
178 + ret = platform_device_register(&bcm63xx_enetsw_device);
179 + if (ret)
180 + return ret;
181 +
182 + return 0;
183 +}
184 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
185 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
186 @@ -39,7 +39,35 @@ struct bcm63xx_enet_platform_data {
187 int phy_id, int reg, int val));
188 };
189
190 +/*
191 + * on board ethernet switch platform data
192 + */
193 +#define ENETSW_MAX_PORT 8
194 +#define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
195 +#define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
196 +
197 +#define ENETSW_RGMII_PORT0 4
198 +
199 +struct bcm63xx_enetsw_port {
200 + int used;
201 + int phy_id;
202 +
203 + int bypass_link;
204 + int force_speed;
205 + int force_duplex_full;
206 +
207 + const char *name;
208 +};
209 +
210 +struct bcm63xx_enetsw_platform_data {
211 + char mac_addr[ETH_ALEN];
212 + int num_ports;
213 + struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
214 +};
215 +
216 int __init bcm63xx_enet_register(int unit,
217 const struct bcm63xx_enet_platform_data *pd);
218
219 +int bcm63xx_enetsw_register(const struct bcm63xx_enetsw_platform_data *pd);
220 +
221 #endif /* ! BCM63XX_DEV_ENET_H_ */
222 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
223 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
224 @@ -873,10 +873,60 @@
225 * _REG relative to RSET_ENETSW
226 *************************************************************************/
227
228 +/* Port traffic control */
229 +#define ENETSW_PTCTRL_REG(x) (0x0 + (x))
230 +#define ENETSW_PTCTRL_RXDIS_MASK (1 << 0)
231 +#define ENETSW_PTCTRL_TXDIS_MASK (1 << 1)
232 +
233 +/* Switch mode register */
234 +#define ENETSW_SWMODE_REG (0xb)
235 +#define ENETSW_SWMODE_FWD_EN_MASK (1 << 1)
236 +
237 +/* IMP override Register */
238 +#define ENETSW_IMPOV_REG (0xe)
239 +#define ENETSW_IMPOV_FORCE_MASK (1 << 7)
240 +#define ENETSW_IMPOV_TXFLOW_MASK (1 << 5)
241 +#define ENETSW_IMPOV_RXFLOW_MASK (1 << 4)
242 +#define ENETSW_IMPOV_1000_MASK (1 << 3)
243 +#define ENETSW_IMPOV_100_MASK (1 << 2)
244 +#define ENETSW_IMPOV_FDX_MASK (1 << 1)
245 +#define ENETSW_IMPOV_LINKUP_MASK (1 << 0)
246 +
247 +/* Port override Register */
248 +#define ENETSW_PORTOV_REG(x) (0x58 + (x))
249 +#define ENETSW_PORTOV_ENABLE_MASK (1 << 6)
250 +#define ENETSW_PORTOV_TXFLOW_MASK (1 << 5)
251 +#define ENETSW_PORTOV_RXFLOW_MASK (1 << 4)
252 +#define ENETSW_PORTOV_1000_MASK (1 << 3)
253 +#define ENETSW_PORTOV_100_MASK (1 << 2)
254 +#define ENETSW_PORTOV_FDX_MASK (1 << 1)
255 +#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
256 +
257 +/* MDIO control register */
258 +#define ENETSW_MDIOC_REG (0xb0)
259 +#define ENETSW_MDIOC_EXT_MASK (1 << 16)
260 +#define ENETSW_MDIOC_REG_SHIFT 20
261 +#define ENETSW_MDIOC_PHYID_SHIFT 25
262 +#define ENETSW_MDIOC_RD_MASK (1 << 30)
263 +#define ENETSW_MDIOC_WR_MASK (1 << 31)
264 +
265 +/* MDIO data register */
266 +#define ENETSW_MDIOD_REG (0xb4)
267 +
268 +/* Global Management Configuration Register */
269 +#define ENETSW_GMCR_REG (0x200)
270 +#define ENETSW_GMCR_RST_MIB_MASK (1 << 0)
271 +
272 /* MIB register */
273 #define ENETSW_MIB_REG(x) (0x2800 + (x) * 4)
274 #define ENETSW_MIB_REG_COUNT 47
275
276 +/* Jumbo control register port mask register */
277 +#define ENETSW_JMBCTL_PORT_REG (0x4004)
278 +
279 +/* Jumbo control mib good frame register */
280 +#define ENETSW_JMBCTL_MAXSIZE_REG (0x4008)
281 +
282
283 /*************************************************************************
284 * _REG relative to RSET_OHCI_PRIV
285 --- a/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
286 +++ b/arch/mips/include/asm/mach-bcm63xx/board_bcm963xx.h
287 @@ -24,6 +24,7 @@ struct board_info {
288 /* enabled feature/device */
289 unsigned int has_enet0:1;
290 unsigned int has_enet1:1;
291 + unsigned int has_enetsw:1;
292 unsigned int has_pci:1;
293 unsigned int has_pccard:1;
294 unsigned int has_ohci0:1;
295 @@ -36,6 +37,7 @@ struct board_info {
296 /* ethernet config */
297 struct bcm63xx_enet_platform_data enet0;
298 struct bcm63xx_enet_platform_data enet1;
299 + struct bcm63xx_enetsw_platform_data enetsw;
300
301 /* USB config */
302 struct bcm63xx_usbd_platform_data usbd;
303 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
304 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
305 @@ -59,8 +59,43 @@ static inline void enet_writel(struct bc
306 }
307
308 /*
309 - * io helpers to access shared registers
310 + * io helpers to access switch registers
311 */
312 +static inline u32 enetsw_readl(struct bcm_enet_priv *priv, u32 off)
313 +{
314 + return bcm_readl(priv->base + off);
315 +}
316 +
317 +static inline void enetsw_writel(struct bcm_enet_priv *priv,
318 + u32 val, u32 off)
319 +{
320 + bcm_writel(val, priv->base + off);
321 +}
322 +
323 +static inline u16 enetsw_readw(struct bcm_enet_priv *priv, u32 off)
324 +{
325 + return bcm_readw(priv->base + off);
326 +}
327 +
328 +static inline void enetsw_writew(struct bcm_enet_priv *priv,
329 + u16 val, u32 off)
330 +{
331 + bcm_writew(val, priv->base + off);
332 +}
333 +
334 +static inline u8 enetsw_readb(struct bcm_enet_priv *priv, u32 off)
335 +{
336 + return bcm_readb(priv->base + off);
337 +}
338 +
339 +static inline void enetsw_writeb(struct bcm_enet_priv *priv,
340 + u8 val, u32 off)
341 +{
342 + bcm_writeb(val, priv->base + off);
343 +}
344 +
345 +
346 +/* io helpers to access shared registers */
347 static inline u32 enet_dma_readl(struct bcm_enet_priv *priv, u32 off)
348 {
349 return bcm_readl(bcm_enet_shared_base[0] + off);
350 @@ -218,7 +253,6 @@ static int bcm_enet_refill_rx(struct net
351 if (!skb)
352 break;
353 priv->rx_skb[desc_idx] = skb;
354 -
355 p = dma_map_single(&priv->pdev->dev, skb->data,
356 priv->rx_skb_size,
357 DMA_FROM_DEVICE);
358 @@ -321,7 +355,8 @@ static int bcm_enet_receive_queue(struct
359 }
360
361 /* recycle packet if it's marked as bad */
362 - if (unlikely(len_stat & DMADESC_ERR_MASK)) {
363 + if (!priv->enet_is_sw &&
364 + unlikely(len_stat & DMADESC_ERR_MASK)) {
365 dev->stats.rx_errors++;
366
367 if (len_stat & DMADESC_OVSIZE_MASK)
368 @@ -552,6 +587,26 @@ static int bcm_enet_start_xmit(struct sk
369 goto out_unlock;
370 }
371
372 + /* pad small packets sent on a switch device */
373 + if (priv->enet_is_sw && skb->len < 64) {
374 + int needed = 64 - skb->len;
375 + char *data;
376 +
377 + if (unlikely(skb_tailroom(skb) < needed)) {
378 + struct sk_buff *nskb;
379 +
380 + nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
381 + if (!nskb) {
382 + ret = NETDEV_TX_BUSY;
383 + goto out_unlock;
384 + }
385 + dev_kfree_skb(skb);
386 + skb = nskb;
387 + }
388 + data = skb_put(skb, needed);
389 + memset(data, 0, needed);
390 + }
391 +
392 /* point to the next available desc */
393 desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
394 priv->tx_skb[priv->tx_curr_desc] = skb;
395 @@ -961,9 +1016,9 @@ static int bcm_enet_open(struct net_devi
396 enet_writel(priv, priv->hw_mtu, ENET_TXMAXLEN_REG);
397
398 /* set dma maximum burst len */
399 - enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
400 + enet_dmac_writel(priv, priv->dma_maxburst,
401 ENETDMAC_MAXBURST_REG(priv->rx_chan));
402 - enet_dmac_writel(priv, BCMENET_DMA_MAXBURST,
403 + enet_dmac_writel(priv, priv->dma_maxburst,
404 ENETDMAC_MAXBURST_REG(priv->tx_chan));
405
406 /* set correct transmit fifo watermark */
407 @@ -1569,7 +1624,7 @@ static int compute_hw_mtu(struct bcm_ene
408 * it's appended
409 */
410 priv->rx_skb_size = ALIGN(actual_mtu + ETH_FCS_LEN,
411 - BCMENET_DMA_MAXBURST * 4);
412 + priv->dma_maxburst * 4);
413 return 0;
414 }
415
416 @@ -1676,6 +1731,9 @@ static int bcm_enet_probe(struct platfor
417 return -ENOMEM;
418 priv = netdev_priv(dev);
419
420 + priv->enet_is_sw = false;
421 + priv->dma_maxburst = BCMENET_DMA_MAXBURST;
422 +
423 ret = compute_hw_mtu(priv, dev->mtu);
424 if (ret)
425 goto out;
426 @@ -1901,60 +1959,916 @@ struct platform_driver bcm63xx_enet_driv
427 };
428
429 /*
430 - * reserve & remap memory space shared between all macs
431 + * switch mii access callbacks
432 */
433 -static int bcm_enet_shared_probe(struct platform_device *pdev)
434 +static int bcmenet_sw_mdio_read(struct bcm_enet_priv *priv,
435 + int ext, int phy_id, int location)
436 {
437 - struct resource *res;
438 - void __iomem *p[3];
439 - unsigned int i;
440 + u32 reg;
441 + int ret;
442
443 - memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
444 + spin_lock_bh(&priv->enetsw_mdio_lock);
445 + enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
446
447 - for (i = 0; i < 3; i++) {
448 - res = platform_get_resource(pdev, IORESOURCE_MEM, i);
449 - p[i] = devm_ioremap_resource(&pdev->dev, res);
450 - if (!p[i])
451 - return -ENOMEM;
452 - }
453 + reg = ENETSW_MDIOC_RD_MASK |
454 + (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
455 + (location << ENETSW_MDIOC_REG_SHIFT);
456 +
457 + if (ext)
458 + reg |= ENETSW_MDIOC_EXT_MASK;
459 +
460 + enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
461 + udelay(50);
462 + ret = enetsw_readw(priv, ENETSW_MDIOD_REG);
463 + spin_unlock_bh(&priv->enetsw_mdio_lock);
464 + return ret;
465 +}
466
467 - memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
468 +static void bcmenet_sw_mdio_write(struct bcm_enet_priv *priv,
469 + int ext, int phy_id, int location,
470 + uint16_t data)
471 +{
472 + u32 reg;
473
474 - return 0;
475 + spin_lock_bh(&priv->enetsw_mdio_lock);
476 + enetsw_writel(priv, 0, ENETSW_MDIOC_REG);
477 +
478 + reg = ENETSW_MDIOC_WR_MASK |
479 + (phy_id << ENETSW_MDIOC_PHYID_SHIFT) |
480 + (location << ENETSW_MDIOC_REG_SHIFT);
481 +
482 + if (ext)
483 + reg |= ENETSW_MDIOC_EXT_MASK;
484 +
485 + reg |= data;
486 +
487 + enetsw_writel(priv, reg, ENETSW_MDIOC_REG);
488 + udelay(50);
489 + spin_unlock_bh(&priv->enetsw_mdio_lock);
490 }
491
492 -static int bcm_enet_shared_remove(struct platform_device *pdev)
493 +static inline int bcm_enet_port_is_rgmii(int portid)
494 {
495 - return 0;
496 + return portid >= ENETSW_RGMII_PORT0;
497 }
498
499 /*
500 - * this "shared" driver is needed because both macs share a single
501 - * address space
502 + * enet sw PHY polling
503 */
504 -struct platform_driver bcm63xx_enet_shared_driver = {
505 - .probe = bcm_enet_shared_probe,
506 - .remove = bcm_enet_shared_remove,
507 - .driver = {
508 - .name = "bcm63xx_enet_shared",
509 - .owner = THIS_MODULE,
510 - },
511 -};
512 +static void swphy_poll_timer(unsigned long data)
513 +{
514 + struct bcm_enet_priv *priv = (struct bcm_enet_priv *)data;
515 + unsigned int i;
516 +
517 + for (i = 0; i < priv->num_ports; i++) {
518 + struct bcm63xx_enetsw_port *port;
519 + int val, j, up, advertise, lpa, lpa2, speed, duplex, media;
520 + int external_phy = bcm_enet_port_is_rgmii(i);
521 + u8 override;
522 +
523 + port = &priv->used_ports[i];
524 + if (!port->used)
525 + continue;
526 +
527 + if (port->bypass_link)
528 + continue;
529 +
530 + /* dummy read to clear */
531 + for (j = 0; j < 2; j++)
532 + val = bcmenet_sw_mdio_read(priv, external_phy,
533 + port->phy_id, MII_BMSR);
534 +
535 + if (val == 0xffff)
536 + continue;
537 +
538 + up = (val & BMSR_LSTATUS) ? 1 : 0;
539 + if (!(up ^ priv->sw_port_link[i]))
540 + continue;
541 +
542 + priv->sw_port_link[i] = up;
543 +
544 + /* link changed */
545 + if (!up) {
546 + dev_info(&priv->pdev->dev, "link DOWN on %s\n",
547 + port->name);
548 + enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
549 + ENETSW_PORTOV_REG(i));
550 + enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
551 + ENETSW_PTCTRL_TXDIS_MASK,
552 + ENETSW_PTCTRL_REG(i));
553 + continue;
554 + }
555 +
556 + advertise = bcmenet_sw_mdio_read(priv, external_phy,
557 + port->phy_id, MII_ADVERTISE);
558 +
559 + lpa = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
560 + MII_LPA);
561 +
562 + lpa2 = bcmenet_sw_mdio_read(priv, external_phy, port->phy_id,
563 + MII_STAT1000);
564 +
565 + /* figure out media and duplex from advertise and LPA values */
566 + media = mii_nway_result(lpa & advertise);
567 + duplex = (media & ADVERTISE_FULL) ? 1 : 0;
568 + if (lpa2 & LPA_1000FULL)
569 + duplex = 1;
570 +
571 + if (lpa2 & (LPA_1000FULL | LPA_1000HALF))
572 + speed = 1000;
573 + else {
574 + if (media & (ADVERTISE_100FULL | ADVERTISE_100HALF))
575 + speed = 100;
576 + else
577 + speed = 10;
578 + }
579 +
580 + dev_info(&priv->pdev->dev,
581 + "link UP on %s, %dMbps, %s-duplex\n",
582 + port->name, speed, duplex ? "full" : "half");
583 +
584 + override = ENETSW_PORTOV_ENABLE_MASK |
585 + ENETSW_PORTOV_LINKUP_MASK;
586 +
587 + if (speed == 1000)
588 + override |= ENETSW_IMPOV_1000_MASK;
589 + else if (speed == 100)
590 + override |= ENETSW_IMPOV_100_MASK;
591 + if (duplex)
592 + override |= ENETSW_IMPOV_FDX_MASK;
593 +
594 + enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
595 + enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
596 + }
597 +
598 + priv->swphy_poll.expires = jiffies + HZ;
599 + add_timer(&priv->swphy_poll);
600 +}
601
602 /*
603 - * entry point
604 + * open callback, allocate dma rings & buffers and start rx operation
605 */
606 -static int __init bcm_enet_init(void)
607 +static int bcm_enetsw_open(struct net_device *dev)
608 {
609 - int ret;
610 + struct bcm_enet_priv *priv;
611 + struct device *kdev;
612 + int i, ret;
613 + unsigned int size;
614 + void *p;
615 + u32 val;
616
617 - ret = platform_driver_register(&bcm63xx_enet_shared_driver);
618 - if (ret)
619 - return ret;
620 + priv = netdev_priv(dev);
621 + kdev = &priv->pdev->dev;
622
623 - ret = platform_driver_register(&bcm63xx_enet_driver);
624 + /* mask all interrupts and request them */
625 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
626 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
627 +
628 + ret = request_irq(priv->irq_rx, bcm_enet_isr_dma,
629 + IRQF_DISABLED, dev->name, dev);
630 if (ret)
631 - platform_driver_unregister(&bcm63xx_enet_shared_driver);
632 + goto out_freeirq;
633 +
634 + if (priv->irq_tx != -1) {
635 + ret = request_irq(priv->irq_tx, bcm_enet_isr_dma,
636 + IRQF_DISABLED, dev->name, dev);
637 + if (ret)
638 + goto out_freeirq_rx;
639 + }
640 +
641 + /* allocate rx dma ring */
642 + size = priv->rx_ring_size * sizeof(struct bcm_enet_desc);
643 + p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
644 + if (!p) {
645 + dev_err(kdev, "cannot allocate rx ring %u\n", size);
646 + ret = -ENOMEM;
647 + goto out_freeirq_tx;
648 + }
649 +
650 + memset(p, 0, size);
651 + priv->rx_desc_alloc_size = size;
652 + priv->rx_desc_cpu = p;
653 +
654 + /* allocate tx dma ring */
655 + size = priv->tx_ring_size * sizeof(struct bcm_enet_desc);
656 + p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
657 + if (!p) {
658 + dev_err(kdev, "cannot allocate tx ring\n");
659 + ret = -ENOMEM;
660 + goto out_free_rx_ring;
661 + }
662 +
663 + memset(p, 0, size);
664 + priv->tx_desc_alloc_size = size;
665 + priv->tx_desc_cpu = p;
666 +
667 + priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
668 + GFP_KERNEL);
669 + if (!priv->tx_skb) {
670 + dev_err(kdev, "cannot allocate rx skb queue\n");
671 + ret = -ENOMEM;
672 + goto out_free_tx_ring;
673 + }
674 +
675 + priv->tx_desc_count = priv->tx_ring_size;
676 + priv->tx_dirty_desc = 0;
677 + priv->tx_curr_desc = 0;
678 + spin_lock_init(&priv->tx_lock);
679 +
680 + /* init & fill rx ring with skbs */
681 + priv->rx_skb = kzalloc(sizeof(struct sk_buff *) * priv->rx_ring_size,
682 + GFP_KERNEL);
683 + if (!priv->rx_skb) {
684 + dev_err(kdev, "cannot allocate rx skb queue\n");
685 + ret = -ENOMEM;
686 + goto out_free_tx_skb;
687 + }
688 +
689 + priv->rx_desc_count = 0;
690 + priv->rx_dirty_desc = 0;
691 + priv->rx_curr_desc = 0;
692 +
693 + /* disable all ports */
694 + for (i = 0; i < priv->num_ports; i++) {
695 + enetsw_writeb(priv, ENETSW_PORTOV_ENABLE_MASK,
696 + ENETSW_PORTOV_REG(i));
697 + enetsw_writeb(priv, ENETSW_PTCTRL_RXDIS_MASK |
698 + ENETSW_PTCTRL_TXDIS_MASK,
699 + ENETSW_PTCTRL_REG(i));
700 +
701 + priv->sw_port_link[i] = 0;
702 + }
703 +
704 + /* reset mib */
705 + val = enetsw_readb(priv, ENETSW_GMCR_REG);
706 + val |= ENETSW_GMCR_RST_MIB_MASK;
707 + enetsw_writeb(priv, val, ENETSW_GMCR_REG);
708 + mdelay(1);
709 + val &= ~ENETSW_GMCR_RST_MIB_MASK;
710 + enetsw_writeb(priv, val, ENETSW_GMCR_REG);
711 + mdelay(1);
712 +
713 + /* force CPU port state */
714 + val = enetsw_readb(priv, ENETSW_IMPOV_REG);
715 + val |= ENETSW_IMPOV_FORCE_MASK | ENETSW_IMPOV_LINKUP_MASK;
716 + enetsw_writeb(priv, val, ENETSW_IMPOV_REG);
717 +
718 + /* enable switch forward engine */
719 + val = enetsw_readb(priv, ENETSW_SWMODE_REG);
720 + val |= ENETSW_SWMODE_FWD_EN_MASK;
721 + enetsw_writeb(priv, val, ENETSW_SWMODE_REG);
722 +
723 + /* enable jumbo on all ports */
724 + enetsw_writel(priv, 0x1ff, ENETSW_JMBCTL_PORT_REG);
725 + enetsw_writew(priv, 9728, ENETSW_JMBCTL_MAXSIZE_REG);
726 +
727 + /* initialize flow control buffer allocation */
728 + enet_dma_writel(priv, ENETDMA_BUFALLOC_FORCE_MASK | 0,
729 + ENETDMA_BUFALLOC_REG(priv->rx_chan));
730 +
731 + if (bcm_enet_refill_rx(dev)) {
732 + dev_err(kdev, "cannot allocate rx skb queue\n");
733 + ret = -ENOMEM;
734 + goto out;
735 + }
736 +
737 + /* write rx & tx ring addresses */
738 + enet_dmas_writel(priv, priv->rx_desc_dma,
739 + ENETDMAS_RSTART_REG(priv->rx_chan));
740 + enet_dmas_writel(priv, priv->tx_desc_dma,
741 + ENETDMAS_RSTART_REG(priv->tx_chan));
742 +
743 + /* clear remaining state ram for rx & tx channel */
744 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->rx_chan));
745 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM2_REG(priv->tx_chan));
746 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->rx_chan));
747 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM3_REG(priv->tx_chan));
748 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->rx_chan));
749 + enet_dmas_writel(priv, 0, ENETDMAS_SRAM4_REG(priv->tx_chan));
750 +
751 + /* set dma maximum burst len */
752 + enet_dmac_writel(priv, priv->dma_maxburst,
753 + ENETDMAC_MAXBURST_REG(priv->rx_chan));
754 + enet_dmac_writel(priv, priv->dma_maxburst,
755 + ENETDMAC_MAXBURST_REG(priv->tx_chan));
756 +
757 + /* set flow control low/high threshold to 1/3 / 2/3 */
758 + val = priv->rx_ring_size / 3;
759 + enet_dma_writel(priv, val, ENETDMA_FLOWCL_REG(priv->rx_chan));
760 + val = (priv->rx_ring_size * 2) / 3;
761 + enet_dma_writel(priv, val, ENETDMA_FLOWCH_REG(priv->rx_chan));
762 +
763 + /* all set, enable mac and interrupts, start dma engine and
764 + * kick rx dma channel
765 + */
766 + wmb();
767 + enet_dma_writel(priv, ENETDMA_CFG_EN_MASK, ENETDMA_CFG_REG);
768 + enet_dmac_writel(priv, ENETDMAC_CHANCFG_EN_MASK,
769 + ENETDMAC_CHANCFG_REG(priv->rx_chan));
770 +
771 + /* watch "packet transferred" interrupt in rx and tx */
772 + enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
773 + ENETDMAC_IR_REG(priv->rx_chan));
774 + enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
775 + ENETDMAC_IR_REG(priv->tx_chan));
776 +
777 + /* make sure we enable napi before rx interrupt */
778 + napi_enable(&priv->napi);
779 +
780 + enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
781 + ENETDMAC_IRMASK_REG(priv->rx_chan));
782 + enet_dmac_writel(priv, ENETDMAC_IR_PKTDONE_MASK,
783 + ENETDMAC_IRMASK_REG(priv->tx_chan));
784 +
785 + netif_carrier_on(dev);
786 + netif_start_queue(dev);
787 +
788 + /* apply override config for bypass_link ports here. */
789 + for (i = 0; i < priv->num_ports; i++) {
790 + struct bcm63xx_enetsw_port *port;
791 + u8 override;
792 + port = &priv->used_ports[i];
793 + if (!port->used)
794 + continue;
795 +
796 + if (!port->bypass_link)
797 + continue;
798 +
799 + override = ENETSW_PORTOV_ENABLE_MASK |
800 + ENETSW_PORTOV_LINKUP_MASK;
801 +
802 + switch (port->force_speed) {
803 + case 1000:
804 + override |= ENETSW_IMPOV_1000_MASK;
805 + break;
806 + case 100:
807 + override |= ENETSW_IMPOV_100_MASK;
808 + break;
809 + case 10:
810 + break;
811 + default:
812 + pr_warn("invalid forced speed on port %s: assume 10\n",
813 + port->name);
814 + break;
815 + }
816 +
817 + if (port->force_duplex_full)
818 + override |= ENETSW_IMPOV_FDX_MASK;
819 +
820 +
821 + enetsw_writeb(priv, override, ENETSW_PORTOV_REG(i));
822 + enetsw_writeb(priv, 0, ENETSW_PTCTRL_REG(i));
823 + }
824 +
825 + /* start phy polling timer */
826 + init_timer(&priv->swphy_poll);
827 + priv->swphy_poll.function = swphy_poll_timer;
828 + priv->swphy_poll.data = (unsigned long)priv;
829 + priv->swphy_poll.expires = jiffies;
830 + add_timer(&priv->swphy_poll);
831 + return 0;
832 +
833 +out:
834 + for (i = 0; i < priv->rx_ring_size; i++) {
835 + struct bcm_enet_desc *desc;
836 +
837 + if (!priv->rx_skb[i])
838 + continue;
839 +
840 + desc = &priv->rx_desc_cpu[i];
841 + dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
842 + DMA_FROM_DEVICE);
843 + kfree_skb(priv->rx_skb[i]);
844 + }
845 + kfree(priv->rx_skb);
846 +
847 +out_free_tx_skb:
848 + kfree(priv->tx_skb);
849 +
850 +out_free_tx_ring:
851 + dma_free_coherent(kdev, priv->tx_desc_alloc_size,
852 + priv->tx_desc_cpu, priv->tx_desc_dma);
853 +
854 +out_free_rx_ring:
855 + dma_free_coherent(kdev, priv->rx_desc_alloc_size,
856 + priv->rx_desc_cpu, priv->rx_desc_dma);
857 +
858 +out_freeirq_tx:
859 + if (priv->irq_tx != -1)
860 + free_irq(priv->irq_tx, dev);
861 +
862 +out_freeirq_rx:
863 + free_irq(priv->irq_rx, dev);
864 +
865 +out_freeirq:
866 + return ret;
867 +}
868 +
869 +/* stop callback */
870 +static int bcm_enetsw_stop(struct net_device *dev)
871 +{
872 + struct bcm_enet_priv *priv;
873 + struct device *kdev;
874 + int i;
875 +
876 + priv = netdev_priv(dev);
877 + kdev = &priv->pdev->dev;
878 +
879 + del_timer_sync(&priv->swphy_poll);
880 + netif_stop_queue(dev);
881 + napi_disable(&priv->napi);
882 + del_timer_sync(&priv->rx_timeout);
883 +
884 + /* mask all interrupts */
885 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->rx_chan));
886 + enet_dmac_writel(priv, 0, ENETDMAC_IRMASK_REG(priv->tx_chan));
887 +
888 + /* disable dma & mac */
889 + bcm_enet_disable_dma(priv, priv->tx_chan);
890 + bcm_enet_disable_dma(priv, priv->rx_chan);
891 +
892 + /* force reclaim of all tx buffers */
893 + bcm_enet_tx_reclaim(dev, 1);
894 +
895 + /* free the rx skb ring */
896 + for (i = 0; i < priv->rx_ring_size; i++) {
897 + struct bcm_enet_desc *desc;
898 +
899 + if (!priv->rx_skb[i])
900 + continue;
901 +
902 + desc = &priv->rx_desc_cpu[i];
903 + dma_unmap_single(kdev, desc->address, priv->rx_skb_size,
904 + DMA_FROM_DEVICE);
905 + kfree_skb(priv->rx_skb[i]);
906 + }
907 +
908 + /* free remaining allocated memory */
909 + kfree(priv->rx_skb);
910 + kfree(priv->tx_skb);
911 + dma_free_coherent(kdev, priv->rx_desc_alloc_size,
912 + priv->rx_desc_cpu, priv->rx_desc_dma);
913 + dma_free_coherent(kdev, priv->tx_desc_alloc_size,
914 + priv->tx_desc_cpu, priv->tx_desc_dma);
915 + if (priv->irq_tx != -1)
916 + free_irq(priv->irq_tx, dev);
917 + free_irq(priv->irq_rx, dev);
918 +
919 + return 0;
920 +}
921 +
922 +/* try to sort out phy external status by walking the used_port field
923 + * in the bcm_enet_priv structure. in case the phy address is not
924 + * assigned to any physical port on the switch, assume it is external
925 + * (and yell at the user).
926 + */
927 +static int bcm_enetsw_phy_is_external(struct bcm_enet_priv *priv, int phy_id)
928 +{
929 + int i;
930 +
931 + for (i = 0; i < priv->num_ports; ++i) {
932 + if (!priv->used_ports[i].used)
933 + continue;
934 + if (priv->used_ports[i].phy_id == phy_id)
935 + return bcm_enet_port_is_rgmii(i);
936 + }
937 +
938 + printk_once(KERN_WARNING "bcm63xx_enet: could not find a used port with phy_id %i, assuming phy is external\n",
939 + phy_id);
940 + return 1;
941 +}
942 +
943 +/* can't use bcmenet_sw_mdio_read directly as we need to sort out
944 + * external/internal status of the given phy_id first.
945 + */
946 +static int bcm_enetsw_mii_mdio_read(struct net_device *dev, int phy_id,
947 + int location)
948 +{
949 + struct bcm_enet_priv *priv;
950 +
951 + priv = netdev_priv(dev);
952 + return bcmenet_sw_mdio_read(priv,
953 + bcm_enetsw_phy_is_external(priv, phy_id),
954 + phy_id, location);
955 +}
956 +
957 +/* can't use bcmenet_sw_mdio_write directly as we need to sort out
958 + * external/internal status of the given phy_id first.
959 + */
960 +static void bcm_enetsw_mii_mdio_write(struct net_device *dev, int phy_id,
961 + int location,
962 + int val)
963 +{
964 + struct bcm_enet_priv *priv;
965 +
966 + priv = netdev_priv(dev);
967 + bcmenet_sw_mdio_write(priv, bcm_enetsw_phy_is_external(priv, phy_id),
968 + phy_id, location, val);
969 +}
970 +
971 +static int bcm_enetsw_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
972 +{
973 + struct mii_if_info mii;
974 +
975 + mii.dev = dev;
976 + mii.mdio_read = bcm_enetsw_mii_mdio_read;
977 + mii.mdio_write = bcm_enetsw_mii_mdio_write;
978 + mii.phy_id = 0;
979 + mii.phy_id_mask = 0x3f;
980 + mii.reg_num_mask = 0x1f;
981 + return generic_mii_ioctl(&mii, if_mii(rq), cmd, NULL);
982 +
983 +}
984 +
985 +static const struct net_device_ops bcm_enetsw_ops = {
986 + .ndo_open = bcm_enetsw_open,
987 + .ndo_stop = bcm_enetsw_stop,
988 + .ndo_start_xmit = bcm_enet_start_xmit,
989 + .ndo_change_mtu = bcm_enet_change_mtu,
990 + .ndo_do_ioctl = bcm_enetsw_ioctl,
991 +};
992 +
993 +
994 +static const struct bcm_enet_stats bcm_enetsw_gstrings_stats[] = {
995 + { "rx_packets", DEV_STAT(rx_packets), -1 },
996 + { "tx_packets", DEV_STAT(tx_packets), -1 },
997 + { "rx_bytes", DEV_STAT(rx_bytes), -1 },
998 + { "tx_bytes", DEV_STAT(tx_bytes), -1 },
999 + { "rx_errors", DEV_STAT(rx_errors), -1 },
1000 + { "tx_errors", DEV_STAT(tx_errors), -1 },
1001 + { "rx_dropped", DEV_STAT(rx_dropped), -1 },
1002 + { "tx_dropped", DEV_STAT(tx_dropped), -1 },
1003 +
1004 + { "tx_good_octets", GEN_STAT(mib.tx_gd_octets), ETHSW_MIB_RX_GD_OCT },
1005 + { "tx_unicast", GEN_STAT(mib.tx_unicast), ETHSW_MIB_RX_BRDCAST },
1006 + { "tx_broadcast", GEN_STAT(mib.tx_brdcast), ETHSW_MIB_RX_BRDCAST },
1007 + { "tx_multicast", GEN_STAT(mib.tx_mult), ETHSW_MIB_RX_MULT },
1008 + { "tx_64_octets", GEN_STAT(mib.tx_64), ETHSW_MIB_RX_64 },
1009 + { "tx_65_127_oct", GEN_STAT(mib.tx_65_127), ETHSW_MIB_RX_65_127 },
1010 + { "tx_128_255_oct", GEN_STAT(mib.tx_128_255), ETHSW_MIB_RX_128_255 },
1011 + { "tx_256_511_oct", GEN_STAT(mib.tx_256_511), ETHSW_MIB_RX_256_511 },
1012 + { "tx_512_1023_oct", GEN_STAT(mib.tx_512_1023), ETHSW_MIB_RX_512_1023},
1013 + { "tx_1024_1522_oct", GEN_STAT(mib.tx_1024_max),
1014 + ETHSW_MIB_RX_1024_1522 },
1015 + { "tx_1523_2047_oct", GEN_STAT(mib.tx_1523_2047),
1016 + ETHSW_MIB_RX_1523_2047 },
1017 + { "tx_2048_4095_oct", GEN_STAT(mib.tx_2048_4095),
1018 + ETHSW_MIB_RX_2048_4095 },
1019 + { "tx_4096_8191_oct", GEN_STAT(mib.tx_4096_8191),
1020 + ETHSW_MIB_RX_4096_8191 },
1021 + { "tx_8192_9728_oct", GEN_STAT(mib.tx_8192_9728),
1022 + ETHSW_MIB_RX_8192_9728 },
1023 + { "tx_oversize", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR },
1024 + { "tx_oversize_drop", GEN_STAT(mib.tx_ovr), ETHSW_MIB_RX_OVR_DISC },
1025 + { "tx_dropped", GEN_STAT(mib.tx_drop), ETHSW_MIB_RX_DROP },
1026 + { "tx_undersize", GEN_STAT(mib.tx_underrun), ETHSW_MIB_RX_UND },
1027 + { "tx_pause", GEN_STAT(mib.tx_pause), ETHSW_MIB_RX_PAUSE },
1028 +
1029 + { "rx_good_octets", GEN_STAT(mib.rx_gd_octets), ETHSW_MIB_TX_ALL_OCT },
1030 + { "rx_broadcast", GEN_STAT(mib.rx_brdcast), ETHSW_MIB_TX_BRDCAST },
1031 + { "rx_multicast", GEN_STAT(mib.rx_mult), ETHSW_MIB_TX_MULT },
1032 + { "rx_unicast", GEN_STAT(mib.rx_unicast), ETHSW_MIB_TX_MULT },
1033 + { "rx_pause", GEN_STAT(mib.rx_pause), ETHSW_MIB_TX_PAUSE },
1034 + { "rx_dropped", GEN_STAT(mib.rx_drop), ETHSW_MIB_TX_DROP_PKTS },
1035 +
1036 +};
1037 +
1038 +#define BCM_ENETSW_STATS_LEN \
1039 + (sizeof(bcm_enetsw_gstrings_stats) / sizeof(struct bcm_enet_stats))
1040 +
1041 +static void bcm_enetsw_get_strings(struct net_device *netdev,
1042 + u32 stringset, u8 *data)
1043 +{
1044 + int i;
1045 +
1046 + switch (stringset) {
1047 + case ETH_SS_STATS:
1048 + for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
1049 + memcpy(data + i * ETH_GSTRING_LEN,
1050 + bcm_enetsw_gstrings_stats[i].stat_string,
1051 + ETH_GSTRING_LEN);
1052 + }
1053 + break;
1054 + }
1055 +}
1056 +
1057 +static int bcm_enetsw_get_sset_count(struct net_device *netdev,
1058 + int string_set)
1059 +{
1060 + switch (string_set) {
1061 + case ETH_SS_STATS:
1062 + return BCM_ENETSW_STATS_LEN;
1063 + default:
1064 + return -EINVAL;
1065 + }
1066 +}
1067 +
1068 +static void bcm_enetsw_get_drvinfo(struct net_device *netdev,
1069 + struct ethtool_drvinfo *drvinfo)
1070 +{
1071 + strncpy(drvinfo->driver, bcm_enet_driver_name, 32);
1072 + strncpy(drvinfo->version, bcm_enet_driver_version, 32);
1073 + strncpy(drvinfo->fw_version, "N/A", 32);
1074 + strncpy(drvinfo->bus_info, "bcm63xx", 32);
1075 + drvinfo->n_stats = BCM_ENETSW_STATS_LEN;
1076 +}
1077 +
1078 +static void bcm_enetsw_get_ethtool_stats(struct net_device *netdev,
1079 + struct ethtool_stats *stats,
1080 + u64 *data)
1081 +{
1082 + struct bcm_enet_priv *priv;
1083 + int i;
1084 +
1085 + priv = netdev_priv(netdev);
1086 +
1087 + for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
1088 + const struct bcm_enet_stats *s;
1089 + u32 lo, hi;
1090 + char *p;
1091 + int reg;
1092 +
1093 + s = &bcm_enetsw_gstrings_stats[i];
1094 +
1095 + reg = s->mib_reg;
1096 + if (reg == -1)
1097 + continue;
1098 +
1099 + lo = enetsw_readl(priv, ENETSW_MIB_REG(reg));
1100 + p = (char *)priv + s->stat_offset;
1101 +
1102 + if (s->sizeof_stat == sizeof(u64)) {
1103 + hi = enetsw_readl(priv, ENETSW_MIB_REG(reg + 1));
1104 + *(u64 *)p = ((u64)hi << 32 | lo);
1105 + } else {
1106 + *(u32 *)p = lo;
1107 + }
1108 + }
1109 +
1110 + for (i = 0; i < BCM_ENETSW_STATS_LEN; i++) {
1111 + const struct bcm_enet_stats *s;
1112 + char *p;
1113 +
1114 + s = &bcm_enetsw_gstrings_stats[i];
1115 +
1116 + if (s->mib_reg == -1)
1117 + p = (char *)&netdev->stats + s->stat_offset;
1118 + else
1119 + p = (char *)priv + s->stat_offset;
1120 +
1121 + data[i] = (s->sizeof_stat == sizeof(u64)) ?
1122 + *(u64 *)p : *(u32 *)p;
1123 + }
1124 +}
1125 +
1126 +static void bcm_enetsw_get_ringparam(struct net_device *dev,
1127 + struct ethtool_ringparam *ering)
1128 +{
1129 + struct bcm_enet_priv *priv;
1130 +
1131 + priv = netdev_priv(dev);
1132 +
1133 + /* rx/tx ring is actually only limited by memory */
1134 + ering->rx_max_pending = 8192;
1135 + ering->tx_max_pending = 8192;
1136 + ering->rx_mini_max_pending = 0;
1137 + ering->rx_jumbo_max_pending = 0;
1138 + ering->rx_pending = priv->rx_ring_size;
1139 + ering->tx_pending = priv->tx_ring_size;
1140 +}
1141 +
1142 +static int bcm_enetsw_set_ringparam(struct net_device *dev,
1143 + struct ethtool_ringparam *ering)
1144 +{
1145 + struct bcm_enet_priv *priv;
1146 + int was_running;
1147 +
1148 + priv = netdev_priv(dev);
1149 +
1150 + was_running = 0;
1151 + if (netif_running(dev)) {
1152 + bcm_enetsw_stop(dev);
1153 + was_running = 1;
1154 + }
1155 +
1156 + priv->rx_ring_size = ering->rx_pending;
1157 + priv->tx_ring_size = ering->tx_pending;
1158 +
1159 + if (was_running) {
1160 + int err;
1161 +
1162 + err = bcm_enetsw_open(dev);
1163 + if (err)
1164 + dev_close(dev);
1165 + }
1166 + return 0;
1167 +}
1168 +
1169 +static struct ethtool_ops bcm_enetsw_ethtool_ops = {
1170 + .get_strings = bcm_enetsw_get_strings,
1171 + .get_sset_count = bcm_enetsw_get_sset_count,
1172 + .get_ethtool_stats = bcm_enetsw_get_ethtool_stats,
1173 + .get_drvinfo = bcm_enetsw_get_drvinfo,
1174 + .get_ringparam = bcm_enetsw_get_ringparam,
1175 + .set_ringparam = bcm_enetsw_set_ringparam,
1176 +};
1177 +
1178 +/* allocate netdevice, request register memory and register device. */
1179 +static int bcm_enetsw_probe(struct platform_device *pdev)
1180 +{
1181 + struct bcm_enet_priv *priv;
1182 + struct net_device *dev;
1183 + struct bcm63xx_enetsw_platform_data *pd;
1184 + struct resource *res_mem;
1185 + int ret, irq_rx, irq_tx;
1186 +
1187 + /* stop if shared driver failed, assume driver->probe will be
1188 + * called in the same order we register devices (correct ?)
1189 + */
1190 + if (!bcm_enet_shared_base[0])
1191 + return -ENODEV;
1192 +
1193 + res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1194 + irq_rx = platform_get_irq(pdev, 0);
1195 + irq_tx = platform_get_irq(pdev, 1);
1196 + if (!res_mem || irq_rx < 0)
1197 + return -ENODEV;
1198 +
1199 + ret = 0;
1200 + dev = alloc_etherdev(sizeof(*priv));
1201 + if (!dev)
1202 + return -ENOMEM;
1203 + priv = netdev_priv(dev);
1204 + memset(priv, 0, sizeof(*priv));
1205 +
1206 + /* initialize default and fetch platform data */
1207 + priv->enet_is_sw = true;
1208 + priv->irq_rx = irq_rx;
1209 + priv->irq_tx = irq_tx;
1210 + priv->rx_ring_size = BCMENET_DEF_RX_DESC;
1211 + priv->tx_ring_size = BCMENET_DEF_TX_DESC;
1212 + priv->dma_maxburst = BCMENETSW_DMA_MAXBURST;
1213 +
1214 + pd = pdev->dev.platform_data;
1215 + if (pd) {
1216 + memcpy(dev->dev_addr, pd->mac_addr, ETH_ALEN);
1217 + memcpy(priv->used_ports, pd->used_ports,
1218 + sizeof(pd->used_ports));
1219 + priv->num_ports = pd->num_ports;
1220 + }
1221 +
1222 + ret = compute_hw_mtu(priv, dev->mtu);
1223 + if (ret)
1224 + goto out;
1225 +
1226 + if (!request_mem_region(res_mem->start, resource_size(res_mem),
1227 + "bcm63xx_enetsw")) {
1228 + ret = -EBUSY;
1229 + goto out;
1230 + }
1231 +
1232 + priv->base = ioremap(res_mem->start, resource_size(res_mem));
1233 + if (priv->base == NULL) {
1234 + ret = -ENOMEM;
1235 + goto out_release_mem;
1236 + }
1237 +
1238 + priv->mac_clk = clk_get(&pdev->dev, "enetsw");
1239 + if (IS_ERR(priv->mac_clk)) {
1240 + ret = PTR_ERR(priv->mac_clk);
1241 + goto out_unmap;
1242 + }
1243 + clk_enable(priv->mac_clk);
1244 +
1245 + priv->rx_chan = 0;
1246 + priv->tx_chan = 1;
1247 + spin_lock_init(&priv->rx_lock);
1248 +
1249 + /* init rx timeout (used for oom) */
1250 + init_timer(&priv->rx_timeout);
1251 + priv->rx_timeout.function = bcm_enet_refill_rx_timer;
1252 + priv->rx_timeout.data = (unsigned long)dev;
1253 +
1254 + /* register netdevice */
1255 + dev->netdev_ops = &bcm_enetsw_ops;
1256 + netif_napi_add(dev, &priv->napi, bcm_enet_poll, 16);
1257 + SET_ETHTOOL_OPS(dev, &bcm_enetsw_ethtool_ops);
1258 + SET_NETDEV_DEV(dev, &pdev->dev);
1259 +
1260 + spin_lock_init(&priv->enetsw_mdio_lock);
1261 +
1262 + ret = register_netdev(dev);
1263 + if (ret)
1264 + goto out_put_clk;
1265 +
1266 + netif_carrier_off(dev);
1267 + platform_set_drvdata(pdev, dev);
1268 + priv->pdev = pdev;
1269 + priv->net_dev = dev;
1270 +
1271 + return 0;
1272 +
1273 +out_put_clk:
1274 + clk_put(priv->mac_clk);
1275 +
1276 +out_unmap:
1277 + iounmap(priv->base);
1278 +
1279 +out_release_mem:
1280 + release_mem_region(res_mem->start, resource_size(res_mem));
1281 +out:
1282 + free_netdev(dev);
1283 + return ret;
1284 +}
1285 +
1286 +
1287 +/* exit func, stops hardware and unregisters netdevice */
1288 +static int bcm_enetsw_remove(struct platform_device *pdev)
1289 +{
1290 + struct bcm_enet_priv *priv;
1291 + struct net_device *dev;
1292 + struct resource *res;
1293 +
1294 + /* stop netdevice */
1295 + dev = platform_get_drvdata(pdev);
1296 + priv = netdev_priv(dev);
1297 + unregister_netdev(dev);
1298 +
1299 + /* release device resources */
1300 + iounmap(priv->base);
1301 + res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1302 + release_mem_region(res->start, resource_size(res));
1303 +
1304 + platform_set_drvdata(pdev, NULL);
1305 + free_netdev(dev);
1306 + return 0;
1307 +}
1308 +
1309 +struct platform_driver bcm63xx_enetsw_driver = {
1310 + .probe = bcm_enetsw_probe,
1311 + .remove = bcm_enetsw_remove,
1312 + .driver = {
1313 + .name = "bcm63xx_enetsw",
1314 + .owner = THIS_MODULE,
1315 + },
1316 +};
1317 +
1318 +/* reserve & remap memory space shared between all macs */
1319 +static int bcm_enet_shared_probe(struct platform_device *pdev)
1320 +{
1321 + struct resource *res;
1322 + void __iomem *p[3];
1323 + unsigned int i;
1324 +
1325 + memset(bcm_enet_shared_base, 0, sizeof(bcm_enet_shared_base));
1326 +
1327 + for (i = 0; i < 3; i++) {
1328 + res = platform_get_resource(pdev, IORESOURCE_MEM, i);
1329 + p[i] = devm_ioremap_resource(&pdev->dev, res);
1330 + if (!p[i])
1331 + return -ENOMEM;
1332 + }
1333 +
1334 + memcpy(bcm_enet_shared_base, p, sizeof(bcm_enet_shared_base));
1335 +
1336 + return 0;
1337 +}
1338 +
1339 +static int bcm_enet_shared_remove(struct platform_device *pdev)
1340 +{
1341 + return 0;
1342 +}
1343 +
1344 +/* this "shared" driver is needed because both macs share a single
1345 + * address space
1346 + */
1347 +struct platform_driver bcm63xx_enet_shared_driver = {
1348 + .probe = bcm_enet_shared_probe,
1349 + .remove = bcm_enet_shared_remove,
1350 + .driver = {
1351 + .name = "bcm63xx_enet_shared",
1352 + .owner = THIS_MODULE,
1353 + },
1354 +};
1355 +
1356 +/* entry point */
1357 +static int __init bcm_enet_init(void)
1358 +{
1359 + int ret;
1360 +
1361 + ret = platform_driver_register(&bcm63xx_enet_shared_driver);
1362 + if (ret)
1363 + return ret;
1364 +
1365 + ret = platform_driver_register(&bcm63xx_enet_driver);
1366 + if (ret)
1367 + platform_driver_unregister(&bcm63xx_enet_shared_driver);
1368 +
1369 + ret = platform_driver_register(&bcm63xx_enetsw_driver);
1370 + if (ret) {
1371 + platform_driver_unregister(&bcm63xx_enet_driver);
1372 + platform_driver_unregister(&bcm63xx_enet_shared_driver);
1373 + }
1374
1375 return ret;
1376 }
1377 @@ -1962,6 +2876,7 @@ static int __init bcm_enet_init(void)
1378 static void __exit bcm_enet_exit(void)
1379 {
1380 platform_driver_unregister(&bcm63xx_enet_driver);
1381 + platform_driver_unregister(&bcm63xx_enetsw_driver);
1382 platform_driver_unregister(&bcm63xx_enet_shared_driver);
1383 }
1384
1385 --- a/drivers/net/ethernet/broadcom/bcm63xx_enet.h
1386 +++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.h
1387 @@ -18,6 +18,7 @@
1388
1389 /* maximum burst len for dma (4 bytes unit) */
1390 #define BCMENET_DMA_MAXBURST 16
1391 +#define BCMENETSW_DMA_MAXBURST 8
1392
1393 /* tx transmit threshold (4 bytes unit), fifo is 256 bytes, the value
1394 * must be low enough so that a DMA transfer of above burst length can
1395 @@ -84,11 +85,60 @@
1396 #define ETH_MIB_RX_CNTRL 54
1397
1398
1399 +/*
1400 + * SW MIB Counters register definitions
1401 +*/
1402 +#define ETHSW_MIB_TX_ALL_OCT 0
1403 +#define ETHSW_MIB_TX_DROP_PKTS 2
1404 +#define ETHSW_MIB_TX_QOS_PKTS 3
1405 +#define ETHSW_MIB_TX_BRDCAST 4
1406 +#define ETHSW_MIB_TX_MULT 5
1407 +#define ETHSW_MIB_TX_UNI 6
1408 +#define ETHSW_MIB_TX_COL 7
1409 +#define ETHSW_MIB_TX_1_COL 8
1410 +#define ETHSW_MIB_TX_M_COL 9
1411 +#define ETHSW_MIB_TX_DEF 10
1412 +#define ETHSW_MIB_TX_LATE 11
1413 +#define ETHSW_MIB_TX_EX_COL 12
1414 +#define ETHSW_MIB_TX_PAUSE 14
1415 +#define ETHSW_MIB_TX_QOS_OCT 15
1416 +
1417 +#define ETHSW_MIB_RX_ALL_OCT 17
1418 +#define ETHSW_MIB_RX_UND 19
1419 +#define ETHSW_MIB_RX_PAUSE 20
1420 +#define ETHSW_MIB_RX_64 21
1421 +#define ETHSW_MIB_RX_65_127 22
1422 +#define ETHSW_MIB_RX_128_255 23
1423 +#define ETHSW_MIB_RX_256_511 24
1424 +#define ETHSW_MIB_RX_512_1023 25
1425 +#define ETHSW_MIB_RX_1024_1522 26
1426 +#define ETHSW_MIB_RX_OVR 27
1427 +#define ETHSW_MIB_RX_JAB 28
1428 +#define ETHSW_MIB_RX_ALIGN 29
1429 +#define ETHSW_MIB_RX_CRC 30
1430 +#define ETHSW_MIB_RX_GD_OCT 31
1431 +#define ETHSW_MIB_RX_DROP 33
1432 +#define ETHSW_MIB_RX_UNI 34
1433 +#define ETHSW_MIB_RX_MULT 35
1434 +#define ETHSW_MIB_RX_BRDCAST 36
1435 +#define ETHSW_MIB_RX_SA_CHANGE 37
1436 +#define ETHSW_MIB_RX_FRAG 38
1437 +#define ETHSW_MIB_RX_OVR_DISC 39
1438 +#define ETHSW_MIB_RX_SYM 40
1439 +#define ETHSW_MIB_RX_QOS_PKTS 41
1440 +#define ETHSW_MIB_RX_QOS_OCT 42
1441 +#define ETHSW_MIB_RX_1523_2047 44
1442 +#define ETHSW_MIB_RX_2048_4095 45
1443 +#define ETHSW_MIB_RX_4096_8191 46
1444 +#define ETHSW_MIB_RX_8192_9728 47
1445 +
1446 +
1447 struct bcm_enet_mib_counters {
1448 u64 tx_gd_octets;
1449 u32 tx_gd_pkts;
1450 u32 tx_all_octets;
1451 u32 tx_all_pkts;
1452 + u32 tx_unicast;
1453 u32 tx_brdcast;
1454 u32 tx_mult;
1455 u32 tx_64;
1456 @@ -97,7 +147,12 @@ struct bcm_enet_mib_counters {
1457 u32 tx_256_511;
1458 u32 tx_512_1023;
1459 u32 tx_1024_max;
1460 + u32 tx_1523_2047;
1461 + u32 tx_2048_4095;
1462 + u32 tx_4096_8191;
1463 + u32 tx_8192_9728;
1464 u32 tx_jab;
1465 + u32 tx_drop;
1466 u32 tx_ovr;
1467 u32 tx_frag;
1468 u32 tx_underrun;
1469 @@ -114,6 +169,7 @@ struct bcm_enet_mib_counters {
1470 u32 rx_all_octets;
1471 u32 rx_all_pkts;
1472 u32 rx_brdcast;
1473 + u32 rx_unicast;
1474 u32 rx_mult;
1475 u32 rx_64;
1476 u32 rx_65_127;
1477 @@ -197,6 +253,9 @@ struct bcm_enet_priv {
1478 /* number of dma desc in tx ring */
1479 int tx_ring_size;
1480
1481 + /* maximum dma burst size */
1482 + int dma_maxburst;
1483 +
1484 /* cpu view of rx dma ring */
1485 struct bcm_enet_desc *tx_desc_cpu;
1486
1487 @@ -269,6 +328,18 @@ struct bcm_enet_priv {
1488
1489 /* maximum hardware transmit/receive size */
1490 unsigned int hw_mtu;
1491 +
1492 + bool enet_is_sw;
1493 +
1494 + /* port mapping for switch devices */
1495 + int num_ports;
1496 + struct bcm63xx_enetsw_port used_ports[ENETSW_MAX_PORT];
1497 + int sw_port_link[ENETSW_MAX_PORT];
1498 +
1499 + /* used to poll switch port state */
1500 + struct timer_list swphy_poll;
1501 + spinlock_t enetsw_mdio_lock;
1502 };
1503
1504 +
1505 #endif /* ! BCM63XX_ENET_H_ */