bcm63xx: add 3.9 support
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-3.9 / 320-MIPS-BCM63XX-wire-up-the-second-CPU-s-irq-line.patch
1 From 1baec3216529f795905b6376f9c8e4f14b114ba2 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Fri, 26 Apr 2013 12:03:15 +0200
4 Subject: [PATCH 11/13] MIPS: BCM63XX: wire up the second CPU's irq line
5
6 It's hardwired to IRQ3, so we don't need to actually check the CPU id.
7
8 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
9 ---
10 arch/mips/bcm63xx/irq.c | 40 ++++++++++++++++++++++++++++++++--------
11 1 file changed, 32 insertions(+), 8 deletions(-)
12
13 --- a/arch/mips/bcm63xx/irq.c
14 +++ b/arch/mips/bcm63xx/irq.c
15 @@ -329,11 +329,15 @@ static void __internal_irq_mask_##width(
16 u32 val; \
17 unsigned reg = (irq / 32) ^ (width/32 - 1); \
18 unsigned bit = irq & 0x1f; \
19 - u32 irq_mask_addr = get_irq_mask_addr(0); \
20 + int cpu; \
21 \
22 - val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
23 - val &= ~(1 << bit); \
24 - bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
25 + for_each_online_cpu(cpu) { \
26 + u32 irq_mask_addr = get_irq_mask_addr(cpu); \
27 + \
28 + val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
29 + val &= ~(1 << bit); \
30 + bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
31 + } \
32 } \
33 \
34 static void __internal_irq_unmask_##width(unsigned int irq) \
35 @@ -341,11 +345,15 @@ static void __internal_irq_unmask_##widt
36 u32 val; \
37 unsigned reg = (irq / 32) ^ (width/32 - 1); \
38 unsigned bit = irq & 0x1f; \
39 - u32 irq_mask_addr = get_irq_mask_addr(0); \
40 + int cpu; \
41 + \
42 + for_each_online_cpu(cpu) { \
43 + u32 irq_mask_addr = get_irq_mask_addr(cpu); \
44 \
45 - val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
46 - val |= (1 << bit); \
47 - bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
48 + val = bcm_readl(irq_mask_addr + reg * sizeof(u32)); \
49 + val |= (1 << bit); \
50 + bcm_writel(val, irq_mask_addr + reg * sizeof(u32)); \
51 + } \
52 }
53
54 BUILD_IPIC_INTERNAL(32);
55 @@ -369,6 +377,10 @@ asmlinkage void plat_irq_dispatch(void)
56 do_IRQ(1);
57 if (cause & CAUSEF_IP2)
58 dispatch_internal(0);
59 +#ifdef CONFIG_SMP
60 + if (cause & CAUSEF_IP3)
61 + dispatch_internal(1);
62 +#else
63 if (!is_ext_irq_cascaded) {
64 if (cause & CAUSEF_IP3)
65 do_IRQ(IRQ_EXT_0);
66 @@ -379,6 +391,7 @@ asmlinkage void plat_irq_dispatch(void)
67 if (cause & CAUSEF_IP6)
68 do_IRQ(IRQ_EXT_3);
69 }
70 +#endif
71 } while (1);
72 }
73
74 @@ -598,6 +611,14 @@ static struct irqaction cpu_ip2_cascade_
75 .flags = IRQF_NO_THREAD,
76 };
77
78 +#ifdef CONFIG_SMP
79 +static struct irqaction cpu_ip3_cascade_action = {
80 + .handler = no_action,
81 + .name = "cascade_ip3",
82 + .flags = IRQF_NO_THREAD,
83 +};
84 +#endif
85 +
86 static struct irqaction cpu_ext_cascade_action = {
87 .handler = no_action,
88 .name = "cascade_extirq",
89 @@ -624,4 +645,7 @@ void __init arch_init_irq(void)
90 }
91
92 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
93 +#ifdef CONFIG_SMP
94 + setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
95 +#endif
96 }