target/linux/brcm63xx/patches-4.1/336-MIPS-BCM63XX-dynamically-set-the-pcie-memory-windows.patch

   1 From aa05464973bc176478af462ca7c53a9239c651d4 Mon Sep 17 00:00:00 2001
   2 From: Jonas Gorski <jogo@openwrt.org>
   3 Date: Sun, 8 Dec 2013 03:13:06 +0100
   4 Subject: [PATCH 46/53] MIPS: BCM63XX: dynamically set the pcie memory windows
   5
   6 Different SoCs use different memory windows (and sizes), so don't
   7 hardcode it.
   8 ---
   9  arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h |  8 ++++----
  10  arch/mips/pci/pci-bcm63xx.c                     | 15 ++++++++++-----
  11  2 files changed, 14 insertions(+), 9 deletions(-)
  12
  13 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
  14 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_io.h
  15 @@ -40,10 +40,10 @@
  16  #define BCM_CB_MEM_END_PA              (BCM_CB_MEM_BASE_PA +           \
  17                                         BCM_CB_MEM_SIZE - 1)
  18
  19 -#define BCM_PCIE_MEM_BASE_PA           0x10f00000
  20 -#define BCM_PCIE_MEM_SIZE              (1 * 1024 * 1024)
  21 -#define BCM_PCIE_MEM_END_PA            (BCM_PCIE_MEM_BASE_PA +         \
  22 -                                       BCM_PCIE_MEM_SIZE - 1)
  23 +#define BCM_PCIE_MEM_BASE_PA_6328      0x10f00000
  24 +#define BCM_PCIE_MEM_SIZE_6328         (1 * 1024 * 1024)
  25 +#define BCM_PCIE_MEM_END_PA_6328       (BCM_PCIE_MEM_BASE_PA_6328 +    \
  26 +                                       BCM_PCIE_MEM_SIZE_6328 - 1)
  27
  28  /*
  29   * Internal registers are accessed through KSEG3
  30 --- a/arch/mips/pci/pci-bcm63xx.c
  31 +++ b/arch/mips/pci/pci-bcm63xx.c
  32 @@ -77,8 +77,8 @@ struct pci_controller bcm63xx_cb_control
  33
  34  static struct resource bcm_pcie_mem_resource = {
  35         .name   = "bcm63xx PCIe memory space",
  36 -       .start  = BCM_PCIE_MEM_BASE_PA,
  37 -       .end    = BCM_PCIE_MEM_END_PA,
  38 +       .start  = 0,
  39 +       .end    = 0,
  40         .flags  = IORESOURCE_MEM,
  41  };
  42
  43 @@ -195,12 +195,12 @@ static int __init bcm63xx_register_pcie(
  44         bcm_pcie_writel(val, PCIE_CONFIG2_REG);
  45
  46         /* set bar0 to little endian */
  47 -       val = (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_BASE_SHIFT;
  48 -       val |= (BCM_PCIE_MEM_BASE_PA >> 20) << BASEMASK_MASK_SHIFT;
  49 +       val = (bcm_pcie_mem_resource.start >> 20) << BASEMASK_BASE_SHIFT;
  50 +       val |= (bcm_pcie_mem_resource.end >> 20) << BASEMASK_MASK_SHIFT;
  51         val |= BASEMASK_REMAP_EN;
  52         bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_BASEMASK_REG);
  53
  54 -       val = (BCM_PCIE_MEM_BASE_PA >> 20) << REBASE_ADDR_BASE_SHIFT;
  55 +       val = (bcm_pcie_mem_resource.start >> 20) << REBASE_ADDR_BASE_SHIFT;
  56         bcm_pcie_writel(val, PCIE_BRIDGE_BAR0_REBASE_ADDR_REG);
  57
  58         register_pci_controller(&bcm63xx_pcie_controller);
  59 @@ -334,6 +334,11 @@ static int __init bcm63xx_pci_init(void)
  60         if (!bcm63xx_pci_enabled)
  61                 return -ENODEV;
  62
  63 +       if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
  64 +               bcm_pcie_mem_resource.start = BCM_PCIE_MEM_BASE_PA_6328;
  65 +               bcm_pcie_mem_resource.end = BCM_PCIE_MEM_END_PA_6328;
  66 +       }
  67 +
  68         switch (bcm63xx_get_cpu_id()) {
  69         case BCM6328_CPU_ID:
  70         case BCM6362_CPU_ID: