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rpcd: iwinfo plugin fixes
[openwrt/svn-archive/archive.git] / target / linux / brcm63xx / patches-4.1 / 339-MIPS-BCM63XX-add-support-for-BCM63268.patch
1 From 98f63141190ac02c58b78d58f771bd263c61d756 Mon Sep 17 00:00:00 2001
2 From: Jonas Gorski <jogo@openwrt.org>
3 Date: Sat, 7 Dec 2013 17:14:17 +0100
4 Subject: [PATCH 48/56] MIPS: BCM63XX: add support for BCM63268
5
6 Signed-off-by: Jonas Gorski <jogo@openwrt.org>
7 ---
8 arch/mips/bcm63xx/Kconfig | 5 +
9 arch/mips/bcm63xx/boards/board_bcm963xx.c | 2 +-
10 arch/mips/bcm63xx/clk.c | 25 ++++-
11 arch/mips/bcm63xx/cpu.c | 59 +++++++++-
12 arch/mips/bcm63xx/dev-flash.c | 6 +
13 arch/mips/bcm63xx/dev-spi.c | 4 +-
14 arch/mips/bcm63xx/irq.c | 20 +++-
15 arch/mips/bcm63xx/reset.c | 21 ++++
16 arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h | 130 ++++++++++++++++++++++
17 arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h | 2 +
18 arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 79 +++++++++++++
19 arch/mips/include/asm/mach-bcm63xx/ioremap.h | 1 +
20 12 files changed, 342 insertions(+), 12 deletions(-)
21
22 --- a/arch/mips/bcm63xx/Kconfig
23 +++ b/arch/mips/bcm63xx/Kconfig
24 @@ -60,6 +60,11 @@ config BCM63XX_CPU_6368
25 select HW_HAS_PCI
26 select BCM63XX_OHCI
27 select BCM63XX_EHCI
28 +
29 +config BCM63XX_CPU_63268
30 + bool "support 63268 CPU"
31 + select SYS_HAS_CPU_BMIPS4350
32 + select HW_HAS_PCI
33 endmenu
34
35 source "arch/mips/bcm63xx/boards/Kconfig"
36 --- a/arch/mips/bcm63xx/boards/board_bcm963xx.c
37 +++ b/arch/mips/bcm63xx/boards/board_bcm963xx.c
38 @@ -712,7 +712,7 @@ void __init board_prom_init(void)
39 /* read base address of boot chip select (0)
40 * 6328/6362 do not have MPI but boot from a fixed address
41 */
42 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362()) {
43 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) {
44 val = 0x18000000;
45 } else {
46 val = bcm_mpi_readl(MPI_CSBASE_REG(0));
47 --- a/arch/mips/bcm63xx/clk.c
48 +++ b/arch/mips/bcm63xx/clk.c
49 @@ -133,6 +133,8 @@ static void enetsw_set(struct clk *clk,
50 CKCTL_6368_SWPKT_USB_EN |
51 CKCTL_6368_SWPKT_SAR_EN,
52 enable);
53 + else if (BCMCPU_IS_63268())
54 + bcm_hwclock_set(CKCTL_63268_ROBOSW_EN, enable);
55 else
56 return;
57
58 @@ -177,6 +179,8 @@ static void usbh_set(struct clk *clk, in
59 bcm_hwclock_set(CKCTL_6362_USBH_EN, enable);
60 else if (BCMCPU_IS_6368())
61 bcm_hwclock_set(CKCTL_6368_USBH_EN, enable);
62 + else if (BCMCPU_IS_63268())
63 + bcm_hwclock_set(CKCTL_63268_USBH_EN, enable);
64 else
65 return;
66
67 @@ -199,6 +203,8 @@ static void usbd_set(struct clk *clk, in
68 bcm_hwclock_set(CKCTL_6362_USBD_EN, enable);
69 else if (BCMCPU_IS_6368())
70 bcm_hwclock_set(CKCTL_6368_USBD_EN, enable);
71 + else if (BCMCPU_IS_63268())
72 + bcm_hwclock_set(CKCTL_63268_USBD_EN, enable);
73 else
74 return;
75
76 @@ -225,9 +231,13 @@ static void spi_set(struct clk *clk, int
77 mask = CKCTL_6358_SPI_EN;
78 else if (BCMCPU_IS_6362())
79 mask = CKCTL_6362_SPI_EN;
80 - else
81 - /* BCMCPU_IS_6368 */
82 + else if (BCMCPU_IS_6368())
83 mask = CKCTL_6368_SPI_EN;
84 + else if (BCMCPU_IS_63268())
85 + mask = CKCTL_63268_SPI_EN;
86 + else
87 + return;
88 +
89 bcm_hwclock_set(mask, enable);
90 }
91
92 @@ -246,6 +256,8 @@ static void hsspi_set(struct clk *clk, i
93 mask = CKCTL_6328_HSSPI_EN;
94 else if (BCMCPU_IS_6362())
95 mask = CKCTL_6362_HSSPI_EN;
96 + else if (BCMCPU_IS_63268())
97 + mask = CKCTL_63268_HSSPI_EN;
98 else
99 return;
100
101 @@ -307,6 +319,8 @@ static void pcie_set(struct clk *clk, in
102 bcm_hwclock_set(CKCTL_6328_PCIE_EN, enable);
103 else if (BCMCPU_IS_6362())
104 bcm_hwclock_set(CKCTL_6362_PCIE_EN, enable);
105 + else if (BCMCPU_IS_63268())
106 + bcm_hwclock_set(CKCTL_63268_PCIE_EN, enable);
107 }
108
109 static struct clk clk_pcie = {
110 @@ -386,9 +400,11 @@ struct clk *clk_get(struct device *dev,
111 return &clk_periph;
112 if ((BCMCPU_IS_3368() || BCMCPU_IS_6358()) && !strcmp(id, "pcm"))
113 return &clk_pcm;
114 - if ((BCMCPU_IS_6362() || BCMCPU_IS_6368()) && !strcmp(id, "ipsec"))
115 + if ((BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268()) &&
116 + !strcmp(id, "ipsec"))
117 return &clk_ipsec;
118 - if ((BCMCPU_IS_6328() || BCMCPU_IS_6362()) && !strcmp(id, "pcie"))
119 + if ((BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268()) &&
120 + !strcmp(id, "pcie"))
121 return &clk_pcie;
122 return ERR_PTR(-ENOENT);
123 }
124 @@ -411,6 +427,7 @@ static int __init bcm63xx_clk_init(void)
125 clk_hsspi.rate = HSSPI_PLL_HZ_6328;
126 break;
127 case BCM6362_CPU_ID:
128 + case BCM63268_CPU_ID:
129 clk_hsspi.rate = HSSPI_PLL_HZ_6362;
130 break;
131 }
132 --- a/arch/mips/bcm63xx/cpu.c
133 +++ b/arch/mips/bcm63xx/cpu.c
134 @@ -101,6 +101,15 @@ static const int bcm6368_irqs[] = {
135
136 };
137
138 +static const unsigned long bcm63268_regs_base[] = {
139 + __GEN_CPU_REGS_TABLE(63268)
140 +};
141 +
142 +static const int bcm63268_irqs[] = {
143 + __GEN_CPU_IRQ_TABLE(63268)
144 +
145 +};
146 +
147 u32 bcm63xx_get_cpu_variant(void)
148 {
149 return bcm63xx_cpu_variant;
150 @@ -253,6 +262,27 @@ static unsigned int detect_cpu_clock(voi
151
152 return (((64 * 1000000) / p1) * p2 * ndiv) / m1;
153 }
154 + case BCM63268_CPU_ID:
155 + {
156 + unsigned int tmp, mips_pll_fcvo;
157 +
158 + tmp = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
159 + mips_pll_fcvo = (tmp & STRAPBUS_63268_FCVO_MASK) >>
160 + STRAPBUS_63268_FCVO_SHIFT;
161 + switch (mips_pll_fcvo) {
162 + case 0x3:
163 + case 0xe:
164 + return 320000000;
165 + case 0xa:
166 + return 333000000;
167 + case 0x2:
168 + case 0xb:
169 + case 0xf:
170 + return 400000000;
171 + default:
172 + return 0;
173 + }
174 + }
175
176 default:
177 panic("Failed to detect clock for CPU with id=%04X\n", cpu_id);
178 @@ -267,7 +297,7 @@ static unsigned int detect_memory_size(v
179 unsigned int cols = 0, rows = 0, is_32bits = 0, banks = 0;
180 u32 val;
181
182 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362())
183 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_63268())
184 return bcm_ddr_readl(DDR_CSEND_REG) << 24;
185
186 if (BCMCPU_IS_6345()) {
187 @@ -305,6 +335,7 @@ void __init bcm63xx_cpu_init(void)
188 unsigned int tmp;
189 unsigned int cpu = smp_processor_id();
190 u32 chipid_reg;
191 + bool long_chipid = false;
192 u8 __maybe_unused varid = 0;
193
194 /* soc registers location depends on cpu type */
195 @@ -326,6 +357,9 @@ void __init bcm63xx_cpu_init(void)
196 case 0x10:
197 chipid_reg = BCM_6345_PERF_BASE;
198 break;
199 + case 0x80:
200 + long_chipid = true;
201 + /* fall-through */
202 default:
203 chipid_reg = BCM_6368_PERF_BASE;
204 break;
205 @@ -333,6 +367,7 @@ void __init bcm63xx_cpu_init(void)
206 break;
207 }
208
209 +
210 /*
211 * really early to panic, but delaying panic would not help since we
212 * will never get any working console
213 @@ -342,10 +377,17 @@ void __init bcm63xx_cpu_init(void)
214
215 /* read out CPU type */
216 tmp = bcm_readl(chipid_reg);
217 - bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
218 - bcm63xx_cpu_variant = bcm63xx_cpu_id;
219 +
220 + if (long_chipid) {
221 + bcm63xx_cpu_id = tmp & REV_LONG_CHIPID_MASK;
222 + bcm63xx_cpu_id >>= REV_LONG_CHIPID_SHIFT;
223 + } else {
224 + bcm63xx_cpu_id = (tmp & REV_CHIPID_MASK) >> REV_CHIPID_SHIFT;
225 + varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
226 + }
227 +
228 bcm63xx_cpu_rev = (tmp & REV_REVID_MASK) >> REV_REVID_SHIFT;
229 - varid = (tmp & REV_VARID_MASK) >> REV_VARID_SHIFT;
230 + bcm63xx_cpu_variant = bcm63xx_cpu_id;
231
232 switch (bcm63xx_cpu_id) {
233 case BCM3368_CPU_ID:
234 @@ -400,6 +442,15 @@ void __init bcm63xx_cpu_init(void)
235 /* BCM6369 is a BCM6368 without xDSL, so treat it the same */
236 bcm63xx_cpu_id = BCM6368_CPU_ID;
237 break;
238 + case BCM63168_CPU_ID:
239 + case BCM63169_CPU_ID:
240 + case BCM63268_CPU_ID:
241 + case BCM63269_CPU_ID:
242 + bcm63xx_regs_base = bcm63268_regs_base;
243 + bcm63xx_irqs = bcm63268_irqs;
244 +
245 + bcm63xx_cpu_id = BCM63268_CPU_ID;
246 + break;
247 default:
248 panic("unsupported broadcom CPU %x", bcm63xx_cpu_id);
249 break;
250 --- a/arch/mips/bcm63xx/dev-flash.c
251 +++ b/arch/mips/bcm63xx/dev-flash.c
252 @@ -94,6 +94,12 @@ static int __init bcm63xx_detect_flash_t
253 case STRAPBUS_6368_BOOT_SEL_PARALLEL:
254 return BCM63XX_FLASH_TYPE_PARALLEL;
255 }
256 + case BCM63268_CPU_ID:
257 + val = bcm_misc_readl(MISC_STRAPBUS_63268_REG);
258 + if (val & STRAPBUS_63268_BOOT_SEL_SERIAL)
259 + return BCM63XX_FLASH_TYPE_SERIAL;
260 + else
261 + return BCM63XX_FLASH_TYPE_NAND;
262 default:
263 return -EINVAL;
264 }
265 --- a/arch/mips/bcm63xx/dev-spi.c
266 +++ b/arch/mips/bcm63xx/dev-spi.c
267 @@ -37,7 +37,7 @@ static __init void bcm63xx_spi_regs_init
268 if (BCMCPU_IS_6338() || BCMCPU_IS_6348())
269 bcm63xx_regs_spi = bcm6348_regs_spi;
270 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() ||
271 - BCMCPU_IS_6362() || BCMCPU_IS_6368())
272 + BCMCPU_IS_6362() || BCMCPU_IS_6368() || BCMCPU_IS_63268())
273 bcm63xx_regs_spi = bcm6358_regs_spi;
274 }
275
276 @@ -85,7 +85,7 @@ int __init bcm63xx_spi_register(void)
277 }
278
279 if (BCMCPU_IS_3368() || BCMCPU_IS_6358() || BCMCPU_IS_6362() ||
280 - BCMCPU_IS_6368()) {
281 + BCMCPU_IS_6368() || BCMCPU_IS_63268()) {
282 spi_resources[0].end += BCM_6358_RSET_SPI_SIZE - 1;
283 spi_pdata.fifo_size = SPI_6358_MSG_DATA_SIZE;
284 spi_pdata.msg_type_shift = SPI_6358_MSG_TYPE_SHIFT;
285 --- a/arch/mips/bcm63xx/irq.c
286 +++ b/arch/mips/bcm63xx/irq.c
287 @@ -150,6 +150,20 @@ void __init arch_init_irq(void)
288 ext_irqs[5] = BCM_6368_EXT_IRQ5;
289 ext_shift = 4;
290 break;
291 + case BCM63268_CPU_ID:
292 + periph_bases[0] += PERF_IRQMASK_63268_REG(0);
293 + periph_bases[1] += PERF_IRQMASK_63268_REG(1);
294 + periph_irq_count = 2;
295 + periph_width = 4;
296 +
297 + ext_intc_bases[0] += PERF_EXTIRQ_CFG_REG_63268;
298 + ext_irq_count = 4;
299 + ext_irqs[0] = BCM_63268_EXT_IRQ0;
300 + ext_irqs[1] = BCM_63268_EXT_IRQ1;
301 + ext_irqs[2] = BCM_63268_EXT_IRQ2;
302 + ext_irqs[3] = BCM_63268_EXT_IRQ3;
303 + ext_shift = 4;
304 + break;
305 default:
306 BUG();
307 }
308 --- a/arch/mips/bcm63xx/reset.c
309 +++ b/arch/mips/bcm63xx/reset.c
310 @@ -125,6 +125,20 @@
311 #define BCM6368_RESET_PCIE 0
312 #define BCM6368_RESET_PCIE_EXT 0
313
314 +#define BCM63268_RESET_SPI SOFTRESET_63268_SPI_MASK
315 +#define BCM63268_RESET_ENET 0
316 +#define BCM63268_RESET_USBH SOFTRESET_63268_USBH_MASK
317 +#define BCM63268_RESET_USBD SOFTRESET_63268_USBS_MASK
318 +#define BCM63268_RESET_DSL 0
319 +#define BCM63268_RESET_SAR SOFTRESET_63268_SAR_MASK
320 +#define BCM63268_RESET_EPHY 0
321 +#define BCM63268_RESET_ENETSW SOFTRESET_63268_ENETSW_MASK
322 +#define BCM63268_RESET_PCM SOFTRESET_63268_PCM_MASK
323 +#define BCM63268_RESET_MPI 0
324 +#define BCM63268_RESET_PCIE (SOFTRESET_63268_PCIE_MASK | \
325 + SOFTRESET_63268_PCIE_CORE_MASK)
326 +#define BCM63268_RESET_PCIE_EXT SOFTRESET_63268_PCIE_EXT_MASK
327 +
328 /*
329 * core reset bits
330 */
331 @@ -156,6 +170,10 @@ static const u32 bcm6368_reset_bits[] =
332 __GEN_RESET_BITS_TABLE(6368)
333 };
334
335 +static const u32 bcm63268_reset_bits[] = {
336 + __GEN_RESET_BITS_TABLE(63268)
337 +};
338 +
339 const u32 *bcm63xx_reset_bits;
340 static int reset_reg;
341
342 @@ -182,6 +200,9 @@ static int __init bcm63xx_reset_bits_ini
343 } else if (BCMCPU_IS_6368()) {
344 reset_reg = PERF_SOFTRESET_6368_REG;
345 bcm63xx_reset_bits = bcm6368_reset_bits;
346 + } else if (BCMCPU_IS_63268()) {
347 + reset_reg = PERF_SOFTRESET_63268_REG;
348 + bcm63xx_reset_bits = bcm63268_reset_bits;
349 }
350
351 return 0;
352 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
353 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_cpu.h
354 @@ -21,6 +21,10 @@
355 #define BCM6362_CPU_ID 0x6362
356 #define BCM6368_CPU_ID 0x6368
357 #define BCM6369_CPU_ID 0x6369
358 +#define BCM63168_CPU_ID 0x63168
359 +#define BCM63169_CPU_ID 0x63169
360 +#define BCM63268_CPU_ID 0x63268
361 +#define BCM63269_CPU_ID 0x63269
362
363 void __init bcm63xx_cpu_init(void);
364 u32 bcm63xx_get_cpu_variant(void);
365 @@ -61,6 +65,10 @@ static inline u32 __pure __bcm63xx_get_c
366 #ifdef CONFIG_BCM63XX_CPU_6368
367 case BCM6368_CPU_ID:
368 #endif
369 +
370 +#ifdef CONFIG_BCM63XX_CPU_63268
371 + case BCM63268_CPU_ID:
372 +#endif
373 break;
374 default:
375 unreachable();
376 @@ -86,6 +94,7 @@ static inline u32 __pure bcm63xx_get_cpu
377 #define BCMCPU_IS_6358() (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
378 #define BCMCPU_IS_6362() (bcm63xx_get_cpu_id() == BCM6362_CPU_ID)
379 #define BCMCPU_IS_6368() (bcm63xx_get_cpu_id() == BCM6368_CPU_ID)
380 +#define BCMCPU_IS_63268() (bcm63xx_get_cpu_id() == BCM63268_CPU_ID)
381
382 #define BCMCPU_VARIANT_IS_3368() \
383 (bcm63xx_get_cpu_variant() == BCM3368_CPU_ID)
384 @@ -109,6 +118,14 @@ static inline u32 __pure bcm63xx_get_cpu
385 (bcm63xx_get_cpu_variant() == BCM6368_CPU_ID)
386 #define BCMCPU_VARIANT_IS_6369() \
387 (bcm63xx_get_cpu_variant() == BCM6369_CPU_ID)
388 +#define BCMCPU_VARIANT_IS_63168() \
389 + (bcm63xx_get_cpu_variant() == BCM63168_CPU_ID)
390 +#define BCMCPU_VARIANT_IS_63169() \
391 + (bcm63xx_get_cpu_variant() == BCM63169_CPU_ID)
392 +#define BCMCPU_VARIANT_IS_63268() \
393 + (bcm63xx_get_cpu_variant() == BCM63268_CPU_ID)
394 +#define BCMCPU_VARIANT_IS_63269() \
395 + (bcm63xx_get_cpu_variant() == BCM63269_CPU_ID)
396
397 /*
398 * While registers sets are (mostly) the same across 63xx CPU, base
399 @@ -573,6 +590,52 @@ enum bcm63xx_regs_set {
400 #define BCM_6368_RNG_BASE (0xb0004180)
401 #define BCM_6368_MISC_BASE (0xdeadbeef)
402
403 +/*
404 + * 63268 register sets base address
405 + */
406 +#define BCM_63268_DSL_LMEM_BASE (0xdeadbeef)
407 +#define BCM_63268_PERF_BASE (0xb0000000)
408 +#define BCM_63268_TIMER_BASE (0xb0000080)
409 +#define BCM_63268_WDT_BASE (0xb000009c)
410 +#define BCM_63268_UART0_BASE (0xb0000180)
411 +#define BCM_63268_UART1_BASE (0xb00001a0)
412 +#define BCM_63268_GPIO_BASE (0xb00000c0)
413 +#define BCM_63268_SPI_BASE (0xb0000800)
414 +#define BCM_63268_HSSPI_BASE (0xb0001000)
415 +#define BCM_63268_UDC0_BASE (0xdeadbeef)
416 +#define BCM_63268_USBDMA_BASE (0xb000c800)
417 +#define BCM_63268_OHCI0_BASE (0xb0002600)
418 +#define BCM_63268_OHCI_PRIV_BASE (0xdeadbeef)
419 +#define BCM_63268_USBH_PRIV_BASE (0xb0002700)
420 +#define BCM_63268_USBD_BASE (0xb0002400)
421 +#define BCM_63268_MPI_BASE (0xdeadbeef)
422 +#define BCM_63268_PCMCIA_BASE (0xdeadbeef)
423 +#define BCM_63268_PCIE_BASE (0xb06e0000)
424 +#define BCM_63268_SDRAM_REGS_BASE (0xdeadbeef)
425 +#define BCM_63268_DSL_BASE (0xdeadbeef)
426 +#define BCM_63268_UBUS_BASE (0xdeadbeef)
427 +#define BCM_63268_ENET0_BASE (0xdeadbeef)
428 +#define BCM_63268_ENET1_BASE (0xdeadbeef)
429 +#define BCM_63268_ENETDMA_BASE (0xb000d800)
430 +#define BCM_63268_ENETDMAC_BASE (0xb000da00)
431 +#define BCM_63268_ENETDMAS_BASE (0xb000dc00)
432 +#define BCM_63268_ENETSW_BASE (0xb0700000)
433 +#define BCM_63268_EHCI0_BASE (0xb0002500)
434 +#define BCM_63268_SDRAM_BASE (0xdeadbeef)
435 +#define BCM_63268_MEMC_BASE (0xdeadbeef)
436 +#define BCM_63268_DDR_BASE (0xb0003000)
437 +#define BCM_63268_M2M_BASE (0xdeadbeef)
438 +#define BCM_63268_ATM_BASE (0xdeadbeef)
439 +#define BCM_63268_XTM_BASE (0xb0007000)
440 +#define BCM_63268_XTMDMA_BASE (0xb000b800)
441 +#define BCM_63268_XTMDMAC_BASE (0xdeadbeef)
442 +#define BCM_63268_XTMDMAS_BASE (0xdeadbeef)
443 +#define BCM_63268_PCM_BASE (0xb000b000)
444 +#define BCM_63268_PCMDMA_BASE (0xb000b800)
445 +#define BCM_63268_PCMDMAC_BASE (0xdeadbeef)
446 +#define BCM_63268_PCMDMAS_BASE (0xdeadbeef)
447 +#define BCM_63268_RNG_BASE (0xdeadbeef)
448 +#define BCM_63268_MISC_BASE (0xb0001800)
449
450 extern const unsigned long *bcm63xx_regs_base;
451
452 @@ -1041,6 +1104,73 @@ enum bcm63xx_irq {
453 #define BCM_6368_EXT_IRQ4 (IRQ_INTERNAL_BASE + 24)
454 #define BCM_6368_EXT_IRQ5 (IRQ_INTERNAL_BASE + 25)
455
456 +/*
457 + * 63268 irqs
458 + */
459 +#define BCM_63268_HIGH_IRQ_BASE (IRQ_INTERNAL_BASE + 32)
460 +#define BCM_63268_VERY_HIGH_IRQ_BASE (BCM_63268_HIGH_IRQ_BASE + 32)
461 +
462 +#define BCM_63268_TIMER_IRQ (IRQ_INTERNAL_BASE + 0)
463 +#define BCM_63268_SPI_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 16)
464 +#define BCM_63268_UART0_IRQ (IRQ_INTERNAL_BASE + 5)
465 +#define BCM_63268_UART1_IRQ (BCM_63268_HIGH_IRQ_BASE + 2)
466 +#define BCM_63268_DSL_IRQ (IRQ_INTERNAL_BASE + 23)
467 +#define BCM_63268_UDC0_IRQ 0
468 +#define BCM_63268_ENET0_IRQ 0
469 +#define BCM_63268_ENET1_IRQ 0
470 +#define BCM_63268_ENET_PHY_IRQ (IRQ_INTERNAL_BASE + 13)
471 +#define BCM_63268_HSSPI_IRQ (IRQ_INTERNAL_BASE + 6)
472 +#define BCM_63268_OHCI0_IRQ (IRQ_INTERNAL_BASE + 9)
473 +#define BCM_63268_EHCI0_IRQ (IRQ_INTERNAL_BASE + 10)
474 +#define BCM_63268_USBD_IRQ (IRQ_INTERNAL_BASE + 11)
475 +#define BCM_63268_USBD_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 19)
476 +#define BCM_63268_USBD_TXDMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 4)
477 +#define BCM_63268_USBD_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 20)
478 +#define BCM_63268_USBD_TXDMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 5)
479 +#define BCM_63268_USBD_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 21)
480 +#define BCM_63268_USBD_TXDMA2_IRQ (BCM_63268_HIGH_IRQ_BASE + 6)
481 +#define BCM_63268_PCMCIA_IRQ 0
482 +#define BCM_63268_ENET0_RXDMA_IRQ 0
483 +#define BCM_63268_ENET0_TXDMA_IRQ 0
484 +#define BCM_63268_ENET1_RXDMA_IRQ 0
485 +#define BCM_63268_ENET1_TXDMA_IRQ 0
486 +#define BCM_63268_PCI_IRQ (BCM_63268_HIGH_IRQ_BASE + 8)
487 +#define BCM_63268_ATM_IRQ 0
488 +#define BCM_63268_ENETSW_RXDMA0_IRQ (IRQ_INTERNAL_BASE + 1)
489 +#define BCM_63268_ENETSW_RXDMA1_IRQ (IRQ_INTERNAL_BASE + 2)
490 +#define BCM_63268_ENETSW_RXDMA2_IRQ (IRQ_INTERNAL_BASE + 3)
491 +#define BCM_63268_ENETSW_RXDMA3_IRQ (IRQ_INTERNAL_BASE + 4)
492 +#define BCM_63268_ENETSW_TXDMA0_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 0)
493 +#define BCM_63268_ENETSW_TXDMA1_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 1)
494 +#define BCM_63268_ENETSW_TXDMA2_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 2)
495 +#define BCM_63268_ENETSW_TXDMA3_IRQ (BCM_63268_VERY_HIGH_IRQ_BASE + 3)
496 +#define BCM_63268_XTM_IRQ (BCM_63268_HIGH_IRQ_BASE + 17)
497 +#define BCM_63268_XTM_DMA0_IRQ (IRQ_INTERNAL_BASE + 26)
498 +
499 +#define BCM_63268_RING_OSC_IRQ (BCM_63268_HIGH_IRQ_BASE + 20)
500 +#define BCM_63268_WLAN_GPIO_IRQ (BCM_63268_HIGH_IRQ_BASE + 3)
501 +#define BCM_63268_WLAN_IRQ (IRQ_INTERNAL_BASE + 7)
502 +#define BCM_63268_IPSEC_IRQ (IRQ_INTERNAL_BASE + 8)
503 +#define BCM_63268_NAND_IRQ (BCM_63268_HIGH_IRQ_BASE + 18)
504 +#define BCM_63268_PCM_IRQ (IRQ_INTERNAL_BASE + 13)
505 +#define BCM_63268_DG_IRQ (IRQ_INTERNAL_BASE + 15)
506 +#define BCM_63268_EPHY_ENERGY0_IRQ (IRQ_INTERNAL_BASE + 16)
507 +#define BCM_63268_EPHY_ENERGY1_IRQ (IRQ_INTERNAL_BASE + 17)
508 +#define BCM_63268_EPHY_ENERGY2_IRQ (IRQ_INTERNAL_BASE + 18)
509 +#define BCM_63268_EPHY_ENERGY3_IRQ (IRQ_INTERNAL_BASE + 19)
510 +#define BCM_63268_IPSEC_DMA0_IRQ (IRQ_INTERNAL_BASE + 22)
511 +#define BCM_63268_IPSEC_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 7)
512 +#define BCM_63268_FAP0_IRQ (IRQ_INTERNAL_BASE + 24)
513 +#define BCM_63268_FAP1_IRQ (IRQ_INTERNAL_BASE + 25)
514 +#define BCM_63268_PCM_DMA0_IRQ (BCM_63268_HIGH_IRQ_BASE + 10)
515 +#define BCM_63268_PCM_DMA1_IRQ (BCM_63268_HIGH_IRQ_BASE + 11)
516 +#define BCM_63268_DECT0_IRQ (BCM_63268_HIGH_IRQ_BASE + 0)
517 +#define BCM_63268_DECT1_IRQ (BCM_63268_HIGH_IRQ_BASE + 1)
518 +#define BCM_63268_EXT_IRQ0 (BCM_63268_HIGH_IRQ_BASE + 12)
519 +#define BCM_63268_EXT_IRQ1 (BCM_63268_HIGH_IRQ_BASE + 13)
520 +#define BCM_63268_EXT_IRQ2 (BCM_63268_HIGH_IRQ_BASE + 14)
521 +#define BCM_63268_EXT_IRQ3 (BCM_63268_HIGH_IRQ_BASE + 15)
522 +
523 extern const int *bcm63xx_irqs;
524
525 #define __GEN_CPU_IRQ_TABLE(__cpu) \
526 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
527 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_gpio.h
528 @@ -22,6 +22,8 @@ static inline unsigned long bcm63xx_gpio
529 return 48;
530 case BCM6368_CPU_ID:
531 return 38;
532 + case BCM63268_CPU_ID:
533 + return 52;
534 case BCM6348_CPU_ID:
535 default:
536 return 37;
537 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
538 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
539 @@ -9,6 +9,8 @@
540 #define PERF_REV_REG 0x0
541 #define REV_CHIPID_SHIFT 16
542 #define REV_CHIPID_MASK (0xffff << REV_CHIPID_SHIFT)
543 +#define REV_LONG_CHIPID_SHIFT 12
544 +#define REV_LONG_CHIPID_MASK (0xfffff << REV_LONG_CHIPID_SHIFT)
545 #define REV_VARID_SHIFT 12
546 #define REV_VARID_MASK (0xf << REV_VARID_SHIFT)
547 #define REV_REVID_SHIFT 0
548 @@ -211,6 +213,52 @@
549 CKCTL_6368_NAND_EN | \
550 CKCTL_6368_IPSEC_EN)
551
552 +#define CKCTL_63268_DISABLE_GLESS (1 << 0)
553 +#define CKCTL_63268_VDSL_QPROC_EN (1 << 1)
554 +#define CKCTL_63268_VDSL_AFE_EN (1 << 2)
555 +#define CKCTL_63268_VDSL_EN (1 << 3)
556 +#define CKCTL_63268_MIPS_EN (1 << 4)
557 +#define CKCTL_63268_WLAN_OCP_EN (1 << 5)
558 +#define CKCTL_63268_DECT_EN (1 << 6)
559 +#define CKCTL_63268_FAP0_EN (1 << 7)
560 +#define CKCTL_63268_FAP1_EN (1 << 8)
561 +#define CKCTL_63268_SAR_EN (1 << 9)
562 +#define CKCTL_63268_ROBOSW_EN (1 << 10)
563 +#define CKCTL_63268_PCM_EN (1 << 11)
564 +#define CKCTL_63268_USBD_EN (1 << 12)
565 +#define CKCTL_63268_USBH_EN (1 << 13)
566 +#define CKCTL_63268_IPSEC_EN (1 << 14)
567 +#define CKCTL_63268_SPI_EN (1 << 15)
568 +#define CKCTL_63268_HSSPI_EN (1 << 16)
569 +#define CKCTL_63268_PCIE_EN (1 << 17)
570 +#define CKCTL_63268_PHYMIPS_EN (1 << 18)
571 +#define CKCTL_63268_GMAC_EN (1 << 19)
572 +#define CKCTL_63268_NAND_EN (1 << 20)
573 +#define CKCTL_63268_TBUS_EN (1 << 27)
574 +#define CKCTL_63268_ROBOSW250_EN (1 << 31)
575 +
576 +#define CKCTL_63268_ALL_SAFE_EN (CKCTL_63268_VDSL_QPROC_EN | \
577 + CKCTL_63268_VDSL_AFE_EN | \
578 + CKCTL_63268_VDSL_EN | \
579 + CKCTL_63268_WLAN_OCP_EN | \
580 + CKCTL_63268_DECT_EN | \
581 + CKCTL_63268_FAP0_EN | \
582 + CKCTL_63268_FAP1_EN | \
583 + CKCTL_63268_SAR_EN | \
584 + CKCTL_63268_ROBOSW_EN | \
585 + CKCTL_63268_PCM_EN | \
586 + CKCTL_63268_USBD_EN | \
587 + CKCTL_63268_USBH_EN | \
588 + CKCTL_63268_IPSEC_EN | \
589 + CKCTL_63268_SPI_EN | \
590 + CKCTL_63268_HSSPI_EN | \
591 + CKCTL_63268_PCIE_EN | \
592 + CKCTL_63268_PHYMIPS_EN | \
593 + CKCTL_63268_GMAC_EN | \
594 + CKCTL_63268_NAND_EN | \
595 + CKCTL_63268_TBUS_EN | \
596 + CKCTL_63268_ROBOSW250_EN)
597 +
598 /* System PLL Control register */
599 #define PERF_SYS_PLL_CTL_REG 0x8
600 #define SYS_PLL_SOFT_RESET 0x1
601 @@ -224,6 +272,7 @@
602 #define PERF_IRQMASK_6358_REG(x) (0xc + (x) * 0x2c)
603 #define PERF_IRQMASK_6362_REG(x) (0x20 + (x) * 0x10)
604 #define PERF_IRQMASK_6368_REG(x) (0x20 + (x) * 0x10)
605 +#define PERF_IRQMASK_63268_REG(x) (0x20 + (x) * 0x20)
606
607 /* Interrupt Status register */
608 #define PERF_IRQSTAT_3368_REG 0x10
609 @@ -234,6 +283,7 @@
610 #define PERF_IRQSTAT_6358_REG(x) (0x10 + (x) * 0x2c)
611 #define PERF_IRQSTAT_6362_REG(x) (0x28 + (x) * 0x10)
612 #define PERF_IRQSTAT_6368_REG(x) (0x28 + (x) * 0x10)
613 +#define PERF_IRQSTAT_63268_REG(x) (0x30 + (x) * 0x20)
614
615 /* External Interrupt Configuration register */
616 #define PERF_EXTIRQ_CFG_REG_3368 0x14
617 @@ -244,6 +294,7 @@
618 #define PERF_EXTIRQ_CFG_REG_6358 0x14
619 #define PERF_EXTIRQ_CFG_REG_6362 0x18
620 #define PERF_EXTIRQ_CFG_REG_6368 0x18
621 +#define PERF_EXTIRQ_CFG_REG_63268 0x18
622
623 #define PERF_EXTIRQ_CFG_REG2_6358 0x1c
624 #define PERF_EXTIRQ_CFG_REG2_6368 0x1c
625 @@ -274,6 +325,7 @@
626 #define PERF_SOFTRESET_6358_REG 0x34
627 #define PERF_SOFTRESET_6362_REG 0x10
628 #define PERF_SOFTRESET_6368_REG 0x10
629 +#define PERF_SOFTRESET_63268_REG 0x10
630
631 #define SOFTRESET_3368_SPI_MASK (1 << 0)
632 #define SOFTRESET_3368_ENET_MASK (1 << 2)
633 @@ -367,6 +419,26 @@
634 #define SOFTRESET_6368_USBH_MASK (1 << 12)
635 #define SOFTRESET_6368_PCM_MASK (1 << 13)
636
637 +#define SOFTRESET_63268_SPI_MASK (1 << 0)
638 +#define SOFTRESET_63268_IPSEC_MASK (1 << 1)
639 +#define SOFTRESET_63268_EPHY_MASK (1 << 2)
640 +#define SOFTRESET_63268_SAR_MASK (1 << 3)
641 +#define SOFTRESET_63268_ENETSW_MASK (1 << 4)
642 +#define SOFTRESET_63268_USBS_MASK (1 << 5)
643 +#define SOFTRESET_63268_USBH_MASK (1 << 6)
644 +#define SOFTRESET_63268_PCM_MASK (1 << 7)
645 +#define SOFTRESET_63268_PCIE_CORE_MASK (1 << 8)
646 +#define SOFTRESET_63268_PCIE_MASK (1 << 9)
647 +#define SOFTRESET_63268_PCIE_EXT_MASK (1 << 10)
648 +#define SOFTRESET_63268_WLAN_SHIM_MASK (1 << 11)
649 +#define SOFTRESET_63268_DDR_PHY_MASK (1 << 12)
650 +#define SOFTRESET_63268_FAP0_MASK (1 << 13)
651 +#define SOFTRESET_63268_WLAN_UBUS_MASK (1 << 14)
652 +#define SOFTRESET_63268_DECT_MASK (1 << 15)
653 +#define SOFTRESET_63268_FAP1_MASK (1 << 16)
654 +#define SOFTRESET_63268_PCIE_HARD_MASK (1 << 17)
655 +#define SOFTRESET_63268_GPHY_MASK (1 << 18)
656 +
657 /* MIPS PLL control register */
658 #define PERF_MIPSPLLCTL_REG 0x34
659 #define MIPSPLLCTL_N1_SHIFT 20
660 @@ -1366,6 +1438,13 @@
661 #define STRAPBUS_6362_BOOT_SEL_SERIAL (1 << 15)
662 #define STRAPBUS_6362_BOOT_SEL_NAND (0 << 15)
663
664 +#define MISC_STRAPBUS_63268_REG 0x14
665 +#define STRAPBUS_63268_HSSPI_CLK_FAST (1 << 9)
666 +#define STRAPBUS_63268_BOOT_SEL_SERIAL (1 << 11)
667 +#define STRAPBUS_63268_BOOT_SEL_NAND (0 << 11)
668 +#define STRAPBUS_63268_FCVO_SHIFT 21
669 +#define STRAPBUS_63268_FCVO_MASK (0xf << STRAPBUS_63268_FCVO_SHIFT)
670 +
671 #define MISC_STRAPBUS_6328_REG 0x240
672 #define STRAPBUS_6328_FCVO_SHIFT 7
673 #define STRAPBUS_6328_FCVO_MASK (0x1f << STRAPBUS_6328_FCVO_SHIFT)
674 --- a/arch/mips/include/asm/mach-bcm63xx/ioremap.h
675 +++ b/arch/mips/include/asm/mach-bcm63xx/ioremap.h
676 @@ -25,6 +25,7 @@ static inline int is_bcm63xx_internal_re
677 case BCM6328_CPU_ID:
678 case BCM6362_CPU_ID:
679 case BCM6368_CPU_ID:
680 + case BCM63268_CPU_ID:
681 if (offset >= 0xb0000000 && offset < 0xb1000000)
682 return 1;
683 break;
684 --- a/arch/mips/bcm63xx/dev-hsspi.c
685 +++ b/arch/mips/bcm63xx/dev-hsspi.c
686 @@ -35,7 +35,7 @@ static struct platform_device bcm63xx_hs
687
688 int __init bcm63xx_hsspi_register(void)
689 {
690 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362())
691 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_63268())
692 return -ENODEV;
693
694 spi_resources[0].start = bcm63xx_regset_address(RSET_HSSPI);
695 --- a/arch/mips/bcm63xx/dev-enet.c
696 +++ b/arch/mips/bcm63xx/dev-enet.c
697 @@ -176,7 +176,8 @@ static int __init register_shared(void)
698 else
699 shared_res[0].end += (RSET_ENETDMA_SIZE) - 1;
700
701 - if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368())
702 + if (BCMCPU_IS_6328() || BCMCPU_IS_6362() || BCMCPU_IS_6368() ||
703 + BCMCPU_IS_63268())
704 chan_count = 32;
705 else if (BCMCPU_IS_6345())
706 chan_count = 8;
707 @@ -276,7 +277,8 @@ bcm63xx_enetsw_register(const struct bcm
708 {
709 int ret;
710
711 - if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368())
712 + if (!BCMCPU_IS_6328() && !BCMCPU_IS_6362() && !BCMCPU_IS_6368() &&
713 + !BCMCPU_IS_63268())
714 return -ENODEV;
715
716 ret = register_shared();
717 @@ -297,6 +299,8 @@ bcm63xx_enetsw_register(const struct bcm
718 enetsw_pd.num_ports = ENETSW_PORTS_6328;
719 else if (BCMCPU_IS_6362() || BCMCPU_IS_6368())
720 enetsw_pd.num_ports = ENETSW_PORTS_6368;
721 + else if (BCMCPU_IS_63268())
722 + enetsw_pd.num_ports = ENETSW_PORTS_63268;
723
724 enetsw_pd.dma_has_sram = true;
725 enetsw_pd.dma_chan_width = ENETDMA_CHAN_WIDTH;
726 --- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
727 +++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_dev_enet.h
728 @@ -62,6 +62,7 @@ struct bcm63xx_enet_platform_data {
729 #define ENETSW_MAX_PORT 8
730 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
731 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
732 +#define ENETSW_PORTS_63268 8 /* 3 FE PHY + 1 GE PHY + 4 RGMII */
733
734 #define ENETSW_RGMII_PORT0 4
735
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