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[cavium-octeon] update to 2.6.30-rc5
[openwrt/svn-archive/archive.git] / target / linux / cavium-octeon / patches / 003_pci_pcie_support.patch
1 This patch adds support for PCI and PCIe to the base Cavium OCTEON
2 processor support.
3
4 Signed-off-by: David Daney <ddaney@caviumnetworks.com>
5 ---
6 arch/mips/Kconfig | 2 +
7 arch/mips/cavium-octeon/Makefile | 4 +
8 arch/mips/cavium-octeon/dma-octeon.c | 310 ++++++-
9 arch/mips/cavium-octeon/executive/Makefile | 2 +
10 .../cavium-octeon/executive/cvmx-helper-errata.c | 379 +++++++
11 .../cavium-octeon/executive/cvmx-helper-util.c | 502 ++++++++++
12 arch/mips/cavium-octeon/executive/cvmx-pcie.c | 1053 ++++++++++++++++++++
13 arch/mips/cavium-octeon/msi.c | 288 ++++++
14 arch/mips/cavium-octeon/octeon-irq.c | 2 +
15 arch/mips/cavium-octeon/pci-common.c | 137 +++
16 arch/mips/cavium-octeon/pci-common.h | 39 +
17 arch/mips/cavium-octeon/pci.c | 568 +++++++++++
18 arch/mips/cavium-octeon/pcie.c | 441 ++++++++
19 arch/mips/include/asm/octeon/cvmx-asm.h | 3 +-
20 arch/mips/include/asm/octeon/cvmx-helper-errata.h | 92 ++
21 arch/mips/include/asm/octeon/cvmx-helper-util.h | 266 +++++
22 arch/mips/include/asm/octeon/cvmx-packet.h | 16 +-
23 arch/mips/include/asm/octeon/cvmx-pcie.h | 284 ++++++
24 arch/mips/include/asm/octeon/cvmx-wqe.h | 422 ++++++++
25 arch/mips/include/asm/octeon/cvmx.h | 12 +
26 arch/mips/include/asm/octeon/octeon.h | 2 +
27 21 files changed, 4816 insertions(+), 8 deletions(-)
28 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
29 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-helper-util.c
30 create mode 100644 arch/mips/cavium-octeon/executive/cvmx-pcie.c
31 create mode 100644 arch/mips/cavium-octeon/msi.c
32 create mode 100644 arch/mips/cavium-octeon/pci-common.c
33 create mode 100644 arch/mips/cavium-octeon/pci-common.h
34 create mode 100644 arch/mips/cavium-octeon/pci.c
35 create mode 100644 arch/mips/cavium-octeon/pcie.c
36 create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-errata.h
37 create mode 100644 arch/mips/include/asm/octeon/cvmx-helper-util.h
38 create mode 100644 arch/mips/include/asm/octeon/cvmx-pcie.h
39 create mode 100644 arch/mips/include/asm/octeon/cvmx-wqe.h
40
41 diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
42 index ea2b262..f009496 100644
43 --- a/arch/mips/Kconfig
44 +++ b/arch/mips/Kconfig
45 @@ -620,6 +620,8 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
46 select SYS_HAS_EARLY_PRINTK
47 select CPU_CAVIUM_OCTEON
48 select SWAP_IO_SPACE
49 + select HW_HAS_PCI
50 + select ARCH_SUPPORTS_MSI
51 help
52 This option supports all of the Octeon reference boards from Cavium
53 Networks. It builds a kernel that dynamically determines the Octeon
54 diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile
55 index 1c2a7fa..2b5f08f 100644
56 --- a/arch/mips/cavium-octeon/Makefile
57 +++ b/arch/mips/cavium-octeon/Makefile
58 @@ -14,5 +14,9 @@
59 obj-y += octeon-memcpy.o
60
61 obj-$(CONFIG_SMP) += smp.o
62 +obj-$(CONFIG_PCI) += pci-common.o
63 +obj-$(CONFIG_PCI) += pci.o
64 +obj-$(CONFIG_PCI) += pcie.o
65 +obj-$(CONFIG_PCI_MSI) += msi.o
66
67 EXTRA_CFLAGS += -Werror
68 diff --git a/arch/mips/cavium-octeon/dma-octeon.c b/arch/mips/cavium-octeon/dma-octeon.c
69 index 01b1ef9..af3c26f 100644
70 --- a/arch/mips/cavium-octeon/dma-octeon.c
71 +++ b/arch/mips/cavium-octeon/dma-octeon.c
72 @@ -13,20 +13,326 @@
73 */
74 #include <linux/types.h>
75 #include <linux/mm.h>
76 +#include <linux/module.h>
77 +#include <linux/string.h>
78 +#include <linux/dma-mapping.h>
79 +#include <linux/platform_device.h>
80 +#include <linux/scatterlist.h>
81 +
82 +#include <linux/cache.h>
83 +#include <linux/io.h>
84 +
85 +#include <asm/octeon/octeon.h>
86 +#include <asm/octeon/cvmx-npi-defs.h>
87 +#include <asm/octeon/cvmx-pci-defs.h>
88
89 #include <dma-coherence.h>
90
91 +#ifdef CONFIG_PCI
92 +#include "pci-common.h"
93 +#endif
94 +
95 +#define BAR2_PCI_ADDRESS 0x8000000000ul
96 +
97 +struct bar1_index_state {
98 + int16_t ref_count; /* Number of PCI mappings using this index */
99 + uint16_t address_bits; /* Upper bits of physical address. This is
100 + shifted 22 bits */
101 +};
102 +
103 +#ifdef CONFIG_PCI
104 +static DEFINE_SPINLOCK(bar1_lock);
105 +static struct bar1_index_state bar1_state[32];
106 +#endif
107 +
108 dma_addr_t octeon_map_dma_mem(struct device *dev, void *ptr, size_t size)
109 {
110 +#ifndef CONFIG_PCI
111 /* Without PCI/PCIe this function can be called for Octeon internal
112 devices such as USB. These devices all support 64bit addressing */
113 mb();
114 return virt_to_phys(ptr);
115 +#else
116 + unsigned long flags;
117 + uint64_t dma_mask;
118 + int64_t start_index;
119 + dma_addr_t result = -1;
120 + uint64_t physical = virt_to_phys(ptr);
121 + int64_t index;
122 +
123 + mb();
124 + /*
125 + * Use the DMA masks to determine the allowed memory
126 + * region. For us it doesn't limit the actual memory, just the
127 + * address visible over PCI. Devices with limits need to use
128 + * lower indexed Bar1 entries.
129 + */
130 + if (dev) {
131 + dma_mask = dev->coherent_dma_mask;
132 + if (dev->dma_mask)
133 + dma_mask = *dev->dma_mask;
134 + } else
135 + dma_mask = 0xfffffffful;
136 +
137 + /*
138 + * Platform devices, such as the internal USB, skip all
139 + * translation and use Octeon physical addresses directly.
140 + */
141 + if (dev->bus == &platform_bus_type)
142 + return physical;
143 +
144 + switch (octeon_dma_bar_type) {
145 + case OCTEON_DMA_BAR_TYPE_PCIE:
146 + if (unlikely(physical < (16ul << 10)))
147 + panic("dma_map_single: Not allowed to map first 16KB."
148 + " It interferes with BAR0 special area\n");
149 + else if ((physical + size >= (256ul << 20)) &&
150 + (physical < (512ul << 20)))
151 + panic("dma_map_single: Not allowed to map bootbus\n");
152 + else if ((physical + size >= 0x400000000ull) &&
153 + physical < 0x410000000ull)
154 + panic("dma_map_single: "
155 + "Attempt to map illegal memory address 0x%lx\n",
156 + physical);
157 + else if (physical >= 0x420000000ull)
158 + panic("dma_map_single: "
159 + "Attempt to map illegal memory address 0x%lx\n",
160 + physical);
161 + else if ((physical + size >=
162 + (4ull<<30) - (OCTEON_PCI_BAR1_HOLE_SIZE<<20))
163 + && physical < (4ull<<30))
164 + pr_warning("dma_map_single: Warning: "
165 + "Mapping memory address that might "
166 + "conflict with devices 0x%lx-0x%lx\n",
167 + physical, physical+size-1);
168 + /* The 2nd 256MB is mapped at 256<<20 instead of 0x410000000 */
169 + if ((physical >= 0x410000000ull) && physical < 0x420000000ull)
170 + result = physical - 0x400000000ull;
171 + else
172 + result = physical;
173 + if (((result+size-1) & dma_mask) != result+size-1)
174 + panic("dma_map_single: Attempt to map address "
175 + "0x%lx-0x%lx, which can't be accessed according "
176 + "to the dma mask 0x%lx\n",
177 + physical, physical+size-1, dma_mask);
178 + goto done;
179 +
180 + case OCTEON_DMA_BAR_TYPE_BIG:
181 +#ifdef CONFIG_64BIT
182 + /* If the device supports 64bit addressing, then use BAR2 */
183 + if (dma_mask > BAR2_PCI_ADDRESS) {
184 + result = physical + BAR2_PCI_ADDRESS;
185 + goto done;
186 + }
187 +#endif
188 + if (unlikely(physical < (4ul << 10))) {
189 + panic("dma_map_single: Not allowed to map first 4KB. "
190 + "It interferes with BAR0 special area\n");
191 + } else if (physical < (256ul << 20)) {
192 + if (unlikely(physical + size > (256ul << 20)))
193 + panic("dma_map_single: Requested memory spans "
194 + "Bar0 0:256MB and bootbus\n");
195 + result = physical;
196 + goto done;
197 + } else if (unlikely(physical < (512ul << 20))) {
198 + panic("dma_map_single: Not allowed to map bootbus\n");
199 + } else if (physical < (2ul << 30)) {
200 + if (unlikely(physical + size > (2ul << 30)))
201 + panic("dma_map_single: Requested memory spans "
202 + "Bar0 512MB:2GB and BAR1\n");
203 + result = physical;
204 + goto done;
205 + } else if (physical < (2ul << 30) + (128 << 20)) {
206 + /* Fall through */
207 + } else if (physical <
208 + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)) {
209 + if (unlikely
210 + (physical + size >
211 + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20)))
212 + panic("dma_map_single: Requested memory "
213 + "extends past Bar1 (4GB-%luMB)\n",
214 + OCTEON_PCI_BAR1_HOLE_SIZE);
215 + result = physical;
216 + goto done;
217 + } else if ((physical >= 0x410000000ull) &&
218 + (physical < 0x420000000ull)) {
219 + if (unlikely(physical + size > 0x420000000ull))
220 + panic("dma_map_single: Requested memory spans "
221 + "non existant memory\n");
222 + /* BAR0 fixed mapping 256MB:512MB ->
223 + * 16GB+256MB:16GB+512MB */
224 + result = physical - 0x400000000ull;
225 + goto done;
226 + } else {
227 + /* Continued below switch statement */
228 + }
229 + break;
230 +
231 + case OCTEON_DMA_BAR_TYPE_SMALL:
232 +#ifdef CONFIG_64BIT
233 + /* If the device supports 64bit addressing, then use BAR2 */
234 + if (dma_mask > BAR2_PCI_ADDRESS) {
235 + result = physical + BAR2_PCI_ADDRESS;
236 + goto done;
237 + }
238 +#endif
239 + /* Continued below switch statement */
240 + break;
241 +
242 + default:
243 + panic("dma_map_single: Invalid octeon_dma_bar_type\n");
244 + }
245 +
246 + /* Don't allow mapping to span multiple Bar entries. The hardware guys
247 + won't guarantee that DMA across boards work */
248 + if (unlikely((physical >> 22) != ((physical + size - 1) >> 22)))
249 + panic("dma_map_single: "
250 + "Requested memory spans more than one Bar1 entry\n");
251 +
252 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
253 + start_index = 31;
254 + else if (unlikely(dma_mask < (1ul << 27)))
255 + start_index = (dma_mask >> 22);
256 + else
257 + start_index = 31;
258 +
259 + /* Only one processor can access the Bar register at once */
260 + spin_lock_irqsave(&bar1_lock, flags);
261 +
262 + /* Look through Bar1 for existing mapping that will work */
263 + for (index = start_index; index >= 0; index--) {
264 + if ((bar1_state[index].address_bits == physical >> 22) &&
265 + (bar1_state[index].ref_count)) {
266 + /* An existing mapping will work, use it */
267 + bar1_state[index].ref_count++;
268 + if (unlikely(bar1_state[index].ref_count < 0))
269 + panic("dma_map_single: "
270 + "Bar1[%d] reference count overflowed\n",
271 + (int) index);
272 + result = (index << 22) | (physical & ((1 << 22) - 1));
273 + /* Large BAR1 is offset at 2GB */
274 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
275 + result += 2ul << 30;
276 + goto done_unlock;
277 + }
278 + }
279 +
280 + /* No existing mappings, look for a free entry */
281 + for (index = start_index; index >= 0; index--) {
282 + if (unlikely(bar1_state[index].ref_count == 0)) {
283 + union cvmx_pci_bar1_indexx bar1_index;
284 + /* We have a free entry, use it */
285 + bar1_state[index].ref_count = 1;
286 + bar1_state[index].address_bits = physical >> 22;
287 + bar1_index.u32 = 0;
288 + /* Address bits[35:22] sent to L2C */
289 + bar1_index.s.addr_idx = physical >> 22;
290 + /* Don't put PCI accesses in L2. */
291 + bar1_index.s.ca = 1;
292 + /* Endian Swap Mode */
293 + bar1_index.s.end_swp = 1;
294 + /* Set '1' when the selected address range is valid. */
295 + bar1_index.s.addr_v = 1;
296 + octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index),
297 + bar1_index.u32);
298 + /* An existing mapping will work, use it */
299 + result = (index << 22) | (physical & ((1 << 22) - 1));
300 + /* Large BAR1 is offset at 2GB */
301 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG)
302 + result += 2ul << 30;
303 + goto done_unlock;
304 + }
305 + }
306 +
307 + pr_err("dma_map_single: "
308 + "Can't find empty BAR1 index for physical mapping 0x%llx\n",
309 + (unsigned long long) physical);
310 +
311 +done_unlock:
312 + spin_unlock_irqrestore(&bar1_lock, flags);
313 +done:
314 + pr_debug("dma_map_single 0x%lx->0x%lx\n", physical, result);
315 + return result;
316 +#endif
317 }
318
319 void octeon_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr)
320 {
321 - /* Without PCI/PCIe this function can be called for Octeon internal
322 - * devices such as USB. These devices all support 64bit addressing */
323 +#ifndef CONFIG_PCI
324 + /*
325 + * Without PCI/PCIe this function can be called for Octeon internal
326 + * devices such as USB. These devices all support 64bit addressing.
327 + */
328 + return;
329 +#else
330 + unsigned long flags;
331 + uint64_t index;
332 +
333 + /*
334 + * Platform devices, such as the internal USB, skip all
335 + * translation and use Octeon physical addresses directly.
336 + */
337 + if (dev->bus == &platform_bus_type)
338 + return;
339 +
340 + switch (octeon_dma_bar_type) {
341 + case OCTEON_DMA_BAR_TYPE_PCIE:
342 + /* Nothing to do, all mappings are static */
343 + goto done;
344 +
345 + case OCTEON_DMA_BAR_TYPE_BIG:
346 +#ifdef CONFIG_64BIT
347 + /* Nothing to do for addresses using BAR2 */
348 + if (dma_addr >= BAR2_PCI_ADDRESS)
349 + goto done;
350 +#endif
351 + if (unlikely(dma_addr < (4ul << 10)))
352 + panic("dma_unmap_single: Unexpect DMA address 0x%lx\n",
353 + dma_addr);
354 + else if (dma_addr < (2ul << 30))
355 + /* Nothing to do for addresses using BAR0 */
356 + goto done;
357 + else if (dma_addr < (2ul << 30) + (128ul << 20))
358 + /* Need to unmap, fall through */
359 + index = (dma_addr - (2ul << 30)) >> 22;
360 + else if (dma_addr <
361 + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20))
362 + goto done; /* Nothing to do for the rest of BAR1 */
363 + else
364 + panic("dma_unmap_single: Unexpect DMA address 0x%lx\n",
365 + dma_addr);
366 + /* Continued below switch statement */
367 + break;
368 +
369 + case OCTEON_DMA_BAR_TYPE_SMALL:
370 +#ifdef CONFIG_64BIT
371 + /* Nothing to do for addresses using BAR2 */
372 + if (dma_addr >= BAR2_PCI_ADDRESS)
373 + goto done;
374 +#endif
375 + index = dma_addr >> 22;
376 + /* Continued below switch statement */
377 + break;
378 +
379 + default:
380 + panic("dma_unmap_single: Invalid octeon_dma_bar_type\n");
381 + }
382 +
383 + if (unlikely(index > 31))
384 + panic("dma_unmap_single: "
385 + "Attempt to unmap an invalid address (0x%llx)\n",
386 + (unsigned long long) dma_addr);
387 +
388 + spin_lock_irqsave(&bar1_lock, flags);
389 + bar1_state[index].ref_count--;
390 + if (bar1_state[index].ref_count == 0)
391 + octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
392 + else if (unlikely(bar1_state[index].ref_count < 0))
393 + panic("dma_unmap_single: Bar1[%u] reference count < 0\n",
394 + (int) index);
395 + spin_unlock_irqrestore(&bar1_lock, flags);
396 +done:
397 + pr_debug("dma_unmap_single 0x%lx\n", dma_addr);
398 return;
399 +#endif
400 }
401 diff --git a/arch/mips/cavium-octeon/executive/Makefile b/arch/mips/cavium-octeon/executive/Makefile
402 index 80d6cb2..9b470dd 100644
403 --- a/arch/mips/cavium-octeon/executive/Makefile
404 +++ b/arch/mips/cavium-octeon/executive/Makefile
405 @@ -11,3 +11,5 @@
406
407 obj-y += cvmx-bootmem.o cvmx-l2c.o cvmx-sysinfo.o octeon-model.o
408
409 +obj-$(CONFIG_PCI) += cvmx-pcie.o
410 +obj-$(CONFIG_PCI) += cvmx-helper-errata.o cvmx-helper-util.o
411 diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
412 new file mode 100644
413 index 0000000..98822c1
414 --- /dev/null
415 +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-errata.c
416 @@ -0,0 +1,379 @@
417 +/***********************license start***************
418 + * Author: Cavium Networks
419 + *
420 + * Contact: support@caviumnetworks.com
421 + * This file is part of the OCTEON SDK
422 + *
423 + * Copyright (c) 2003-2008 Cavium Networks
424 + *
425 + * This file is free software; you can redistribute it and/or modify
426 + * it under the terms of the GNU General Public License, Version 2, as
427 + * published by the Free Software Foundation.
428 + *
429 + * This file is distributed in the hope that it will be useful, but
430 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
431 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
432 + * NONINFRINGEMENT. See the GNU General Public License for more
433 + * details.
434 + *
435 + * You should have received a copy of the GNU General Public License
436 + * along with this file; if not, write to the Free Software
437 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
438 + * or visit http://www.gnu.org/licenses/.
439 + *
440 + * This file may also be available under a different license from Cavium.
441 + * Contact Cavium Networks for more information
442 + ***********************license end**************************************/
443 +
444 +/**
445 + *
446 + * Fixes and workaround for Octeon chip errata. This file
447 + * contains functions called by cvmx-helper to workaround known
448 + * chip errata. For the most part, code doesn't need to call
449 + * these functions directly.
450 + *
451 + */
452 +#include <asm/octeon/octeon.h>
453 +
454 +#include <asm/octeon/cvmx-helper-util.h>
455 +
456 +#ifdef CVMX_ENABLE_PKO_FUNCTIONS
457 +
458 +/**
459 + * @INTERNAL
460 + * Function to adjust internal IPD pointer alignments
461 + *
462 + * Returns 0 on success
463 + * !0 on failure
464 + */
465 +int __cvmx_helper_errata_fix_ipd_ptr_alignment(void)
466 +{
467 +#define FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES \
468 + (CVMX_FPA_PACKET_POOL_SIZE - 8 - CVMX_HELPER_FIRST_MBUFF_SKIP)
469 +#define FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES \
470 + (CVMX_FPA_PACKET_POOL_SIZE - 8 - CVMX_HELPER_NOT_FIRST_MBUFF_SKIP)
471 +#define FIX_IPD_OUTPORT 0
472 + /* Ports 0-15 are interface 0, 16-31 are interface 1 */
473 +#define INTERFACE(port) (port >> 4)
474 +#define INDEX(port) (port & 0xf)
475 + uint64_t *p64;
476 + cvmx_pko_command_word0_t pko_command;
477 + cvmx_buf_ptr_t g_buffer, pkt_buffer;
478 + cvmx_wqe_t *work;
479 + int size, num_segs = 0, wqe_pcnt, pkt_pcnt;
480 + cvmx_gmxx_prtx_cfg_t gmx_cfg;
481 + int retry_cnt;
482 + int retry_loop_cnt;
483 + int mtu;
484 + int i;
485 + cvmx_helper_link_info_t link_info;
486 +
487 + /* Save values for restore at end */
488 + uint64_t prtx_cfg =
489 + cvmx_read_csr(CVMX_GMXX_PRTX_CFG(INDEX(FIX_IPD_OUTPORT),
490 + INTERFACE(FIX_IPD_OUTPORT)));
491 + uint64_t tx_ptr_en =
492 + cvmx_read_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
493 + uint64_t rx_ptr_en =
494 + cvmx_read_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)));
495 + uint64_t rxx_jabber =
496 + cvmx_read_csr(CVMX_GMXX_RXX_JABBER(INDEX(FIX_IPD_OUTPORT),
497 + INTERFACE(FIX_IPD_OUTPORT)));
498 + uint64_t frame_max =
499 + cvmx_read_csr(CVMX_GMXX_RXX_FRM_MAX(INDEX(FIX_IPD_OUTPORT),
500 + INTERFACE(FIX_IPD_OUTPORT)));
501 +
502 + /* Configure port to gig FDX as required for loopback mode */
503 + cvmx_helper_rgmii_internal_loopback(FIX_IPD_OUTPORT);
504 +
505 + /*
506 + * Disable reception on all ports so if traffic is present it
507 + * will not interfere.
508 + */
509 + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)), 0);
510 +
511 + cvmx_wait(100000000ull);
512 +
513 + for (retry_loop_cnt = 0; retry_loop_cnt < 10; retry_loop_cnt++) {
514 + retry_cnt = 100000;
515 + wqe_pcnt = cvmx_read_csr(CVMX_IPD_PTR_COUNT);
516 + pkt_pcnt = (wqe_pcnt >> 7) & 0x7f;
517 + wqe_pcnt &= 0x7f;
518 +
519 + num_segs = (2 + pkt_pcnt - wqe_pcnt) & 3;
520 +
521 + if (num_segs == 0)
522 + goto fix_ipd_exit;
523 +
524 + num_segs += 1;
525 +
526 + size =
527 + FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES +
528 + ((num_segs - 1) * FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES) -
529 + (FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES / 2);
530 +
531 + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)),
532 + 1 << INDEX(FIX_IPD_OUTPORT));
533 + CVMX_SYNC;
534 +
535 + g_buffer.u64 = 0;
536 + g_buffer.s.addr =
537 + cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_WQE_POOL));
538 + if (g_buffer.s.addr == 0) {
539 + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer "
540 + "allocation failure.\n");
541 + goto fix_ipd_exit;
542 + }
543 +
544 + g_buffer.s.pool = CVMX_FPA_WQE_POOL;
545 + g_buffer.s.size = num_segs;
546 +
547 + pkt_buffer.u64 = 0;
548 + pkt_buffer.s.addr =
549 + cvmx_ptr_to_phys(cvmx_fpa_alloc(CVMX_FPA_PACKET_POOL));
550 + if (pkt_buffer.s.addr == 0) {
551 + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT buffer "
552 + "allocation failure.\n");
553 + goto fix_ipd_exit;
554 + }
555 + pkt_buffer.s.i = 1;
556 + pkt_buffer.s.pool = CVMX_FPA_PACKET_POOL;
557 + pkt_buffer.s.size = FIX_IPD_FIRST_BUFF_PAYLOAD_BYTES;
558 +
559 + p64 = (uint64_t *) cvmx_phys_to_ptr(pkt_buffer.s.addr);
560 + p64[0] = 0xffffffffffff0000ull;
561 + p64[1] = 0x08004510ull;
562 + p64[2] = ((uint64_t) (size - 14) << 48) | 0x5ae740004000ull;
563 + p64[3] = 0x3a5fc0a81073c0a8ull;
564 +
565 + for (i = 0; i < num_segs; i++) {
566 + if (i > 0)
567 + pkt_buffer.s.size =
568 + FIX_IPD_NON_FIRST_BUFF_PAYLOAD_BYTES;
569 +
570 + if (i == (num_segs - 1))
571 + pkt_buffer.s.i = 0;
572 +
573 + *(uint64_t *) cvmx_phys_to_ptr(g_buffer.s.addr +
574 + 8 * i) = pkt_buffer.u64;
575 + }
576 +
577 + /* Build the PKO command */
578 + pko_command.u64 = 0;
579 + pko_command.s.segs = num_segs;
580 + pko_command.s.total_bytes = size;
581 + pko_command.s.dontfree = 0;
582 + pko_command.s.gather = 1;
583 +
584 + gmx_cfg.u64 =
585 + cvmx_read_csr(CVMX_GMXX_PRTX_CFG
586 + (INDEX(FIX_IPD_OUTPORT),
587 + INTERFACE(FIX_IPD_OUTPORT)));
588 + gmx_cfg.s.en = 1;
589 + cvmx_write_csr(CVMX_GMXX_PRTX_CFG
590 + (INDEX(FIX_IPD_OUTPORT),
591 + INTERFACE(FIX_IPD_OUTPORT)), gmx_cfg.u64);
592 + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
593 + 1 << INDEX(FIX_IPD_OUTPORT));
594 + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
595 + 1 << INDEX(FIX_IPD_OUTPORT));
596 +
597 + mtu =
598 + cvmx_read_csr(CVMX_GMXX_RXX_JABBER
599 + (INDEX(FIX_IPD_OUTPORT),
600 + INTERFACE(FIX_IPD_OUTPORT)));
601 + cvmx_write_csr(CVMX_GMXX_RXX_JABBER
602 + (INDEX(FIX_IPD_OUTPORT),
603 + INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
604 + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
605 + (INDEX(FIX_IPD_OUTPORT),
606 + INTERFACE(FIX_IPD_OUTPORT)), 65392 - 14 - 4);
607 +
608 +#if CVMX_PKO_USE_FAU_FOR_OUTPUT_QUEUES
609 + cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT,
610 + cvmx_pko_get_base_queue
611 + (FIX_IPD_OUTPORT),
612 + CVMX_PKO_LOCK_NONE);
613 + cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT,
614 + cvmx_pko_get_base_queue
615 + (FIX_IPD_OUTPORT), pko_command,
616 + g_buffer, CVMX_PKO_LOCK_NONE);
617 +#else
618 + cvmx_pko_send_packet_prepare(FIX_IPD_OUTPORT,
619 + cvmx_pko_get_base_queue
620 + (FIX_IPD_OUTPORT),
621 + CVMX_PKO_LOCK_CMD_QUEUE);
622 + cvmx_pko_send_packet_finish(FIX_IPD_OUTPORT,
623 + cvmx_pko_get_base_queue
624 + (FIX_IPD_OUTPORT), pko_command,
625 + g_buffer, CVMX_PKO_LOCK_CMD_QUEUE);
626 +#endif
627 + CVMX_SYNC;
628 +
629 + do {
630 + work = cvmx_pow_work_request_sync(CVMX_POW_WAIT);
631 + retry_cnt--;
632 + } while ((work == NULL) && (retry_cnt > 0));
633 +
634 + if (!retry_cnt)
635 + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT "
636 + "get_work() timeout occured.\n");
637 +
638 + /* Free packet */
639 + if (work)
640 + cvmx_helper_free_packet_data(work);
641 + }
642 +
643 +fix_ipd_exit:
644 +
645 + /* Return CSR configs to saved values */
646 + cvmx_write_csr(CVMX_GMXX_PRTX_CFG
647 + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
648 + prtx_cfg);
649 + cvmx_write_csr(CVMX_ASXX_TX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
650 + tx_ptr_en);
651 + cvmx_write_csr(CVMX_ASXX_RX_PRT_EN(INTERFACE(FIX_IPD_OUTPORT)),
652 + rx_ptr_en);
653 + cvmx_write_csr(CVMX_GMXX_RXX_JABBER
654 + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
655 + rxx_jabber);
656 + cvmx_write_csr(CVMX_GMXX_RXX_FRM_MAX
657 + (INDEX(FIX_IPD_OUTPORT), INTERFACE(FIX_IPD_OUTPORT)),
658 + frame_max);
659 + cvmx_write_csr(CVMX_ASXX_PRT_LOOP(INTERFACE(FIX_IPD_OUTPORT)), 0);
660 + /* Set link to down so autonegotiation will set it up again */
661 + link_info.u64 = 0;
662 + cvmx_helper_link_set(FIX_IPD_OUTPORT, link_info);
663 +
664 + /*
665 + * Bring the link back up as autonegotiation is not done in
666 + * user applications.
667 + */
668 + cvmx_helper_link_autoconf(FIX_IPD_OUTPORT);
669 +
670 + CVMX_SYNC;
671 + if (num_segs)
672 + cvmx_dprintf("WARNING: FIX_IPD_PTR_ALIGNMENT failed.\n");
673 +
674 + return !!num_segs;
675 +
676 +}
677 +
678 +/**
679 + * @INTERNAL
680 + * Workaround ASX setup errata with CN38XX pass1
681 + *
682 + * @interface: Interface to setup
683 + * @port: Port to setup (0..3)
684 + * @cpu_clock_hz:
685 + * Chip frequency in Hertz
686 + *
687 + * Returns Zero on success, negative on failure
688 + */
689 +int __cvmx_helper_errata_asx_pass1(int interface, int port, int cpu_clock_hz)
690 +{
691 + /* Set hi water mark as per errata GMX-4 */
692 + if (cpu_clock_hz >= 325000000 && cpu_clock_hz < 375000000)
693 + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 12);
694 + else if (cpu_clock_hz >= 375000000 && cpu_clock_hz < 437000000)
695 + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 11);
696 + else if (cpu_clock_hz >= 437000000 && cpu_clock_hz < 550000000)
697 + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 10);
698 + else if (cpu_clock_hz >= 550000000 && cpu_clock_hz < 687000000)
699 + cvmx_write_csr(CVMX_ASXX_TX_HI_WATERX(port, interface), 9);
700 + else
701 + cvmx_dprintf("Illegal clock frequency (%d). "
702 + "CVMX_ASXX_TX_HI_WATERX not set\n",
703 + cpu_clock_hz);
704 + return 0;
705 +}
706 +
707 +/**
708 + * This function needs to be called on all Octeon chips with
709 + * errata PKI-100.
710 + *
711 + * The Size field is 8 too large in WQE and next pointers
712 + *
713 + * The Size field generated by IPD is 8 larger than it should
714 + * be. The Size field is <55:40> of both:
715 + * - WORD3 in the work queue entry, and
716 + * - the next buffer pointer (which precedes the packet data
717 + * in each buffer).
718 + *
719 + * @work: Work queue entry to fix
720 + * Returns Zero on success. Negative on failure
721 + */
722 +int cvmx_helper_fix_ipd_packet_chain(cvmx_wqe_t *work)
723 +{
724 + uint64_t number_buffers = work->word2.s.bufs;
725 +
726 + /* We only need to do this if the work has buffers */
727 + if (number_buffers) {
728 + cvmx_buf_ptr_t buffer_ptr = work->packet_ptr;
729 + /* Check for errata PKI-100 */
730 + if ((buffer_ptr.s.pool == 0) &&
731 + (((uint64_t) buffer_ptr.s.size +
732 + ((uint64_t) buffer_ptr.s.back << 7) +
733 + ((uint64_t) buffer_ptr.s.addr & 0x7F)) !=
734 + (CVMX_FPA_PACKET_POOL_SIZE + 8))) {
735 + /* fix is not needed */
736 + return 0;
737 + }
738 + /* Decrement the work packet pointer */
739 + buffer_ptr.s.size -= 8;
740 + work->packet_ptr = buffer_ptr;
741 +
742 + /*
743 + * Now loop through decrementing the size for each
744 + * additional buffer.
745 + */
746 + while (--number_buffers) {
747 + /* Chain pointers are 8 bytes before the data */
748 + cvmx_buf_ptr_t *ptr =
749 + (cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
750 + buffer_ptr = *ptr;
751 + buffer_ptr.s.size -= 8;
752 + *ptr = buffer_ptr;
753 + }
754 + }
755 + /*
756 + * Make sure that these write go out before other operations
757 + * such as FPA frees.
758 + */
759 + CVMX_SYNCWS;
760 + return 0;
761 +}
762 +
763 +#endif /* CVMX_ENABLE_PKO_FUNCTIONS */
764 +
765 +/**
766 + * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
767 + * 1 doesn't work properly. The following code disables 2nd order
768 + * CDR for the specified QLM.
769 + *
770 + * @qlm: QLM to disable 2nd order CDR for.
771 + */
772 +void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm)
773 +{
774 + int lane;
775 + cvmx_helper_qlm_jtag_init();
776 + /* We need to load all four lanes of the QLM, a total of 1072 bits */
777 + for (lane = 0; lane < 4; lane++) {
778 + /*
779 + * Each lane has 268 bits. We need to set
780 + * cfg_cdr_incx<67:64> = 3 and cfg_cdr_secord<77> =
781 + * 1. All other bits are zero. Bits go in LSB first,
782 + * so start off with the zeros for bits <63:0>.
783 + */
784 + cvmx_helper_qlm_jtag_shift_zeros(qlm, 63 - 0 + 1);
785 + /* cfg_cdr_incx<67:64>=3 */
786 + cvmx_helper_qlm_jtag_shift(qlm, 67 - 64 + 1, 3);
787 + /* Zeros for bits <76:68> */
788 + cvmx_helper_qlm_jtag_shift_zeros(qlm, 76 - 68 + 1);
789 + /* cfg_cdr_secord<77>=1 */
790 + cvmx_helper_qlm_jtag_shift(qlm, 77 - 77 + 1, 1);
791 + /* Zeros for bits <267:78> */
792 + cvmx_helper_qlm_jtag_shift_zeros(qlm, 267 - 78 + 1);
793 + }
794 + cvmx_helper_qlm_jtag_update(qlm);
795 +}
796 diff --git a/arch/mips/cavium-octeon/executive/cvmx-helper-util.c b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
797 new file mode 100644
798 index 0000000..dc0087c
799 --- /dev/null
800 +++ b/arch/mips/cavium-octeon/executive/cvmx-helper-util.c
801 @@ -0,0 +1,502 @@
802 +/***********************license start***************
803 + * Author: Cavium Networks
804 + *
805 + * Contact: support@caviumnetworks.com
806 + * This file is part of the OCTEON SDK
807 + *
808 + * Copyright (c) 2003-2008 Cavium Networks
809 + *
810 + * This file is free software; you can redistribute it and/or modify
811 + * it under the terms of the GNU General Public License, Version 2, as
812 + * published by the Free Software Foundation.
813 + *
814 + * This file is distributed in the hope that it will be useful, but
815 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
816 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
817 + * NONINFRINGEMENT. See the GNU General Public License for more
818 + * details.
819 + *
820 + * You should have received a copy of the GNU General Public License
821 + * along with this file; if not, write to the Free Software
822 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
823 + * or visit http://www.gnu.org/licenses/.
824 + *
825 + * This file may also be available under a different license from Cavium.
826 + * Contact Cavium Networks for more information
827 + ***********************license end**************************************/
828 +
829 +/**
830 + *
831 + * Small helper utilities.
832 + *
833 + */
834 +
835 +#include <asm/octeon/octeon.h>
836 +
837 +#include <asm/octeon/cvmx-helper-util.h>
838 +
839 +#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
840 +
841 +/**
842 + * Get the version of the CVMX libraries.
843 + *
844 + * Returns Version string. Note this buffer is allocated statically
845 + * and will be shared by all callers.
846 + */
847 +const char *cvmx_helper_get_version(void)
848 +{
849 + return OCTEON_SDK_VERSION_STRING;
850 +}
851 +
852 +/**
853 + * Convert a interface mode into a human readable string
854 + *
855 + * @mode: Mode to convert
856 + *
857 + * Returns String
858 + */
859 +const char *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t
860 + mode)
861 +{
862 + switch (mode) {
863 + case CVMX_HELPER_INTERFACE_MODE_DISABLED:
864 + return "DISABLED";
865 + case CVMX_HELPER_INTERFACE_MODE_RGMII:
866 + return "RGMII";
867 + case CVMX_HELPER_INTERFACE_MODE_GMII:
868 + return "GMII";
869 + case CVMX_HELPER_INTERFACE_MODE_SPI:
870 + return "SPI";
871 + case CVMX_HELPER_INTERFACE_MODE_PCIE:
872 + return "PCIE";
873 + case CVMX_HELPER_INTERFACE_MODE_XAUI:
874 + return "XAUI";
875 + case CVMX_HELPER_INTERFACE_MODE_SGMII:
876 + return "SGMII";
877 + case CVMX_HELPER_INTERFACE_MODE_PICMG:
878 + return "PICMG";
879 + case CVMX_HELPER_INTERFACE_MODE_NPI:
880 + return "NPI";
881 + case CVMX_HELPER_INTERFACE_MODE_LOOP:
882 + return "LOOP";
883 + }
884 + return "UNKNOWN";
885 +}
886 +
887 +/**
888 + * Debug routine to dump the packet structure to the console
889 + *
890 + * @work: Work queue entry containing the packet to dump
891 + */
892 +int cvmx_helper_dump_packet(cvmx_wqe_t *work)
893 +{
894 + uint64_t count;
895 + uint64_t remaining_bytes;
896 + cvmx_buf_ptr_t buffer_ptr;
897 + uint64_t start_of_buffer;
898 + uint8_t *data_address;
899 + uint8_t *end_of_data;
900 +
901 + cvmx_dprintf("Packet Length: %u\n", work->len);
902 + cvmx_dprintf(" Input Port: %u\n", work->ipprt);
903 + cvmx_dprintf(" QoS: %u\n", work->qos);
904 + cvmx_dprintf(" Buffers: %u\n", work->word2.s.bufs);
905 +
906 + if (work->word2.s.bufs == 0) {
907 + cvmx_ipd_wqe_fpa_queue_t wqe_pool;
908 + wqe_pool.u64 = cvmx_read_csr(CVMX_IPD_WQE_FPA_QUEUE);
909 + buffer_ptr.u64 = 0;
910 + buffer_ptr.s.pool = wqe_pool.s.wqe_pool;
911 + buffer_ptr.s.size = 128;
912 + buffer_ptr.s.addr = cvmx_ptr_to_phys(work->packet_data);
913 + if (cvmx_likely(!work->word2.s.not_IP)) {
914 + if (work->word2.s.is_v6)
915 + buffer_ptr.s.addr += 2;
916 + else
917 + buffer_ptr.s.addr += 6;
918 + }
919 + } else
920 + buffer_ptr = work->packet_ptr;
921 + remaining_bytes = work->len;
922 +
923 + while (remaining_bytes) {
924 + start_of_buffer =
925 + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
926 + cvmx_dprintf(" Buffer Start:%llx\n",
927 + (unsigned long long)start_of_buffer);
928 + cvmx_dprintf(" Buffer I : %u\n", buffer_ptr.s.i);
929 + cvmx_dprintf(" Buffer Back: %u\n", buffer_ptr.s.back);
930 + cvmx_dprintf(" Buffer Pool: %u\n", buffer_ptr.s.pool);
931 + cvmx_dprintf(" Buffer Data: %llx\n",
932 + (unsigned long long)buffer_ptr.s.addr);
933 + cvmx_dprintf(" Buffer Size: %u\n", buffer_ptr.s.size);
934 +
935 + cvmx_dprintf("\t\t");
936 + data_address = (uint8_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr);
937 + end_of_data = data_address + buffer_ptr.s.size;
938 + count = 0;
939 + while (data_address < end_of_data) {
940 + if (remaining_bytes == 0)
941 + break;
942 + else
943 + remaining_bytes--;
944 + cvmx_dprintf("%02x", (unsigned int)*data_address);
945 + data_address++;
946 + if (remaining_bytes && (count == 7)) {
947 + cvmx_dprintf("\n\t\t");
948 + count = 0;
949 + } else
950 + count++;
951 + }
952 + cvmx_dprintf("\n");
953 +
954 + if (remaining_bytes)
955 + buffer_ptr =
956 + *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.
957 + addr - 8);
958 + }
959 + return 0;
960 +}
961 +
962 +/**
963 + * Setup Random Early Drop on a specific input queue
964 + *
965 + * @queue: Input queue to setup RED on (0-7)
966 + * @pass_thresh:
967 + * Packets will begin slowly dropping when there are less than
968 + * this many packet buffers free in FPA 0.
969 + * @drop_thresh:
970 + * All incomming packets will be dropped when there are less
971 + * than this many free packet buffers in FPA 0.
972 + * Returns Zero on success. Negative on failure
973 + */
974 +int cvmx_helper_setup_red_queue(int queue, int pass_thresh, int drop_thresh)
975 +{
976 + cvmx_ipd_qos_red_marks_t red_marks;
977 + cvmx_ipd_red_quex_param_t red_param;
978 +
979 + /*
980 + * Set RED to begin dropping packets when there are
981 + * pass_thresh buffers left. It will linearly drop more
982 + * packets until reaching drop_thresh buffers.
983 + */
984 + red_marks.u64 = 0;
985 + red_marks.s.drop = drop_thresh;
986 + red_marks.s.pass = pass_thresh;
987 + cvmx_write_csr(CVMX_IPD_QOSX_RED_MARKS(queue), red_marks.u64);
988 +
989 + /* Use the actual queue 0 counter, not the average */
990 + red_param.u64 = 0;
991 + red_param.s.prb_con =
992 + (255ul << 24) / (red_marks.s.pass - red_marks.s.drop);
993 + red_param.s.avg_con = 1;
994 + red_param.s.new_con = 255;
995 + red_param.s.use_pcnt = 1;
996 + cvmx_write_csr(CVMX_IPD_RED_QUEX_PARAM(queue), red_param.u64);
997 + return 0;
998 +}
999 +
1000 +/**
1001 + * Setup Random Early Drop to automatically begin dropping packets.
1002 + *
1003 + * @pass_thresh:
1004 + * Packets will begin slowly dropping when there are less than
1005 + * this many packet buffers free in FPA 0.
1006 + * @drop_thresh:
1007 + * All incomming packets will be dropped when there are less
1008 + * than this many free packet buffers in FPA 0.
1009 + * Returns Zero on success. Negative on failure
1010 + */
1011 +int cvmx_helper_setup_red(int pass_thresh, int drop_thresh)
1012 +{
1013 + cvmx_ipd_portx_bp_page_cnt_t page_cnt;
1014 + cvmx_ipd_bp_prt_red_end_t ipd_bp_prt_red_end;
1015 + cvmx_ipd_red_port_enable_t red_port_enable;
1016 + int queue;
1017 + int interface;
1018 + int port;
1019 +
1020 + /* Disable backpressure based on queued buffers. It needs SW support */
1021 + page_cnt.u64 = 0;
1022 + page_cnt.s.bp_enb = 0;
1023 + page_cnt.s.page_cnt = 100;
1024 + for (interface = 0; interface < 2; interface++) {
1025 + for (port = cvmx_helper_get_first_ipd_port(interface);
1026 + port < cvmx_helper_get_last_ipd_port(interface); port++)
1027 + cvmx_write_csr(CVMX_IPD_PORTX_BP_PAGE_CNT(port),
1028 + page_cnt.u64);
1029 + }
1030 +
1031 + for (queue = 0; queue < 8; queue++)
1032 + cvmx_helper_setup_red_queue(queue, pass_thresh, drop_thresh);
1033 +
1034 + /* Shutoff the dropping based on the per port page count. SW isn't
1035 + decrementing it right now */
1036 + ipd_bp_prt_red_end.u64 = 0;
1037 + ipd_bp_prt_red_end.s.prt_enb = 0;
1038 + cvmx_write_csr(CVMX_IPD_BP_PRT_RED_END, ipd_bp_prt_red_end.u64);
1039 +
1040 + red_port_enable.u64 = 0;
1041 + red_port_enable.s.prt_enb = 0xfffffffffull;
1042 + red_port_enable.s.avg_dly = 10000;
1043 + red_port_enable.s.prb_dly = 10000;
1044 + cvmx_write_csr(CVMX_IPD_RED_PORT_ENABLE, red_port_enable.u64);
1045 +
1046 + return 0;
1047 +}
1048 +
1049 +/**
1050 + * Setup the common GMX settings that determine the number of
1051 + * ports. These setting apply to almost all configurations of all
1052 + * chips.
1053 + *
1054 + * @interface: Interface to configure
1055 + * @num_ports: Number of ports on the interface
1056 + *
1057 + * Returns Zero on success, negative on failure
1058 + */
1059 +int __cvmx_helper_setup_gmx(int interface, int num_ports)
1060 +{
1061 + cvmx_gmxx_tx_prts_t gmx_tx_prts;
1062 + cvmx_gmxx_rx_prts_t gmx_rx_prts;
1063 + cvmx_pko_reg_gmx_port_mode_t pko_mode;
1064 +
1065 + /* Tell GMX the number of TX ports on this interface */
1066 + gmx_tx_prts.u64 = cvmx_read_csr(CVMX_GMXX_TX_PRTS(interface));
1067 + gmx_tx_prts.s.prts = num_ports;
1068 + cvmx_write_csr(CVMX_GMXX_TX_PRTS(interface), gmx_tx_prts.u64);
1069 +
1070 + /*
1071 + * Tell GMX the number of RX ports on this interface. This only
1072 + * applies to *GMII and XAUI ports.
1073 + */
1074 + if (cvmx_helper_interface_get_mode(interface) ==
1075 + CVMX_HELPER_INTERFACE_MODE_RGMII
1076 + || cvmx_helper_interface_get_mode(interface) ==
1077 + CVMX_HELPER_INTERFACE_MODE_SGMII
1078 + || cvmx_helper_interface_get_mode(interface) ==
1079 + CVMX_HELPER_INTERFACE_MODE_GMII
1080 + || cvmx_helper_interface_get_mode(interface) ==
1081 + CVMX_HELPER_INTERFACE_MODE_XAUI) {
1082 + if (num_ports > 4) {
1083 + cvmx_dprintf("__cvmx_helper_setup_gmx: "
1084 + "Illegal num_ports\n");
1085 + return -1;
1086 + }
1087 +
1088 + gmx_rx_prts.u64 = cvmx_read_csr(CVMX_GMXX_RX_PRTS(interface));
1089 + gmx_rx_prts.s.prts = num_ports;
1090 + cvmx_write_csr(CVMX_GMXX_RX_PRTS(interface), gmx_rx_prts.u64);
1091 + }
1092 +
1093 + /* Skip setting CVMX_PKO_REG_GMX_PORT_MODE on 30XX and 31XX */
1094 + if (OCTEON_IS_MODEL(OCTEON_CN30XX) || OCTEON_IS_MODEL(OCTEON_CN31XX)
1095 + || OCTEON_IS_MODEL(OCTEON_CN50XX))
1096 + return 0;
1097 +
1098 + /* Tell PKO the number of ports on this interface */
1099 + pko_mode.u64 = cvmx_read_csr(CVMX_PKO_REG_GMX_PORT_MODE);
1100 + if (interface == 0) {
1101 + if (num_ports == 1)
1102 + pko_mode.s.mode0 = 4;
1103 + else if (num_ports == 2)
1104 + pko_mode.s.mode0 = 3;
1105 + else if (num_ports <= 4)
1106 + pko_mode.s.mode0 = 2;
1107 + else if (num_ports <= 8)
1108 + pko_mode.s.mode0 = 1;
1109 + else
1110 + pko_mode.s.mode0 = 0;
1111 + } else {
1112 + if (num_ports == 1)
1113 + pko_mode.s.mode1 = 4;
1114 + else if (num_ports == 2)
1115 + pko_mode.s.mode1 = 3;
1116 + else if (num_ports <= 4)
1117 + pko_mode.s.mode1 = 2;
1118 + else if (num_ports <= 8)
1119 + pko_mode.s.mode1 = 1;
1120 + else
1121 + pko_mode.s.mode1 = 0;
1122 + }
1123 + cvmx_write_csr(CVMX_PKO_REG_GMX_PORT_MODE, pko_mode.u64);
1124 + return 0;
1125 +}
1126 +
1127 +/**
1128 + * Returns the IPD/PKO port number for a port on the given
1129 + * interface.
1130 + *
1131 + * @interface: Interface to use
1132 + * @port: Port on the interface
1133 + *
1134 + * Returns IPD/PKO port number
1135 + */
1136 +int cvmx_helper_get_ipd_port(int interface, int port)
1137 +{
1138 + switch (interface) {
1139 + case 0:
1140 + return port;
1141 + case 1:
1142 + return port + 16;
1143 + case 2:
1144 + return port + 32;
1145 + case 3:
1146 + return port + 36;
1147 + }
1148 + return -1;
1149 +}
1150 +
1151 +#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
1152 +
1153 +/**
1154 + * Returns the interface number for an IPD/PKO port number.
1155 + *
1156 + * @ipd_port: IPD/PKO port number
1157 + *
1158 + * Returns Interface number
1159 + */
1160 +int cvmx_helper_get_interface_num(int ipd_port)
1161 +{
1162 + if (ipd_port < 16)
1163 + return 0;
1164 + else if (ipd_port < 32)
1165 + return 1;
1166 + else if (ipd_port < 36)
1167 + return 2;
1168 + else if (ipd_port < 40)
1169 + return 3;
1170 + else
1171 + cvmx_dprintf("cvmx_helper_get_interface_num: "
1172 + "Illegal IPD port number\n");
1173 +
1174 + return -1;
1175 +}
1176 +
1177 +/**
1178 + * Returns the interface index number for an IPD/PKO port
1179 + * number.
1180 + *
1181 + * @ipd_port: IPD/PKO port number
1182 + *
1183 + * Returns Interface index number
1184 + */
1185 +int cvmx_helper_get_interface_index_num(int ipd_port)
1186 +{
1187 + if (ipd_port < 32)
1188 + return ipd_port & 15;
1189 + else if (ipd_port < 36)
1190 + return ipd_port & 3;
1191 + else if (ipd_port < 40)
1192 + return ipd_port & 3;
1193 + else
1194 + cvmx_dprintf("cvmx_helper_get_interface_index_num: "
1195 + "Illegal IPD port number\n");
1196 +
1197 + return -1;
1198 +}
1199 +
1200 +/**
1201 + * Initialize the internal QLM JTAG logic to allow programming
1202 + * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
1203 + * These functions should only be used at the direction of Cavium
1204 + * Networks. Programming incorrect values into the JTAG chain
1205 + * can cause chip damage.
1206 + */
1207 +void cvmx_helper_qlm_jtag_init(void)
1208 +{
1209 + union cvmx_ciu_qlm_jtgc jtgc;
1210 + int clock_div = 0;
1211 + int divisor = cvmx_sysinfo_get()->cpu_clock_hz / (25 * 1000000);
1212 + divisor = (divisor - 1) >> 2;
1213 + /* Convert the divisor into a power of 2 shift */
1214 + CVMX_CLZ(clock_div, divisor);
1215 + clock_div = 32 - clock_div;
1216 +
1217 + /*
1218 + * Clock divider for QLM JTAG operations. eclk is divided by
1219 + * 2^(CLK_DIV + 2).
1220 + */
1221 + jtgc.u64 = 0;
1222 + jtgc.s.clk_div = clock_div;
1223 + jtgc.s.mux_sel = 0;
1224 + if (OCTEON_IS_MODEL(OCTEON_CN52XX))
1225 + jtgc.s.bypass = 0x3;
1226 + else
1227 + jtgc.s.bypass = 0xf;
1228 + cvmx_write_csr(CVMX_CIU_QLM_JTGC, jtgc.u64);
1229 + cvmx_read_csr(CVMX_CIU_QLM_JTGC);
1230 +}
1231 +
1232 +/**
1233 + * Write up to 32bits into the QLM jtag chain. Bits are shifted
1234 + * into the MSB and out the LSB, so you should shift in the low
1235 + * order bits followed by the high order bits. The JTAG chain is
1236 + * 4 * 268 bits long, or 1072.
1237 + *
1238 + * @qlm: QLM to shift value into
1239 + * @bits: Number of bits to shift in (1-32).
1240 + * @data: Data to shift in. Bit 0 enters the chain first, followed by
1241 + * bit 1, etc.
1242 + *
1243 + * Returns The low order bits of the JTAG chain that shifted out of the
1244 + * circle.
1245 + */
1246 +uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data)
1247 +{
1248 + union cvmx_ciu_qlm_jtgd jtgd;
1249 + jtgd.u64 = 0;
1250 + jtgd.s.shift = 1;
1251 + jtgd.s.shft_cnt = bits - 1;
1252 + jtgd.s.shft_reg = data;
1253 + if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
1254 + jtgd.s.select = 1 << qlm;
1255 + cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
1256 + do {
1257 + jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
1258 + } while (jtgd.s.shift);
1259 + return jtgd.s.shft_reg >> (32 - bits);
1260 +}
1261 +
1262 +/**
1263 + * Shift long sequences of zeros into the QLM JTAG chain. It is
1264 + * common to need to shift more than 32 bits of zeros into the
1265 + * chain. This function is a convience wrapper around
1266 + * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
1267 + * zeros at a time.
1268 + *
1269 + * @qlm: QLM to shift zeros into
1270 + * @bits:
1271 + */
1272 +void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits)
1273 +{
1274 + while (bits > 0) {
1275 + int n = bits;
1276 + if (n > 32)
1277 + n = 32;
1278 + cvmx_helper_qlm_jtag_shift(qlm, n, 0);
1279 + bits -= n;
1280 + }
1281 +}
1282 +
1283 +/**
1284 + * Program the QLM JTAG chain into all lanes of the QLM. You must
1285 + * have already shifted in 268*4, or 1072 bits into the JTAG
1286 + * chain. Updating invalid values can possibly cause chip damage.
1287 + *
1288 + * @qlm: QLM to program
1289 + */
1290 +void cvmx_helper_qlm_jtag_update(int qlm)
1291 +{
1292 + union cvmx_ciu_qlm_jtgd jtgd;
1293 +
1294 + /* Update the new data */
1295 + jtgd.u64 = 0;
1296 + jtgd.s.update = 1;
1297 + if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X))
1298 + jtgd.s.select = 1 << qlm;
1299 + cvmx_write_csr(CVMX_CIU_QLM_JTGD, jtgd.u64);
1300 + do {
1301 + jtgd.u64 = cvmx_read_csr(CVMX_CIU_QLM_JTGD);
1302 + } while (jtgd.s.update);
1303 +}
1304 diff --git a/arch/mips/cavium-octeon/executive/cvmx-pcie.c b/arch/mips/cavium-octeon/executive/cvmx-pcie.c
1305 new file mode 100644
1306 index 0000000..710f21f
1307 --- /dev/null
1308 +++ b/arch/mips/cavium-octeon/executive/cvmx-pcie.c
1309 @@ -0,0 +1,1053 @@
1310 +/***********************license start***************
1311 + * Author: Cavium Networks
1312 + *
1313 + * Contact: support@caviumnetworks.com
1314 + * This file is part of the OCTEON SDK
1315 + *
1316 + * Copyright (c) 2003-2008 Cavium Networks
1317 + *
1318 + * This file is free software; you can redistribute it and/or modify
1319 + * it under the terms of the GNU General Public License, Version 2, as
1320 + * published by the Free Software Foundation.
1321 + *
1322 + * This file is distributed in the hope that it will be useful, but
1323 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
1324 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
1325 + * NONINFRINGEMENT. See the GNU General Public License for more
1326 + * details.
1327 + *
1328 + * You should have received a copy of the GNU General Public License
1329 + * along with this file; if not, write to the Free Software
1330 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
1331 + * 02110-1301 USA or visit http://www.gnu.org/licenses/.
1332 + *
1333 + * This file may also be available under a different license from Cavium.
1334 + * Contact Cavium Networks for more information
1335 + ***********************license end**************************************/
1336 +
1337 +/**
1338 + *
1339 + * Interface to PCIe as a host(RC) or target(EP)
1340 + *
1341 + */
1342 +#include <linux/delay.h>
1343 +#include <asm/byteorder.h>
1344 +
1345 +#include <asm/octeon/octeon.h>
1346 +#include <asm/octeon/cvmx-npei-defs.h>
1347 +#include <asm/octeon/cvmx-pciercx-defs.h>
1348 +#include <asm/octeon/cvmx-pescx-defs.h>
1349 +#include <asm/octeon/cvmx-pexp-defs.h>
1350 +#include <asm/octeon/cvmx-pcieep-defs.h>
1351 +#include <asm/octeon/cvmx-helper-errata.h>
1352 +#include <asm/octeon/cvmx-pcie.h>
1353 +
1354 +/**
1355 + * Return the Core virtual base address for PCIe IO access. IOs are
1356 + * read/written as an offset from this address.
1357 + *
1358 + * @pcie_port: PCIe port the IO is for
1359 + *
1360 + * Returns 64bit Octeon IO base address for read/write
1361 + */
1362 +uint64_t cvmx_pcie_get_io_base_address(int pcie_port)
1363 +{
1364 + union cvmx_pcie_address pcie_addr;
1365 + pcie_addr.u64 = 0;
1366 + pcie_addr.io.upper = 0;
1367 + pcie_addr.io.io = 1;
1368 + pcie_addr.io.did = 3;
1369 + pcie_addr.io.subdid = 2;
1370 + pcie_addr.io.es = 1;
1371 + pcie_addr.io.port = pcie_port;
1372 + return pcie_addr.u64;
1373 +}
1374 +
1375 +/**
1376 + * Size of the IO address region returned at address
1377 + * cvmx_pcie_get_io_base_address()
1378 + *
1379 + * @pcie_port: PCIe port the IO is for
1380 + *
1381 + * Returns Size of the IO window
1382 + */
1383 +uint64_t cvmx_pcie_get_io_size(int pcie_port)
1384 +{
1385 + return 1ull << 32;
1386 +}
1387 +
1388 +/**
1389 + * Return the Core virtual base address for PCIe MEM access. Memory is
1390 + * read/written as an offset from this address.
1391 + *
1392 + * @pcie_port: PCIe port the IO is for
1393 + *
1394 + * Returns 64bit Octeon IO base address for read/write
1395 + */
1396 +uint64_t cvmx_pcie_get_mem_base_address(int pcie_port)
1397 +{
1398 + union cvmx_pcie_address pcie_addr;
1399 + pcie_addr.u64 = 0;
1400 + pcie_addr.mem.upper = 0;
1401 + pcie_addr.mem.io = 1;
1402 + pcie_addr.mem.did = 3;
1403 + pcie_addr.mem.subdid = 3 + pcie_port;
1404 + return pcie_addr.u64;
1405 +}
1406 +
1407 +/**
1408 + * Size of the Mem address region returned at address
1409 + * cvmx_pcie_get_mem_base_address()
1410 + *
1411 + * @pcie_port: PCIe port the IO is for
1412 + *
1413 + * Returns Size of the Mem window
1414 + */
1415 +uint64_t cvmx_pcie_get_mem_size(int pcie_port)
1416 +{
1417 + return 1ull << 36;
1418 +}
1419 +
1420 +/**
1421 + * Initialize the RC config space CSRs
1422 + *
1423 + * @pcie_port: PCIe port to initialize
1424 + */
1425 +static void __cvmx_pcie_rc_initialize_config_space(int pcie_port)
1426 +{
1427 + union cvmx_pciercx_cfg030 pciercx_cfg030;
1428 + union cvmx_npei_ctl_status2 npei_ctl_status2;
1429 + union cvmx_pciercx_cfg070 pciercx_cfg070;
1430 + union cvmx_pciercx_cfg001 pciercx_cfg001;
1431 + union cvmx_pciercx_cfg032 pciercx_cfg032;
1432 + union cvmx_pciercx_cfg006 pciercx_cfg006;
1433 + union cvmx_pciercx_cfg008 pciercx_cfg008;
1434 + union cvmx_pciercx_cfg009 pciercx_cfg009;
1435 + union cvmx_pciercx_cfg010 pciercx_cfg010;
1436 + union cvmx_pciercx_cfg011 pciercx_cfg011;
1437 + union cvmx_pciercx_cfg035 pciercx_cfg035;
1438 + union cvmx_pciercx_cfg075 pciercx_cfg075;
1439 + union cvmx_pciercx_cfg034 pciercx_cfg034;
1440 +
1441 + /* Max Payload Size (PCIE*_CFG030[MPS]) */
1442 + /* Max Read Request Size (PCIE*_CFG030[MRRS]) */
1443 + /* Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN] */
1444 + /* Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN]) */
1445 + pciercx_cfg030.u32 =
1446 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
1447 + /*
1448 + * Max payload size = 128 bytes for best Octeon DMA
1449 + * performance.
1450 + */
1451 + pciercx_cfg030.s.mps = 0;
1452 + /*
1453 + * Max read request size = 128 bytes for best Octeon DMA
1454 + * performance.
1455 + */
1456 + pciercx_cfg030.s.mrrs = 0;
1457 + /* Enable relaxed ordering. */
1458 + pciercx_cfg030.s.ro_en = 1;
1459 + /* Enable no snoop. */
1460 + pciercx_cfg030.s.ns_en = 1;
1461 + /* Correctable error reporting enable. */
1462 + pciercx_cfg030.s.ce_en = 1;
1463 + /* Non-fatal error reporting enable. */
1464 + pciercx_cfg030.s.nfe_en = 1;
1465 + /* Fatal error reporting enable. */
1466 + pciercx_cfg030.s.fe_en = 1;
1467 + /* Unsupported request reporting enable. */
1468 + pciercx_cfg030.s.ur_en = 1;
1469 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
1470 + pciercx_cfg030.u32);
1471 +
1472 + /*
1473 + * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
1474 + * PCIE*_CFG030[MPS]
1475 + *
1476 + * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
1477 + * exceed PCIE*_CFG030[MRRS].
1478 + */
1479 + npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
1480 + /* Max payload size = 128 bytes for best Octeon DMA performance */
1481 + npei_ctl_status2.s.mps = 0;
1482 + /* Max read request size = 128 bytes for best Octeon DMA performance */
1483 + npei_ctl_status2.s.mrrs = 0;
1484 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
1485 +
1486 + /* ECRC Generation (PCIE*_CFG070[GE,CE]) */
1487 + pciercx_cfg070.u32 =
1488 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG070(pcie_port));
1489 + pciercx_cfg070.s.ge = 1; /* ECRC generation enable. */
1490 + pciercx_cfg070.s.ce = 1; /* ECRC check enable. */
1491 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG070(pcie_port),
1492 + pciercx_cfg070.u32);
1493 +
1494 + /*
1495 + * Access Enables (PCIE*_CFG001[MSAE,ME]) ME and MSAE should
1496 + * always be set.
1497 + *
1498 + * Interrupt Disable (PCIE*_CFG001[I_DIS]) System Error
1499 + * Message Enable (PCIE*_CFG001[SEE])
1500 + */
1501 + pciercx_cfg001.u32 =
1502 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG001(pcie_port));
1503 + pciercx_cfg001.s.msae = 1; /* Memory space enable. */
1504 + pciercx_cfg001.s.me = 1; /* Bus master enable. */
1505 + pciercx_cfg001.s.i_dis = 1; /* INTx assertion disable. */
1506 + pciercx_cfg001.s.see = 1; /* SERR# enable */
1507 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG001(pcie_port),
1508 + pciercx_cfg001.u32);
1509 +
1510 + /* Advanced Error Recovery Message Enables */
1511 + /* (PCIE*_CFG066,PCIE*_CFG067,PCIE*_CFG069) */
1512 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG066(pcie_port), 0);
1513 + /* Use CVMX_PCIERCX_CFG067 hardware default */
1514 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG069(pcie_port), 0);
1515 +
1516 + /* Active State Power Management (PCIE*_CFG032[ASLPC]) */
1517 + pciercx_cfg032.u32 =
1518 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG032(pcie_port));
1519 + pciercx_cfg032.s.aslpc = 0; /* Active state Link PM control. */
1520 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG032(pcie_port),
1521 + pciercx_cfg032.u32);
1522 +
1523 + /* Entrance Latencies (PCIE*_CFG451[L0EL,L1EL]) */
1524 +
1525 + /*
1526 + * Link Width Mode (PCIERCn_CFG452[LME]) - Set during
1527 + * cvmx_pcie_rc_initialize_link()
1528 + *
1529 + * Primary Bus Number (PCIERCn_CFG006[PBNUM])
1530 + *
1531 + * We set the primary bus number to 1 so IDT bridges are
1532 + * happy. They don't like zero.
1533 + */
1534 + pciercx_cfg006.u32 = 0;
1535 + pciercx_cfg006.s.pbnum = 1;
1536 + pciercx_cfg006.s.sbnum = 1;
1537 + pciercx_cfg006.s.subbnum = 1;
1538 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG006(pcie_port),
1539 + pciercx_cfg006.u32);
1540 +
1541 + /*
1542 + * Memory-mapped I/O BAR (PCIERCn_CFG008)
1543 + * Most applications should disable the memory-mapped I/O BAR by
1544 + * setting PCIERCn_CFG008[ML_ADDR] < PCIERCn_CFG008[MB_ADDR]
1545 + */
1546 + pciercx_cfg008.u32 = 0;
1547 + pciercx_cfg008.s.mb_addr = 0x100;
1548 + pciercx_cfg008.s.ml_addr = 0;
1549 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG008(pcie_port),
1550 + pciercx_cfg008.u32);
1551 +
1552 + /*
1553 + * Prefetchable BAR (PCIERCn_CFG009,PCIERCn_CFG010,PCIERCn_CFG011)
1554 + * Most applications should disable the prefetchable BAR by setting
1555 + * PCIERCn_CFG011[UMEM_LIMIT],PCIERCn_CFG009[LMEM_LIMIT] <
1556 + * PCIERCn_CFG010[UMEM_BASE],PCIERCn_CFG009[LMEM_BASE]
1557 + */
1558 + pciercx_cfg009.u32 =
1559 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG009(pcie_port));
1560 + pciercx_cfg010.u32 =
1561 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG010(pcie_port));
1562 + pciercx_cfg011.u32 =
1563 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG011(pcie_port));
1564 + pciercx_cfg009.s.lmem_base = 0x100;
1565 + pciercx_cfg009.s.lmem_limit = 0;
1566 + pciercx_cfg010.s.umem_base = 0x100;
1567 + pciercx_cfg011.s.umem_limit = 0;
1568 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG009(pcie_port),
1569 + pciercx_cfg009.u32);
1570 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG010(pcie_port),
1571 + pciercx_cfg010.u32);
1572 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG011(pcie_port),
1573 + pciercx_cfg011.u32);
1574 +
1575 + /*
1576 + * System Error Interrupt Enables (PCIERCn_CFG035[SECEE,SEFEE,SENFEE])
1577 + * PME Interrupt Enables (PCIERCn_CFG035[PMEIE])
1578 + */
1579 + pciercx_cfg035.u32 =
1580 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG035(pcie_port));
1581 + /* System error on correctable error enable. */
1582 + pciercx_cfg035.s.secee = 1;
1583 + /* System error on fatal error enable. */
1584 + pciercx_cfg035.s.sefee = 1;
1585 + /* System error on non-fatal error enable. */
1586 + pciercx_cfg035.s.senfee = 1;
1587 + /* PME interrupt enable. */
1588 + pciercx_cfg035.s.pmeie = 1;
1589 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG035(pcie_port),
1590 + pciercx_cfg035.u32);
1591 +
1592 + /*
1593 + * Advanced Error Recovery Interrupt Enables
1594 + * (PCIERCn_CFG075[CERE,NFERE,FERE])
1595 + */
1596 + pciercx_cfg075.u32 =
1597 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG075(pcie_port));
1598 + /* Correctable error reporting enable. */
1599 + pciercx_cfg075.s.cere = 1;
1600 + /* Non-fatal error reporting enable. */
1601 + pciercx_cfg075.s.nfere = 1;
1602 + /* Fatal error reporting enable. */
1603 + pciercx_cfg075.s.fere = 1;
1604 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG075(pcie_port),
1605 + pciercx_cfg075.u32);
1606 +
1607 + /* HP Interrupt Enables (PCIERCn_CFG034[HPINT_EN],
1608 + * PCIERCn_CFG034[DLLS_EN,CCINT_EN])
1609 + */
1610 + pciercx_cfg034.u32 =
1611 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG034(pcie_port));
1612 + /* Hot-plug interrupt enable. */
1613 + pciercx_cfg034.s.hpint_en = 1;
1614 + /* Data Link Layer state changed enable */
1615 + pciercx_cfg034.s.dlls_en = 1;
1616 + /* Command completed interrupt enable. */
1617 + pciercx_cfg034.s.ccint_en = 1;
1618 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG034(pcie_port),
1619 + pciercx_cfg034.u32);
1620 +}
1621 +
1622 +/**
1623 + * Initialize a host mode PCIe link. This function takes a PCIe
1624 + * port from reset to a link up state. Software can then begin
1625 + * configuring the rest of the link.
1626 + *
1627 + * @pcie_port: PCIe port to initialize
1628 + *
1629 + * Returns Zero on success
1630 + */
1631 +static int __cvmx_pcie_rc_initialize_link(int pcie_port)
1632 +{
1633 + uint64_t start_cycle;
1634 + union cvmx_pescx_ctl_status pescx_ctl_status;
1635 + union cvmx_pciercx_cfg452 pciercx_cfg452;
1636 + union cvmx_pciercx_cfg032 pciercx_cfg032;
1637 + union cvmx_pciercx_cfg448 pciercx_cfg448;
1638 +
1639 + /* Set the lane width */
1640 + pciercx_cfg452.u32 =
1641 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG452(pcie_port));
1642 + pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
1643 + if (pescx_ctl_status.s.qlm_cfg == 0) {
1644 + /* We're in 8 lane (56XX) or 4 lane (54XX) mode */
1645 + pciercx_cfg452.s.lme = 0xf;
1646 + } else {
1647 + /* We're in 4 lane (56XX) or 2 lane (52XX) mode */
1648 + pciercx_cfg452.s.lme = 0x7;
1649 + }
1650 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG452(pcie_port),
1651 + pciercx_cfg452.u32);
1652 +
1653 + /*
1654 + * CN52XX pass 1.x has an errata where length mismatches on UR
1655 + * responses can cause bus errors on 64bit memory
1656 + * reads. Turning off length error checking fixes this.
1657 + */
1658 + if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1659 + union cvmx_pciercx_cfg455 pciercx_cfg455;
1660 + pciercx_cfg455.u32 =
1661 + cvmx_pcie_cfgx_read(pcie_port,
1662 + CVMX_PCIERCX_CFG455(pcie_port));
1663 + pciercx_cfg455.s.m_cpl_len_err = 1;
1664 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG455(pcie_port),
1665 + pciercx_cfg455.u32);
1666 + }
1667 +
1668 + /* Lane swap needs to be manually enabled for CN52XX */
1669 + if (OCTEON_IS_MODEL(OCTEON_CN52XX) && (pcie_port == 1)) {
1670 + pescx_ctl_status.s.lane_swp = 1;
1671 + cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port),
1672 + pescx_ctl_status.u64);
1673 + }
1674 +
1675 + /* Bring up the link */
1676 + pescx_ctl_status.u64 = cvmx_read_csr(CVMX_PESCX_CTL_STATUS(pcie_port));
1677 + pescx_ctl_status.s.lnk_enb = 1;
1678 + cvmx_write_csr(CVMX_PESCX_CTL_STATUS(pcie_port), pescx_ctl_status.u64);
1679 +
1680 + /*
1681 + * CN52XX pass 1.0: Due to a bug in 2nd order CDR, it needs to
1682 + * be disabled.
1683 + */
1684 + if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_0))
1685 + __cvmx_helper_errata_qlm_disable_2nd_order_cdr(0);
1686 +
1687 + /* Wait for the link to come up */
1688 + cvmx_dprintf("PCIe: Waiting for port %d link\n", pcie_port);
1689 + start_cycle = cvmx_get_cycle();
1690 + do {
1691 + if (cvmx_get_cycle() - start_cycle >
1692 + 2 * cvmx_sysinfo_get()->cpu_clock_hz) {
1693 + cvmx_dprintf("PCIe: Port %d link timeout\n",
1694 + pcie_port);
1695 + return -1;
1696 + }
1697 + cvmx_wait(10000);
1698 + pciercx_cfg032.u32 =
1699 + cvmx_pcie_cfgx_read(pcie_port,
1700 + CVMX_PCIERCX_CFG032(pcie_port));
1701 + } while (pciercx_cfg032.s.dlla == 0);
1702 +
1703 + /* Display the link status */
1704 + cvmx_dprintf("PCIe: Port %d link active, %d lanes\n", pcie_port,
1705 + pciercx_cfg032.s.nlw);
1706 +
1707 + /*
1708 + * Update the Replay Time Limit. Empirically, some PCIe
1709 + * devices take a little longer to respond than expected under
1710 + * load. As a workaround for this we configure the Replay Time
1711 + * Limit to the value expected for a 512 byte MPS instead of
1712 + * our actual 256 byte MPS. The numbers below are directly
1713 + * from the PCIe spec table 3-4.
1714 + */
1715 + pciercx_cfg448.u32 =
1716 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG448(pcie_port));
1717 + switch (pciercx_cfg032.s.nlw) {
1718 + case 1: /* 1 lane */
1719 + pciercx_cfg448.s.rtl = 1677;
1720 + break;
1721 + case 2: /* 2 lanes */
1722 + pciercx_cfg448.s.rtl = 867;
1723 + break;
1724 + case 4: /* 4 lanes */
1725 + pciercx_cfg448.s.rtl = 462;
1726 + break;
1727 + case 8: /* 8 lanes */
1728 + pciercx_cfg448.s.rtl = 258;
1729 + break;
1730 + }
1731 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG448(pcie_port),
1732 + pciercx_cfg448.u32);
1733 +
1734 + return 0;
1735 +}
1736 +
1737 +/**
1738 + * Initialize a PCIe port for use in host(RC) mode. It doesn't
1739 + * enumerate the bus.
1740 + *
1741 + * @pcie_port: PCIe port to initialize
1742 + *
1743 + * Returns Zero on success
1744 + */
1745 +int cvmx_pcie_rc_initialize(int pcie_port)
1746 +{
1747 + int i;
1748 + union cvmx_ciu_soft_prst ciu_soft_prst;
1749 + union cvmx_pescx_bist_status pescx_bist_status;
1750 + union cvmx_pescx_bist_status2 pescx_bist_status2;
1751 + union cvmx_npei_ctl_status npei_ctl_status;
1752 + union cvmx_npei_mem_access_ctl npei_mem_access_ctl;
1753 + union cvmx_npei_mem_access_subidx mem_access_subid;
1754 + union cvmx_npei_dbg_data npei_dbg_data;
1755 + union cvmx_pescx_ctl_status2 pescx_ctl_status2;
1756 +
1757 + /*
1758 + * Make sure we aren't trying to setup a target mode interface
1759 + * in host mode.
1760 + */
1761 + npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
1762 + if ((pcie_port == 0) && !npei_ctl_status.s.host_mode) {
1763 + cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() called "
1764 + "on port0, but port0 is not in host mode\n");
1765 + return -1;
1766 + }
1767 +
1768 + /*
1769 + * Make sure a CN52XX isn't trying to bring up port 1 when it
1770 + * is disabled.
1771 + */
1772 + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
1773 + npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
1774 + if ((pcie_port == 1) && npei_dbg_data.cn52xx.qlm0_link_width) {
1775 + cvmx_dprintf("PCIe: ERROR: cvmx_pcie_rc_initialize() "
1776 + "called on port1, but port1 is disabled\n");
1777 + return -1;
1778 + }
1779 + }
1780 +
1781 + /*
1782 + * PCIe switch arbitration mode. '0' == fixed priority NPEI,
1783 + * PCIe0, then PCIe1. '1' == round robin.
1784 + */
1785 + npei_ctl_status.s.arb = 1;
1786 + /* Allow up to 0x20 config retries */
1787 + npei_ctl_status.s.cfg_rtry = 0x20;
1788 + /*
1789 + * CN52XX pass1.x has an errata where P0_NTAGS and P1_NTAGS
1790 + * don't reset.
1791 + */
1792 + if (OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1793 + npei_ctl_status.s.p0_ntags = 0x20;
1794 + npei_ctl_status.s.p1_ntags = 0x20;
1795 + }
1796 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS, npei_ctl_status.u64);
1797 +
1798 + /* Bring the PCIe out of reset */
1799 + if (cvmx_sysinfo_get()->board_type == CVMX_BOARD_TYPE_EBH5200) {
1800 + /*
1801 + * The EBH5200 board swapped the PCIe reset lines on
1802 + * the board. As a workaround for this bug, we bring
1803 + * both PCIe ports out of reset at the same time
1804 + * instead of on separate calls. So for port 0, we
1805 + * bring both out of reset and do nothing on port 1.
1806 + */
1807 + if (pcie_port == 0) {
1808 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1809 + /*
1810 + * After a chip reset the PCIe will also be in
1811 + * reset. If it isn't, most likely someone is
1812 + * trying to init it again without a proper
1813 + * PCIe reset.
1814 + */
1815 + if (ciu_soft_prst.s.soft_prst == 0) {
1816 + /* Reset the ports */
1817 + ciu_soft_prst.s.soft_prst = 1;
1818 + cvmx_write_csr(CVMX_CIU_SOFT_PRST,
1819 + ciu_soft_prst.u64);
1820 + ciu_soft_prst.u64 =
1821 + cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1822 + ciu_soft_prst.s.soft_prst = 1;
1823 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
1824 + ciu_soft_prst.u64);
1825 + /* Wait until pcie resets the ports. */
1826 + udelay(2000);
1827 + }
1828 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1829 + ciu_soft_prst.s.soft_prst = 0;
1830 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1831 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1832 + ciu_soft_prst.s.soft_prst = 0;
1833 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1834 + }
1835 + } else {
1836 + /*
1837 + * The normal case: The PCIe ports are completely
1838 + * separate and can be brought out of reset
1839 + * independently.
1840 + */
1841 + if (pcie_port)
1842 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1843 + else
1844 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1845 + /*
1846 + * After a chip reset the PCIe will also be in
1847 + * reset. If it isn't, most likely someone is trying
1848 + * to init it again without a proper PCIe reset.
1849 + */
1850 + if (ciu_soft_prst.s.soft_prst == 0) {
1851 + /* Reset the port */
1852 + ciu_soft_prst.s.soft_prst = 1;
1853 + if (pcie_port)
1854 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1,
1855 + ciu_soft_prst.u64);
1856 + else
1857 + cvmx_write_csr(CVMX_CIU_SOFT_PRST,
1858 + ciu_soft_prst.u64);
1859 + /* Wait until pcie resets the ports. */
1860 + udelay(2000);
1861 + }
1862 + if (pcie_port) {
1863 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
1864 + ciu_soft_prst.s.soft_prst = 0;
1865 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
1866 + } else {
1867 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
1868 + ciu_soft_prst.s.soft_prst = 0;
1869 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
1870 + }
1871 + }
1872 +
1873 + /*
1874 + * Wait for PCIe reset to complete. Due to errata PCIE-700, we
1875 + * don't poll PESCX_CTL_STATUS2[PCIERST], but simply wait a
1876 + * fixed number of cycles.
1877 + */
1878 + cvmx_wait(400000);
1879 +
1880 + /* PESCX_BIST_STATUS2[PCLK_RUN] was missing on pass 1 of CN56XX and
1881 + CN52XX, so we only probe it on newer chips */
1882 + if (!OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
1883 + && !OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1884 + /* Clear PCLK_RUN so we can check if the clock is running */
1885 + pescx_ctl_status2.u64 =
1886 + cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
1887 + pescx_ctl_status2.s.pclk_run = 1;
1888 + cvmx_write_csr(CVMX_PESCX_CTL_STATUS2(pcie_port),
1889 + pescx_ctl_status2.u64);
1890 + /*
1891 + * Now that we cleared PCLK_RUN, wait for it to be set
1892 + * again telling us the clock is running.
1893 + */
1894 + if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CTL_STATUS2(pcie_port),
1895 + union cvmx_pescx_ctl_status2,
1896 + pclk_run, ==, 1, 10000)) {
1897 + cvmx_dprintf("PCIe: Port %d isn't clocked, skipping.\n",
1898 + pcie_port);
1899 + return -1;
1900 + }
1901 + }
1902 +
1903 + /*
1904 + * Check and make sure PCIe came out of reset. If it doesn't
1905 + * the board probably hasn't wired the clocks up and the
1906 + * interface should be skipped.
1907 + */
1908 + pescx_ctl_status2.u64 =
1909 + cvmx_read_csr(CVMX_PESCX_CTL_STATUS2(pcie_port));
1910 + if (pescx_ctl_status2.s.pcierst) {
1911 + cvmx_dprintf("PCIe: Port %d stuck in reset, skipping.\n",
1912 + pcie_port);
1913 + return -1;
1914 + }
1915 +
1916 + /*
1917 + * Check BIST2 status. If any bits are set skip this interface. This
1918 + * is an attempt to catch PCIE-813 on pass 1 parts.
1919 + */
1920 + pescx_bist_status2.u64 =
1921 + cvmx_read_csr(CVMX_PESCX_BIST_STATUS2(pcie_port));
1922 + if (pescx_bist_status2.u64) {
1923 + cvmx_dprintf("PCIe: Port %d BIST2 failed. Most likely this "
1924 + "port isn't hooked up, skipping.\n",
1925 + pcie_port);
1926 + return -1;
1927 + }
1928 +
1929 + /* Check BIST status */
1930 + pescx_bist_status.u64 =
1931 + cvmx_read_csr(CVMX_PESCX_BIST_STATUS(pcie_port));
1932 + if (pescx_bist_status.u64)
1933 + cvmx_dprintf("PCIe: BIST FAILED for port %d (0x%016llx)\n",
1934 + pcie_port, CAST64(pescx_bist_status.u64));
1935 +
1936 + /* Initialize the config space CSRs */
1937 + __cvmx_pcie_rc_initialize_config_space(pcie_port);
1938 +
1939 + /* Bring the link up */
1940 + if (__cvmx_pcie_rc_initialize_link(pcie_port)) {
1941 + cvmx_dprintf
1942 + ("PCIe: ERROR: cvmx_pcie_rc_initialize_link() failed\n");
1943 + return -1;
1944 + }
1945 +
1946 + /* Store merge control (NPEI_MEM_ACCESS_CTL[TIMER,MAX_WORD]) */
1947 + npei_mem_access_ctl.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL);
1948 + /* Allow 16 words to combine */
1949 + npei_mem_access_ctl.s.max_word = 0;
1950 + /* Wait up to 127 cycles for more data */
1951 + npei_mem_access_ctl.s.timer = 127;
1952 + cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_CTL, npei_mem_access_ctl.u64);
1953 +
1954 + /* Setup Mem access SubDIDs */
1955 + mem_access_subid.u64 = 0;
1956 + /* Port the request is sent to. */
1957 + mem_access_subid.s.port = pcie_port;
1958 + /* Due to an errata on pass 1 chips, no merging is allowed. */
1959 + mem_access_subid.s.nmerge = 1;
1960 + /* Endian-swap for Reads. */
1961 + mem_access_subid.s.esr = 1;
1962 + /* Endian-swap for Writes. */
1963 + mem_access_subid.s.esw = 1;
1964 + /* No Snoop for Reads. */
1965 + mem_access_subid.s.nsr = 1;
1966 + /* No Snoop for Writes. */
1967 + mem_access_subid.s.nsw = 1;
1968 + /* Disable Relaxed Ordering for Reads. */
1969 + mem_access_subid.s.ror = 0;
1970 + /* Disable Relaxed Ordering for Writes. */
1971 + mem_access_subid.s.row = 0;
1972 + /* PCIe Adddress Bits <63:34>. */
1973 + mem_access_subid.s.ba = 0;
1974 +
1975 + /*
1976 + * Setup mem access 12-15 for port 0, 16-19 for port 1,
1977 + * supplying 36 bits of address space.
1978 + */
1979 + for (i = 12 + pcie_port * 4; i < 16 + pcie_port * 4; i++) {
1980 + cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(i),
1981 + mem_access_subid.u64);
1982 + /* Set each SUBID to extend the addressable range */
1983 + mem_access_subid.s.ba += 1;
1984 + }
1985 +
1986 + /*
1987 + * Disable the peer to peer forwarding register. This must be
1988 + * setup by the OS after it enumerates the bus and assigns
1989 + * addresses to the PCIe busses.
1990 + */
1991 + for (i = 0; i < 4; i++) {
1992 + cvmx_write_csr(CVMX_PESCX_P2P_BARX_START(i, pcie_port), -1);
1993 + cvmx_write_csr(CVMX_PESCX_P2P_BARX_END(i, pcie_port), -1);
1994 + }
1995 +
1996 + /* Set Octeon's BAR0 to decode 0-16KB. It overlaps with Bar2 */
1997 + cvmx_write_csr(CVMX_PESCX_P2N_BAR0_START(pcie_port), 0);
1998 +
1999 + /*
2000 + * Disable Octeon's BAR1. It isn't needed in RC mode since
2001 + * BAR2 maps all of memory. BAR2 also maps 256MB-512MB into
2002 + * the 2nd 256MB of memory.
2003 + */
2004 + cvmx_write_csr(CVMX_PESCX_P2N_BAR1_START(pcie_port), -1);
2005 +
2006 + /*
2007 + * Set Octeon's BAR2 to decode 0-2^39. Bar0 and Bar1 take
2008 + * precedence where they overlap. It also overlaps with the
2009 + * device addresses, so make sure the peer to peer forwarding
2010 + * is set right.
2011 + */
2012 + cvmx_write_csr(CVMX_PESCX_P2N_BAR2_START(pcie_port), 0);
2013 +
2014 + /*
2015 + * Setup BAR2 attributes
2016 + *
2017 + * Relaxed Ordering (NPEI_CTL_PORTn[PTLP_RO,CTLP_RO, WAIT_COM])
2018 + * - PTLP_RO,CTLP_RO should normally be set (except for debug).
2019 + * - WAIT_COM=0 will likely work for all applications.
2020 + *
2021 + * Load completion relaxed ordering (NPEI_CTL_PORTn[WAITL_COM]).
2022 + */
2023 + if (pcie_port) {
2024 + union cvmx_npei_ctl_port1 npei_ctl_port;
2025 + npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT1);
2026 + npei_ctl_port.s.bar2_enb = 1;
2027 + npei_ctl_port.s.bar2_esx = 1;
2028 + npei_ctl_port.s.bar2_cax = 0;
2029 + npei_ctl_port.s.ptlp_ro = 1;
2030 + npei_ctl_port.s.ctlp_ro = 1;
2031 + npei_ctl_port.s.wait_com = 0;
2032 + npei_ctl_port.s.waitl_com = 0;
2033 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT1, npei_ctl_port.u64);
2034 + } else {
2035 + union cvmx_npei_ctl_port0 npei_ctl_port;
2036 + npei_ctl_port.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_PORT0);
2037 + npei_ctl_port.s.bar2_enb = 1;
2038 + npei_ctl_port.s.bar2_esx = 1;
2039 + npei_ctl_port.s.bar2_cax = 0;
2040 + npei_ctl_port.s.ptlp_ro = 1;
2041 + npei_ctl_port.s.ctlp_ro = 1;
2042 + npei_ctl_port.s.wait_com = 0;
2043 + npei_ctl_port.s.waitl_com = 0;
2044 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_PORT0, npei_ctl_port.u64);
2045 + }
2046 + return 0;
2047 +}
2048 +
2049 +/**
2050 + * Shutdown a PCIe port and put it in reset
2051 + *
2052 + * @pcie_port: PCIe port to shutdown
2053 + *
2054 + * Returns Zero on success
2055 + */
2056 +int cvmx_pcie_rc_shutdown(int pcie_port)
2057 +{
2058 + /* Wait for all pending operations to complete */
2059 + if (CVMX_WAIT_FOR_FIELD64(CVMX_PESCX_CPL_LUT_VALID(pcie_port),
2060 + union cvmx_pescx_cpl_lut_valid,
2061 + tag, ==, 0, 2000))
2062 + cvmx_dprintf("PCIe: Port %d shutdown timeout\n", pcie_port);
2063 +
2064 + /* Force reset */
2065 + if (pcie_port) {
2066 + union cvmx_ciu_soft_prst ciu_soft_prst;
2067 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST1);
2068 + ciu_soft_prst.s.soft_prst = 1;
2069 + cvmx_write_csr(CVMX_CIU_SOFT_PRST1, ciu_soft_prst.u64);
2070 + } else {
2071 + union cvmx_ciu_soft_prst ciu_soft_prst;
2072 + ciu_soft_prst.u64 = cvmx_read_csr(CVMX_CIU_SOFT_PRST);
2073 + ciu_soft_prst.s.soft_prst = 1;
2074 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, ciu_soft_prst.u64);
2075 + }
2076 + return 0;
2077 +}
2078 +
2079 +/**
2080 + * Build a PCIe config space request address for a device
2081 + *
2082 + * @pcie_port: PCIe port to access
2083 + * @bus: Sub bus
2084 + * @dev: Device ID
2085 + * @fn: Device sub function
2086 + * @reg: Register to access
2087 + *
2088 + * Returns 64bit Octeon IO address
2089 + */
2090 +static inline uint64_t __cvmx_pcie_build_config_addr(int pcie_port, int bus,
2091 + int dev, int fn, int reg)
2092 +{
2093 + union cvmx_pcie_address pcie_addr;
2094 + union cvmx_pciercx_cfg006 pciercx_cfg006;
2095 +
2096 + pciercx_cfg006.u32 =
2097 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG006(pcie_port));
2098 + if ((bus <= pciercx_cfg006.s.pbnum) && (dev != 0))
2099 + return 0;
2100 +
2101 + pcie_addr.u64 = 0;
2102 + pcie_addr.config.upper = 2;
2103 + pcie_addr.config.io = 1;
2104 + pcie_addr.config.did = 3;
2105 + pcie_addr.config.subdid = 1;
2106 + pcie_addr.config.es = 1;
2107 + pcie_addr.config.port = pcie_port;
2108 + pcie_addr.config.ty = (bus > pciercx_cfg006.s.pbnum);
2109 + pcie_addr.config.bus = bus;
2110 + pcie_addr.config.dev = dev;
2111 + pcie_addr.config.func = fn;
2112 + pcie_addr.config.reg = reg;
2113 + return pcie_addr.u64;
2114 +}
2115 +
2116 +/**
2117 + * Read 8bits from a Device's config space
2118 + *
2119 + * @pcie_port: PCIe port the device is on
2120 + * @bus: Sub bus
2121 + * @dev: Device ID
2122 + * @fn: Device sub function
2123 + * @reg: Register to access
2124 + *
2125 + * Returns Result of the read
2126 + */
2127 +uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev,
2128 + int fn, int reg)
2129 +{
2130 + uint64_t address =
2131 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2132 + if (address)
2133 + return cvmx_read64_uint8(address);
2134 + else
2135 + return 0xff;
2136 +}
2137 +
2138 +/**
2139 + * Read 16bits from a Device's config space
2140 + *
2141 + * @pcie_port: PCIe port the device is on
2142 + * @bus: Sub bus
2143 + * @dev: Device ID
2144 + * @fn: Device sub function
2145 + * @reg: Register to access
2146 + *
2147 + * Returns Result of the read
2148 + */
2149 +uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn,
2150 + int reg)
2151 +{
2152 + uint64_t address =
2153 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2154 + if (address)
2155 + return le16_to_cpu(cvmx_read64_uint16(address));
2156 + else
2157 + return 0xffff;
2158 +}
2159 +
2160 +/**
2161 + * Read 32bits from a Device's config space
2162 + *
2163 + * @pcie_port: PCIe port the device is on
2164 + * @bus: Sub bus
2165 + * @dev: Device ID
2166 + * @fn: Device sub function
2167 + * @reg: Register to access
2168 + *
2169 + * Returns Result of the read
2170 + */
2171 +uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn,
2172 + int reg)
2173 +{
2174 + uint64_t address =
2175 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2176 + if (address)
2177 + return le32_to_cpu(cvmx_read64_uint32(address));
2178 + else
2179 + return 0xffffffff;
2180 +}
2181 +
2182 +/**
2183 + * Write 8bits to a Device's config space
2184 + *
2185 + * @pcie_port: PCIe port the device is on
2186 + * @bus: Sub bus
2187 + * @dev: Device ID
2188 + * @fn: Device sub function
2189 + * @reg: Register to access
2190 + * @val: Value to write
2191 + */
2192 +void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn,
2193 + int reg, uint8_t val)
2194 +{
2195 + uint64_t address =
2196 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2197 + if (address)
2198 + cvmx_write64_uint8(address, val);
2199 +}
2200 +
2201 +/**
2202 + * Write 16bits to a Device's config space
2203 + *
2204 + * @pcie_port: PCIe port the device is on
2205 + * @bus: Sub bus
2206 + * @dev: Device ID
2207 + * @fn: Device sub function
2208 + * @reg: Register to access
2209 + * @val: Value to write
2210 + */
2211 +void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn,
2212 + int reg, uint16_t val)
2213 +{
2214 + uint64_t address =
2215 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2216 + if (address)
2217 + cvmx_write64_uint16(address, cpu_to_le16(val));
2218 +}
2219 +
2220 +/**
2221 + * Write 32bits to a Device's config space
2222 + *
2223 + * @pcie_port: PCIe port the device is on
2224 + * @bus: Sub bus
2225 + * @dev: Device ID
2226 + * @fn: Device sub function
2227 + * @reg: Register to access
2228 + * @val: Value to write
2229 + */
2230 +void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn,
2231 + int reg, uint32_t val)
2232 +{
2233 + uint64_t address =
2234 + __cvmx_pcie_build_config_addr(pcie_port, bus, dev, fn, reg);
2235 + if (address)
2236 + cvmx_write64_uint32(address, cpu_to_le32(val));
2237 +}
2238 +
2239 +/**
2240 + * Read a PCIe config space register indirectly. This is used for
2241 + * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
2242 + *
2243 + * @pcie_port: PCIe port to read from
2244 + * @cfg_offset: Address to read
2245 + *
2246 + * Returns Value read
2247 + */
2248 +uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset)
2249 +{
2250 + union cvmx_pescx_cfg_rd pescx_cfg_rd;
2251 + pescx_cfg_rd.u64 = 0;
2252 + pescx_cfg_rd.s.addr = cfg_offset;
2253 + cvmx_write_csr(CVMX_PESCX_CFG_RD(pcie_port), pescx_cfg_rd.u64);
2254 + pescx_cfg_rd.u64 = cvmx_read_csr(CVMX_PESCX_CFG_RD(pcie_port));
2255 + return pescx_cfg_rd.s.data;
2256 +}
2257 +
2258 +/**
2259 + * Write a PCIe config space register indirectly. This is used for
2260 + * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
2261 + *
2262 + * @pcie_port: PCIe port to write to
2263 + * @cfg_offset: Address to write
2264 + * @val: Value to write
2265 + */
2266 +void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val)
2267 +{
2268 + union cvmx_pescx_cfg_wr pescx_cfg_wr;
2269 + pescx_cfg_wr.u64 = 0;
2270 + pescx_cfg_wr.s.addr = cfg_offset;
2271 + pescx_cfg_wr.s.data = val;
2272 + cvmx_write_csr(CVMX_PESCX_CFG_WR(pcie_port), pescx_cfg_wr.u64);
2273 +}
2274 +
2275 +/**
2276 + * Initialize a PCIe port for use in target(EP) mode.
2277 + *
2278 + * Returns Zero on success
2279 + */
2280 +int cvmx_pcie_ep_initialize(void)
2281 +{
2282 + int pcie_port = 0;
2283 + union cvmx_npei_ctl_status npei_ctl_status;
2284 + union cvmx_pciercx_cfg030 pciercx_cfg030;
2285 + union cvmx_npei_ctl_status2 npei_ctl_status2;
2286 + union cvmx_npei_mem_access_subidx mem_access_subid;
2287 +
2288 + npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
2289 + if (npei_ctl_status.s.host_mode)
2290 + return -1;
2291 +
2292 + /* Enable bus master and memory */
2293 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIEEP_CFG001, 0x6);
2294 +
2295 + /*
2296 + * Max Payload Size (PCIE*_CFG030[MPS])
2297 + * Max Read Request Size (PCIE*_CFG030[MRRS])
2298 + * Relaxed-order, no-snoop enables (PCIE*_CFG030[RO_EN,NS_EN]
2299 + * Error Message Enables (PCIE*_CFG030[CE_EN,NFE_EN,FE_EN,UR_EN])
2300 + */
2301 + pciercx_cfg030.u32 =
2302 + cvmx_pcie_cfgx_read(pcie_port, CVMX_PCIERCX_CFG030(pcie_port));
2303 + /* Max payload size = 128 bytes (Limit of most PCs) */
2304 + pciercx_cfg030.s.mps = 0;
2305 + /*
2306 + * Max read request size = 128 bytes for best Octeon DMA
2307 + * performance.
2308 + */
2309 + pciercx_cfg030.s.mrrs = 0;
2310 + /* Enable relaxed ordering. */
2311 + pciercx_cfg030.s.ro_en = 1;
2312 + /* Enable no snoop. */
2313 + pciercx_cfg030.s.ns_en = 1;
2314 + /* Correctable error reporting enable. */
2315 + pciercx_cfg030.s.ce_en = 1;
2316 + /* Non-fatal error reporting enable. */
2317 + pciercx_cfg030.s.nfe_en = 1;
2318 + /* Fatal error reporting enable. */
2319 + pciercx_cfg030.s.fe_en = 1;
2320 + /* Unsupported request reporting enable. */
2321 + pciercx_cfg030.s.ur_en = 1;
2322 + cvmx_pcie_cfgx_write(pcie_port, CVMX_PCIERCX_CFG030(pcie_port),
2323 + pciercx_cfg030.u32);
2324 +
2325 + /*
2326 + * Max Payload Size (NPEI_CTL_STATUS2[MPS]) must match
2327 + * PCIE*_CFG030[MPS]
2328 + *
2329 + * Max Read Request Size (NPEI_CTL_STATUS2[MRRS]) must not
2330 + * exceed PCIE*_CFG030[MRRS]
2331 + */
2332 + npei_ctl_status2.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS2);
2333 + /* Max payload size = 128 bytes (Limit of most PCs) */
2334 + npei_ctl_status2.s.mps = 0;
2335 + /* Max read request size = 128 bytes for best Octeon DMA performance */
2336 + npei_ctl_status2.s.mrrs = 0;
2337 + cvmx_write_csr(CVMX_PEXP_NPEI_CTL_STATUS2, npei_ctl_status2.u64);
2338 +
2339 + /* Setup Mem access SubDID 12 to access Host memory */
2340 + mem_access_subid.u64 = 0;
2341 + /* Port the request is sent to. */
2342 + mem_access_subid.s.port = pcie_port;
2343 + /* Merging is allowed in this window. */
2344 + mem_access_subid.s.nmerge = 1;
2345 + /* Endian-swap for Reads. */
2346 + mem_access_subid.s.esr = 0;
2347 + /* Endian-swap for Writes. */
2348 + mem_access_subid.s.esw = 0;
2349 + /* No Snoop for Reads. */
2350 + mem_access_subid.s.nsr = 1;
2351 + /* No Snoop for Writes. */
2352 + mem_access_subid.s.nsw = 1;
2353 + /* Disable Relaxed Ordering for Reads. */
2354 + mem_access_subid.s.ror = 0;
2355 + /* Disable Relaxed Ordering for Writes. */
2356 + mem_access_subid.s.row = 0;
2357 + /* PCIe Adddress Bits <63:34>. */
2358 + mem_access_subid.s.ba = 0;
2359 + cvmx_write_csr(CVMX_PEXP_NPEI_MEM_ACCESS_SUBIDX(12),
2360 + mem_access_subid.u64);
2361 + return 0;
2362 +}
2363 diff --git a/arch/mips/cavium-octeon/msi.c b/arch/mips/cavium-octeon/msi.c
2364 new file mode 100644
2365 index 0000000..964b03b
2366 --- /dev/null
2367 +++ b/arch/mips/cavium-octeon/msi.c
2368 @@ -0,0 +1,288 @@
2369 +/*
2370 + * This file is subject to the terms and conditions of the GNU General Public
2371 + * License. See the file "COPYING" in the main directory of this archive
2372 + * for more details.
2373 + *
2374 + * Copyright (C) 2005-2007 Cavium Networks
2375 + */
2376 +#include <linux/kernel.h>
2377 +#include <linux/init.h>
2378 +#include <linux/msi.h>
2379 +#include <linux/spinlock.h>
2380 +#include <linux/interrupt.h>
2381 +
2382 +#include <asm/octeon/octeon.h>
2383 +#include <asm/octeon/cvmx-npi-defs.h>
2384 +#include <asm/octeon/cvmx-pci-defs.h>
2385 +#include <asm/octeon/cvmx-npei-defs.h>
2386 +#include <asm/octeon/cvmx-pexp-defs.h>
2387 +
2388 +#include "pci-common.h"
2389 +
2390 +/*
2391 + * Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
2392 + * in use.
2393 + */
2394 +static uint64_t msi_free_irq_bitmask;
2395 +
2396 +/*
2397 + * Each bit in msi_multiple_irq_bitmask tells that the device using
2398 + * this bit in msi_free_irq_bitmask is also using the next bit. This
2399 + * is used so we can disable all of the MSI interrupts when a device
2400 + * uses multiple.
2401 + */
2402 +static uint64_t msi_multiple_irq_bitmask;
2403 +
2404 +/*
2405 + * This lock controls updates to msi_free_irq_bitmask and
2406 + * msi_multiple_irq_bitmask.
2407 + */
2408 +static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
2409 +
2410 +
2411 +/**
2412 + * Called when a driver request MSI interrupts instead of the
2413 + * legacy INT A-D. This routine will allocate multiple interrupts
2414 + * for MSI devices that support them. A device can override this by
2415 + * programming the MSI control bits [6:4] before calling
2416 + * pci_enable_msi().
2417 + *
2418 + * @param dev Device requesting MSI interrupts
2419 + * @param desc MSI descriptor
2420 + *
2421 + * Returns 0 on success.
2422 + */
2423 +int arch_setup_msi_irq(struct pci_dev *dev, struct msi_desc *desc)
2424 +{
2425 + struct msi_msg msg;
2426 + uint16_t control;
2427 + int configured_private_bits;
2428 + int request_private_bits;
2429 + int irq;
2430 + int irq_step;
2431 + uint64_t search_mask;
2432 +
2433 + /*
2434 + * Read the MSI config to figure out how many IRQs this device
2435 + * wants. Most devices only want 1, which will give
2436 + * configured_private_bits and request_private_bits equal 0.
2437 + */
2438 + pci_read_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
2439 + &control);
2440 +
2441 + /*
2442 + * If the number of private bits has been configured then use
2443 + * that value instead of the requested number. This gives the
2444 + * driver the chance to override the number of interrupts
2445 + * before calling pci_enable_msi().
2446 + */
2447 + configured_private_bits = (control & PCI_MSI_FLAGS_QSIZE) >> 4;
2448 + if (configured_private_bits == 0) {
2449 + /* Nothing is configured, so use the hardware requested size */
2450 + request_private_bits = (control & PCI_MSI_FLAGS_QMASK) >> 1;
2451 + } else {
2452 + /*
2453 + * Use the number of configured bits, assuming the
2454 + * driver wanted to override the hardware request
2455 + * value.
2456 + */
2457 + request_private_bits = configured_private_bits;
2458 + }
2459 +
2460 + /*
2461 + * The PCI 2.3 spec mandates that there are at most 32
2462 + * interrupts. If this device asks for more, only give it one.
2463 + */
2464 + if (request_private_bits > 5)
2465 + request_private_bits = 0;
2466 +
2467 +try_only_one:
2468 + /*
2469 + * The IRQs have to be aligned on a power of two based on the
2470 + * number being requested.
2471 + */
2472 + irq_step = 1 << request_private_bits;
2473 +
2474 + /* Mask with one bit for each IRQ */
2475 + search_mask = (1 << irq_step) - 1;
2476 +
2477 + /*
2478 + * We're going to search msi_free_irq_bitmask_lock for zero
2479 + * bits. This represents an MSI interrupt number that isn't in
2480 + * use.
2481 + */
2482 + spin_lock(&msi_free_irq_bitmask_lock);
2483 + for (irq = 0; irq < 64; irq += irq_step) {
2484 + if ((msi_free_irq_bitmask & (search_mask << irq)) == 0) {
2485 + msi_free_irq_bitmask |= search_mask << irq;
2486 + msi_multiple_irq_bitmask |= (search_mask >> 1) << irq;
2487 + break;
2488 + }
2489 + }
2490 + spin_unlock(&msi_free_irq_bitmask_lock);
2491 +
2492 + /* Make sure the search for available interrupts didn't fail */
2493 + if (irq >= 64) {
2494 + if (request_private_bits) {
2495 + pr_err("arch_setup_msi_irq: Unable to find %d free "
2496 + "interrupts, trying just one",
2497 + 1 << request_private_bits);
2498 + request_private_bits = 0;
2499 + goto try_only_one;
2500 + } else
2501 + panic("arch_setup_msi_irq: Unable to find a free MSI "
2502 + "interrupt");
2503 + }
2504 +
2505 + /* MSI interrupts start at logical IRQ OCTEON_IRQ_MSI_BIT0 */
2506 + irq += OCTEON_IRQ_MSI_BIT0;
2507 +
2508 + switch (octeon_dma_bar_type) {
2509 + case OCTEON_DMA_BAR_TYPE_SMALL:
2510 + /* When not using big bar, Bar 0 is based at 128MB */
2511 + msg.address_lo =
2512 + ((128ul << 20) + CVMX_PCI_MSI_RCV) & 0xffffffff;
2513 + msg.address_hi = ((128ul << 20) + CVMX_PCI_MSI_RCV) >> 32;
2514 + case OCTEON_DMA_BAR_TYPE_BIG:
2515 + /* When using big bar, Bar 0 is based at 0 */
2516 + msg.address_lo = (0 + CVMX_PCI_MSI_RCV) & 0xffffffff;
2517 + msg.address_hi = (0 + CVMX_PCI_MSI_RCV) >> 32;
2518 + break;
2519 + case OCTEON_DMA_BAR_TYPE_PCIE:
2520 + /* When using PCIe, Bar 0 is based at 0 */
2521 + /* FIXME CVMX_NPEI_MSI_RCV* other than 0? */
2522 + msg.address_lo = (0 + CVMX_NPEI_PCIE_MSI_RCV) & 0xffffffff;
2523 + msg.address_hi = (0 + CVMX_NPEI_PCIE_MSI_RCV) >> 32;
2524 + break;
2525 + default:
2526 + panic("arch_setup_msi_irq: Invalid octeon_dma_bar_type\n");
2527 + }
2528 + msg.data = irq - OCTEON_IRQ_MSI_BIT0;
2529 +
2530 + /* Update the number of IRQs the device has available to it */
2531 + control &= ~PCI_MSI_FLAGS_QSIZE;
2532 + control |= request_private_bits << 4;
2533 + pci_write_config_word(dev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
2534 + control);
2535 +
2536 + set_irq_msi(irq, desc);
2537 + write_msi_msg(irq, &msg);
2538 + return 0;
2539 +}
2540 +
2541 +
2542 +/**
2543 + * Called when a device no longer needs its MSI interrupts. All
2544 + * MSI interrupts for the device are freed.
2545 + *
2546 + * @irq: The devices first irq number. There may be multple in sequence.
2547 + */
2548 +void arch_teardown_msi_irq(unsigned int irq)
2549 +{
2550 + int number_irqs;
2551 + uint64_t bitmask;
2552 +
2553 + if ((irq < OCTEON_IRQ_MSI_BIT0) || (irq > OCTEON_IRQ_MSI_BIT63))
2554 + panic("arch_teardown_msi_irq: Attempted to teardown illegal "
2555 + "MSI interrupt (%d)", irq);
2556 + irq -= OCTEON_IRQ_MSI_BIT0;
2557 +
2558 + /*
2559 + * Count the number of IRQs we need to free by looking at the
2560 + * msi_multiple_irq_bitmask. Each bit set means that the next
2561 + * IRQ is also owned by this device.
2562 + */
2563 + number_irqs = 0;
2564 + while ((irq+number_irqs < 64) &&
2565 + (msi_multiple_irq_bitmask & (1ull << (irq + number_irqs))))
2566 + number_irqs++;
2567 + number_irqs++;
2568 + /* Mask with one bit for each IRQ */
2569 + bitmask = (1 << number_irqs) - 1;
2570 + /* Shift the mask to the correct bit location */
2571 + bitmask <<= irq;
2572 + if ((msi_free_irq_bitmask & bitmask) != bitmask)
2573 + panic("arch_teardown_msi_irq: Attempted to teardown MSI "
2574 + "interrupt (%d) not in use", irq);
2575 +
2576 + /* Checks are done, update the in use bitmask */
2577 + spin_lock(&msi_free_irq_bitmask_lock);
2578 + msi_free_irq_bitmask &= ~bitmask;
2579 + msi_multiple_irq_bitmask &= ~bitmask;
2580 + spin_unlock(&msi_free_irq_bitmask_lock);
2581 +}
2582 +
2583 +
2584 +/**
2585 + * Called by the interrupt handling code when an MSI interrupt
2586 + * occurs.
2587 + *
2588 + * @param cpl
2589 + * @param dev_id
2590 + *
2591 + * @return
2592 + */
2593 +static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
2594 +{
2595 + uint64_t msi_bits;
2596 + int irq;
2597 +
2598 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_PCIE)
2599 + msi_bits = cvmx_read_csr(CVMX_PEXP_NPEI_MSI_RCV0);
2600 + else
2601 + msi_bits = cvmx_read_csr(CVMX_NPI_NPI_MSI_RCV);
2602 + irq = fls64(msi_bits);
2603 + if (irq) {
2604 + irq += OCTEON_IRQ_MSI_BIT0 - 1;
2605 + if (irq_desc[irq].action) {
2606 + do_IRQ(irq);
2607 + return IRQ_HANDLED;
2608 + } else {
2609 + pr_err("Spurious MSI interrupt %d\n", irq);
2610 + if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
2611 + /* These chips have PCIe */
2612 + cvmx_write_csr(CVMX_PEXP_NPEI_MSI_RCV0,
2613 + 1ull << (irq -
2614 + OCTEON_IRQ_MSI_BIT0));
2615 + } else {
2616 + /* These chips have PCI */
2617 + cvmx_write_csr(CVMX_NPI_NPI_MSI_RCV,
2618 + 1ull << (irq -
2619 + OCTEON_IRQ_MSI_BIT0));
2620 + }
2621 + }
2622 + }
2623 + return IRQ_NONE;
2624 +}
2625 +
2626 +
2627 +/**
2628 + * Initializes the MSI interrupt handling code
2629 + *
2630 + * @return
2631 + */
2632 +int octeon_msi_initialize(void)
2633 +{
2634 + int r;
2635 + if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
2636 + r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
2637 + IRQF_SHARED,
2638 + "MSI[0:63]", octeon_msi_interrupt);
2639 + } else if (octeon_is_pci_host()) {
2640 + r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
2641 + IRQF_SHARED,
2642 + "MSI[0:15]", octeon_msi_interrupt);
2643 + r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
2644 + IRQF_SHARED,
2645 + "MSI[16:31]", octeon_msi_interrupt);
2646 + r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
2647 + IRQF_SHARED,
2648 + "MSI[32:47]", octeon_msi_interrupt);
2649 + r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
2650 + IRQF_SHARED,
2651 + "MSI[48:63]", octeon_msi_interrupt);
2652 + }
2653 + return 0;
2654 +}
2655 +
2656 +subsys_initcall(octeon_msi_initialize);
2657 diff --git a/arch/mips/cavium-octeon/octeon-irq.c b/arch/mips/cavium-octeon/octeon-irq.c
2658 index 788d588..3d7be84 100644
2659 --- a/arch/mips/cavium-octeon/octeon-irq.c
2660 +++ b/arch/mips/cavium-octeon/octeon-irq.c
2661 @@ -10,6 +10,8 @@
2662 #include <linux/hardirq.h>
2663
2664 #include <asm/octeon/octeon.h>
2665 +#include <asm/octeon/cvmx-pexp-defs.h>
2666 +#include <asm/octeon/cvmx-npi-defs.h>
2667
2668 DEFINE_RWLOCK(octeon_irq_ciu0_rwlock);
2669 DEFINE_RWLOCK(octeon_irq_ciu1_rwlock);
2670 diff --git a/arch/mips/cavium-octeon/pci-common.c b/arch/mips/cavium-octeon/pci-common.c
2671 new file mode 100644
2672 index 0000000..cd029f8
2673 --- /dev/null
2674 +++ b/arch/mips/cavium-octeon/pci-common.c
2675 @@ -0,0 +1,137 @@
2676 +/*
2677 + * This file is subject to the terms and conditions of the GNU General Public
2678 + * License. See the file "COPYING" in the main directory of this archive
2679 + * for more details.
2680 + *
2681 + * Copyright (C) 2005-2007 Cavium Networks
2682 + */
2683 +#include <linux/kernel.h>
2684 +#include <linux/init.h>
2685 +#include <linux/pci.h>
2686 +#include <linux/interrupt.h>
2687 +#include <linux/time.h>
2688 +#include <linux/delay.h>
2689 +#include "pci-common.h"
2690 +
2691 +typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
2692 +enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
2693 +
2694 +/**
2695 + * Map a PCI device to the appropriate interrupt line
2696 + *
2697 + * @param dev The Linux PCI device structure for the device to map
2698 + * @param slot The slot number for this device on __BUS 0__. Linux
2699 + * enumerates through all the bridges and figures out the
2700 + * slot on Bus 0 where this device eventually hooks to.
2701 + * @param pin The PCI interrupt pin read from the device, then swizzled
2702 + * as it goes through each bridge.
2703 + * @return Interrupt number for the device
2704 + */
2705 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
2706 +{
2707 + if (octeon_pcibios_map_irq)
2708 + return octeon_pcibios_map_irq(dev, slot, pin);
2709 + else
2710 + panic("octeon_pcibios_map_irq doesn't point to a "
2711 + "pcibios_map_irq() function");
2712 +}
2713 +
2714 +
2715 +/**
2716 + * Called to perform platform specific PCI setup
2717 + *
2718 + * @param dev
2719 + * @return
2720 + */
2721 +int pcibios_plat_dev_init(struct pci_dev *dev)
2722 +{
2723 + uint16_t config;
2724 + uint32_t dconfig;
2725 + int pos;
2726 + /*
2727 + * Force the Cache line setting to 64 bytes. The standard
2728 + * Linux bus scan doesn't seem to set it. Octeon really has
2729 + * 128 byte lines, but Intel bridges get really upset if you
2730 + * try and set values above 64 bytes. Value is specified in
2731 + * 32bit words.
2732 + */
2733 + pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
2734 + /* Set latency timers for all devices */
2735 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
2736 +
2737 + /* Enable reporting System errors and parity errors on all devices */
2738 + /* Enable parity checking and error reporting */
2739 + pci_read_config_word(dev, PCI_COMMAND, &config);
2740 + config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
2741 + pci_write_config_word(dev, PCI_COMMAND, config);
2742 +
2743 + if (dev->subordinate) {
2744 + /* Set latency timers on sub bridges */
2745 + pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
2746 + /* More bridge error detection */
2747 + pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
2748 + config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
2749 + pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
2750 + }
2751 +
2752 + /* Enable the PCIe normal error reporting */
2753 + pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
2754 + if (pos) {
2755 + /* Update Device Control */
2756 + pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
2757 + /* Correctable Error Reporting */
2758 + config |= PCI_EXP_DEVCTL_CERE;
2759 + /* Non-Fatal Error Reporting */
2760 + config |= PCI_EXP_DEVCTL_NFERE;
2761 + /* Fatal Error Reporting */
2762 + config |= PCI_EXP_DEVCTL_FERE;
2763 + /* Unsupported Request */
2764 + config |= PCI_EXP_DEVCTL_URRE;
2765 + pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
2766 + }
2767 +
2768 + /* Find the Advanced Error Reporting capability */
2769 + pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
2770 + if (pos) {
2771 + /* Clear Uncorrectable Error Status */
2772 + pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
2773 + &dconfig);
2774 + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
2775 + dconfig);
2776 + /* Enable reporting of all uncorrectable errors */
2777 + /* Uncorrectable Error Mask - turned on bits disable errors */
2778 + pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
2779 + /*
2780 + * Leave severity at HW default. This only controls if
2781 + * errors are reported as uncorrectable or
2782 + * correctable, not if the error is reported.
2783 + */
2784 + /* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
2785 + /* Clear Correctable Error Status */
2786 + pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
2787 + pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
2788 + /* Enable reporting of all correctable errors */
2789 + /* Correctable Error Mask - turned on bits disable errors */
2790 + pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
2791 + /* Advanced Error Capabilities */
2792 + pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
2793 + /* ECRC Generation Enable */
2794 + if (config & PCI_ERR_CAP_ECRC_GENC)
2795 + config |= PCI_ERR_CAP_ECRC_GENE;
2796 + /* ECRC Check Enable */
2797 + if (config & PCI_ERR_CAP_ECRC_CHKC)
2798 + config |= PCI_ERR_CAP_ECRC_CHKE;
2799 + pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
2800 + /* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
2801 + /* Report all errors to the root complex */
2802 + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
2803 + PCI_ERR_ROOT_CMD_COR_EN |
2804 + PCI_ERR_ROOT_CMD_NONFATAL_EN |
2805 + PCI_ERR_ROOT_CMD_FATAL_EN);
2806 + /* Clear the Root status register */
2807 + pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
2808 + pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
2809 + }
2810 +
2811 + return 0;
2812 +}
2813 diff --git a/arch/mips/cavium-octeon/pci-common.h b/arch/mips/cavium-octeon/pci-common.h
2814 new file mode 100644
2815 index 0000000..74ae799
2816 --- /dev/null
2817 +++ b/arch/mips/cavium-octeon/pci-common.h
2818 @@ -0,0 +1,39 @@
2819 +/*
2820 + * This file is subject to the terms and conditions of the GNU General Public
2821 + * License. See the file "COPYING" in the main directory of this archive
2822 + * for more details.
2823 + *
2824 + * Copyright (C) 2005-2007 Cavium Networks
2825 + */
2826 +#ifndef __OCTEON_PCI_COMMON_H__
2827 +#define __OCTEON_PCI_COMMON_H__
2828 +
2829 +#include <linux/pci.h>
2830 +
2831 +/* Some PCI cards require delays when accessing config space. */
2832 +#define PCI_CONFIG_SPACE_DELAY 10000
2833 +
2834 +/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
2835 + Octeon specific version pointed to by this variable. This function needs to
2836 + change for PCI or PCIe based hosts */
2837 +extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
2838 +
2839 +/* The following defines are only used when octeon_dma_bar_type =
2840 + OCTEON_DMA_BAR_TYPE_BIG */
2841 +#define OCTEON_PCI_BAR1_HOLE_BITS 5
2842 +#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
2843 +
2844 +enum octeon_dma_bar_type {
2845 + OCTEON_DMA_BAR_TYPE_INVALID,
2846 + OCTEON_DMA_BAR_TYPE_SMALL,
2847 + OCTEON_DMA_BAR_TYPE_BIG,
2848 + OCTEON_DMA_BAR_TYPE_PCIE
2849 +};
2850 +
2851 +/**
2852 + * This is a variable to tell the DMA mapping system in dma-octeon.c
2853 + * how to map PCI DMA addresses.
2854 + */
2855 +extern enum octeon_dma_bar_type octeon_dma_bar_type;
2856 +
2857 +#endif
2858 diff --git a/arch/mips/cavium-octeon/pci.c b/arch/mips/cavium-octeon/pci.c
2859 new file mode 100644
2860 index 0000000..67c0ff5
2861 --- /dev/null
2862 +++ b/arch/mips/cavium-octeon/pci.c
2863 @@ -0,0 +1,568 @@
2864 +/*
2865 + * This file is subject to the terms and conditions of the GNU General Public
2866 + * License. See the file "COPYING" in the main directory of this archive
2867 + * for more details.
2868 + *
2869 + * Copyright (C) 2005-2007 Cavium Networks
2870 + */
2871 +#include <linux/kernel.h>
2872 +#include <linux/init.h>
2873 +#include <linux/pci.h>
2874 +#include <linux/interrupt.h>
2875 +#include <linux/time.h>
2876 +#include <linux/delay.h>
2877 +
2878 +#include <asm/time.h>
2879 +
2880 +#include <asm/octeon/octeon.h>
2881 +#include <asm/octeon/cvmx-npi-defs.h>
2882 +#include <asm/octeon/cvmx-pci-defs.h>
2883 +
2884 +#include "pci-common.h"
2885 +
2886 +#define USE_OCTEON_INTERNAL_ARBITER
2887 +
2888 +/*
2889 + * Octeon's PCI controller uses did=3, subdid=2 for PCI IO
2890 + * addresses. Use PCI endian swapping 1 so no address swapping is
2891 + * necessary. The Linux io routines will endian swap the data.
2892 + */
2893 +#define OCTEON_PCI_IOSPACE_BASE 0x80011a0400000000ull
2894 +#define OCTEON_PCI_IOSPACE_SIZE (1ull<<32)
2895 +
2896 +/* Octeon't PCI controller uses did=3, subdid=3 for PCI memory. */
2897 +#define OCTEON_PCI_MEMSPACE_OFFSET (0x00011b0000000000ull)
2898 +
2899 +/**
2900 + * This is the bit decoding used for the Octeon PCI controller addresses
2901 + */
2902 +union octeon_pci_address {
2903 + uint64_t u64;
2904 + struct {
2905 + uint64_t upper:2;
2906 + uint64_t reserved:13;
2907 + uint64_t io:1;
2908 + uint64_t did:5;
2909 + uint64_t subdid:3;
2910 + uint64_t reserved2:4;
2911 + uint64_t endian_swap:2;
2912 + uint64_t reserved3:10;
2913 + uint64_t bus:8;
2914 + uint64_t dev:5;
2915 + uint64_t func:3;
2916 + uint64_t reg:8;
2917 + } s;
2918 +};
2919 +
2920 +/**
2921 + * Return the mapping of PCI device number to IRQ line. Each
2922 + * character in the return string represents the interrupt
2923 + * line for the device at that position. Device 1 maps to the
2924 + * first character, etc. The characters A-D are used for PCI
2925 + * interrupts.
2926 + *
2927 + * Returns PCI interrupt mapping
2928 + */
2929 +const char *octeon_get_pci_interrupts(void)
2930 +{
2931 + /*
2932 + * Returning an empty string causes the interrupts to be
2933 + * routed based on the PCI specification. From the PCI spec:
2934 + *
2935 + * INTA# of Device Number 0 is connected to IRQW on the system
2936 + * board. (Device Number has no significance regarding being
2937 + * located on the system board or in a connector.) INTA# of
2938 + * Device Number 1 is connected to IRQX on the system
2939 + * board. INTA# of Device Number 2 is connected to IRQY on the
2940 + * system board. INTA# of Device Number 3 is connected to IRQZ
2941 + * on the system board. The table below describes how each
2942 + * agent's INTx# lines are connected to the system board
2943 + * interrupt lines. The following equation can be used to
2944 + * determine to which INTx# signal on the system board a given
2945 + * device's INTx# line(s) is connected.
2946 + *
2947 + * MB = (D + I) MOD 4 MB = System board Interrupt (IRQW = 0,
2948 + * IRQX = 1, IRQY = 2, and IRQZ = 3) D = Device Number I =
2949 + * Interrupt Number (INTA# = 0, INTB# = 1, INTC# = 2, and
2950 + * INTD# = 3)
2951 + */
2952 + switch (octeon_bootinfo->board_type) {
2953 + case CVMX_BOARD_TYPE_NAO38:
2954 + /* This is really the NAC38 */
2955 + return "AAAAADABAAAAAAAAAAAAAAAAAAAAAAAA";
2956 + case CVMX_BOARD_TYPE_THUNDER:
2957 + return "";
2958 + case CVMX_BOARD_TYPE_EBH3000:
2959 + return "";
2960 + case CVMX_BOARD_TYPE_EBH3100:
2961 + case CVMX_BOARD_TYPE_CN3010_EVB_HS5:
2962 + case CVMX_BOARD_TYPE_CN3005_EVB_HS5:
2963 + return "AAABAAAAAAAAAAAAAAAAAAAAAAAAAAAA";
2964 + case CVMX_BOARD_TYPE_BBGW_REF:
2965 + return "AABCD";
2966 + default:
2967 + return "";
2968 + }
2969 +}
2970 +
2971 +/**
2972 + * Map a PCI device to the appropriate interrupt line
2973 + *
2974 + * @dev: The Linux PCI device structure for the device to map
2975 + * @slot: The slot number for this device on __BUS 0__. Linux
2976 + * enumerates through all the bridges and figures out the
2977 + * slot on Bus 0 where this device eventually hooks to.
2978 + * @pin: The PCI interrupt pin read from the device, then swizzled
2979 + * as it goes through each bridge.
2980 + * Returns Interrupt number for the device
2981 + */
2982 +int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
2983 + u8 slot, u8 pin)
2984 +{
2985 + int irq_num;
2986 + const char *interrupts;
2987 + int dev_num;
2988 +
2989 + /* Get the board specific interrupt mapping */
2990 + interrupts = octeon_get_pci_interrupts();
2991 +
2992 + dev_num = dev->devfn >> 3;
2993 + if (dev_num < strlen(interrupts))
2994 + irq_num = ((interrupts[dev_num] - 'A' + pin - 1) & 3) +
2995 + OCTEON_IRQ_PCI_INT0;
2996 + else
2997 + irq_num = ((slot + pin - 3) & 3) + OCTEON_IRQ_PCI_INT0;
2998 + return irq_num;
2999 +}
3000 +
3001 +
3002 +/**
3003 + * Read a value from configuration space
3004 + *
3005 + */
3006 +static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
3007 + int reg, int size, u32 *val)
3008 +{
3009 + union octeon_pci_address pci_addr;
3010 +
3011 + pci_addr.u64 = 0;
3012 + pci_addr.s.upper = 2;
3013 + pci_addr.s.io = 1;
3014 + pci_addr.s.did = 3;
3015 + pci_addr.s.subdid = 1;
3016 + pci_addr.s.endian_swap = 1;
3017 + pci_addr.s.bus = bus->number;
3018 + pci_addr.s.dev = devfn >> 3;
3019 + pci_addr.s.func = devfn & 0x7;
3020 + pci_addr.s.reg = reg;
3021 +
3022 +#if PCI_CONFIG_SPACE_DELAY
3023 + udelay(PCI_CONFIG_SPACE_DELAY);
3024 +#endif
3025 + switch (size) {
3026 + case 4:
3027 + *val = le32_to_cpu(cvmx_read64_uint32(pci_addr.u64));
3028 + return PCIBIOS_SUCCESSFUL;
3029 + case 2:
3030 + *val = le16_to_cpu(cvmx_read64_uint16(pci_addr.u64));
3031 + return PCIBIOS_SUCCESSFUL;
3032 + case 1:
3033 + *val = cvmx_read64_uint8(pci_addr.u64);
3034 + return PCIBIOS_SUCCESSFUL;
3035 + }
3036 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3037 +}
3038 +
3039 +
3040 +/**
3041 + * Write a value to PCI configuration space
3042 + *
3043 + * @bus:
3044 + * @devfn:
3045 + * @reg:
3046 + * @size:
3047 + * @val:
3048 + * Returns
3049 + */
3050 +static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
3051 + int reg, int size, u32 val)
3052 +{
3053 + union octeon_pci_address pci_addr;
3054 +
3055 + pci_addr.u64 = 0;
3056 + pci_addr.s.upper = 2;
3057 + pci_addr.s.io = 1;
3058 + pci_addr.s.did = 3;
3059 + pci_addr.s.subdid = 1;
3060 + pci_addr.s.endian_swap = 1;
3061 + pci_addr.s.bus = bus->number;
3062 + pci_addr.s.dev = devfn >> 3;
3063 + pci_addr.s.func = devfn & 0x7;
3064 + pci_addr.s.reg = reg;
3065 +
3066 +#if PCI_CONFIG_SPACE_DELAY
3067 + udelay(PCI_CONFIG_SPACE_DELAY);
3068 +#endif
3069 + switch (size) {
3070 + case 4:
3071 + cvmx_write64_uint32(pci_addr.u64, cpu_to_le32(val));
3072 + return PCIBIOS_SUCCESSFUL;
3073 + case 2:
3074 + cvmx_write64_uint16(pci_addr.u64, cpu_to_le16(val));
3075 + return PCIBIOS_SUCCESSFUL;
3076 + case 1:
3077 + cvmx_write64_uint8(pci_addr.u64, val);
3078 + return PCIBIOS_SUCCESSFUL;
3079 + }
3080 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3081 +}
3082 +
3083 +
3084 +static struct pci_ops octeon_pci_ops = {
3085 + octeon_read_config,
3086 + octeon_write_config,
3087 +};
3088 +
3089 +static struct resource octeon_pci_mem_resource = {
3090 + .start = 0,
3091 + .end = 0,
3092 + .name = "Octeon PCI MEM",
3093 + .flags = IORESOURCE_MEM,
3094 +};
3095 +
3096 +/*
3097 + * PCI ports must be above 16KB so the ISA bus filtering in the PCI-X to PCI
3098 + * bridge
3099 + */
3100 +static struct resource octeon_pci_io_resource = {
3101 + .start = 0x4000,
3102 + .end = OCTEON_PCI_IOSPACE_SIZE - 1,
3103 + .name = "Octeon PCI IO",
3104 + .flags = IORESOURCE_IO,
3105 +};
3106 +
3107 +static struct pci_controller octeon_pci_controller = {
3108 + .pci_ops = &octeon_pci_ops,
3109 + .mem_resource = &octeon_pci_mem_resource,
3110 + .mem_offset = OCTEON_PCI_MEMSPACE_OFFSET,
3111 + .io_resource = &octeon_pci_io_resource,
3112 + .io_offset = 0,
3113 + .io_map_base = OCTEON_PCI_IOSPACE_BASE,
3114 +};
3115 +
3116 +
3117 +/**
3118 + * Low level initialize the Octeon PCI controller
3119 + *
3120 + * Returns
3121 + */
3122 +static void octeon_pci_initialize(void)
3123 +{
3124 + union cvmx_pci_cfg01 cfg01;
3125 + union cvmx_npi_ctl_status ctl_status;
3126 + union cvmx_pci_ctl_status_2 ctl_status_2;
3127 + union cvmx_pci_cfg19 cfg19;
3128 + union cvmx_pci_cfg16 cfg16;
3129 + union cvmx_pci_cfg22 cfg22;
3130 + union cvmx_pci_cfg56 cfg56;
3131 +
3132 + /* Reset the PCI Bus */
3133 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x1);
3134 + cvmx_read_csr(CVMX_CIU_SOFT_PRST);
3135 +
3136 + udelay(2000); /* Hold PCI reset for 2 ms */
3137 +
3138 + ctl_status.u64 = 0; /* cvmx_read_csr(CVMX_NPI_CTL_STATUS); */
3139 + ctl_status.s.max_word = 1;
3140 + ctl_status.s.timer = 1;
3141 + cvmx_write_csr(CVMX_NPI_CTL_STATUS, ctl_status.u64);
3142 +
3143 + /* Deassert PCI reset and advertize PCX Host Mode Device Capability
3144 + (64b) */
3145 + cvmx_write_csr(CVMX_CIU_SOFT_PRST, 0x4);
3146 + cvmx_read_csr(CVMX_CIU_SOFT_PRST);
3147 +
3148 + udelay(2000); /* Wait 2 ms after deasserting PCI reset */
3149 +
3150 + ctl_status_2.u32 = 0;
3151 + ctl_status_2.s.tsr_hwm = 1; /* Initializes to 0. Must be set
3152 + before any PCI reads. */
3153 + ctl_status_2.s.bar2pres = 1; /* Enable BAR2 */
3154 + ctl_status_2.s.bar2_enb = 1;
3155 + ctl_status_2.s.bar2_cax = 1; /* Don't use L2 */
3156 + ctl_status_2.s.bar2_esx = 1;
3157 + ctl_status_2.s.pmo_amod = 1; /* Round robin priority */
3158 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
3159 + /* BAR1 hole */
3160 + ctl_status_2.s.bb1_hole = OCTEON_PCI_BAR1_HOLE_BITS;
3161 + ctl_status_2.s.bb1_siz = 1; /* BAR1 is 2GB */
3162 + ctl_status_2.s.bb_ca = 1; /* Don't use L2 with big bars */
3163 + ctl_status_2.s.bb_es = 1; /* Big bar in byte swap mode */
3164 + ctl_status_2.s.bb1 = 1; /* BAR1 is big */
3165 + ctl_status_2.s.bb0 = 1; /* BAR0 is big */
3166 + }
3167 +
3168 + octeon_npi_write32(CVMX_NPI_PCI_CTL_STATUS_2, ctl_status_2.u32);
3169 + udelay(2000); /* Wait 2 ms before doing PCI reads */
3170 +
3171 + ctl_status_2.u32 = octeon_npi_read32(CVMX_NPI_PCI_CTL_STATUS_2);
3172 + pr_notice("PCI Status: %s %s-bit\n",
3173 + ctl_status_2.s.ap_pcix ? "PCI-X" : "PCI",
3174 + ctl_status_2.s.ap_64ad ? "64" : "32");
3175 +
3176 + if (OCTEON_IS_MODEL(OCTEON_CN58XX) || OCTEON_IS_MODEL(OCTEON_CN50XX)) {
3177 + union cvmx_pci_cnt_reg cnt_reg_start;
3178 + union cvmx_pci_cnt_reg cnt_reg_end;
3179 + unsigned long cycles, pci_clock;
3180 +
3181 + cnt_reg_start.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
3182 + cycles = read_c0_cvmcount();
3183 + udelay(1000);
3184 + cnt_reg_end.u64 = cvmx_read_csr(CVMX_NPI_PCI_CNT_REG);
3185 + cycles = read_c0_cvmcount() - cycles;
3186 + pci_clock = (cnt_reg_end.s.pcicnt - cnt_reg_start.s.pcicnt) /
3187 + (cycles / (mips_hpt_frequency / 1000000));
3188 + pr_notice("PCI Clock: %lu MHz\n", pci_clock);
3189 + }
3190 +
3191 + /*
3192 + * TDOMC must be set to one in PCI mode. TDOMC should be set to 4
3193 + * in PCI-X mode to allow four oustanding splits. Otherwise,
3194 + * should not change from its reset value. Don't write PCI_CFG19
3195 + * in PCI mode (0x82000001 reset value), write it to 0x82000004
3196 + * after PCI-X mode is known. MRBCI,MDWE,MDRE -> must be zero.
3197 + * MRBCM -> must be one.
3198 + */
3199 + if (ctl_status_2.s.ap_pcix) {
3200 + cfg19.u32 = 0;
3201 + /*
3202 + * Target Delayed/Split request outstanding maximum
3203 + * count. [1..31] and 0=32. NOTE: If the user
3204 + * programs these bits beyond the Designed Maximum
3205 + * outstanding count, then the designed maximum table
3206 + * depth will be used instead. No additional
3207 + * Deferred/Split transactions will be accepted if
3208 + * this outstanding maximum count is
3209 + * reached. Furthermore, no additional deferred/split
3210 + * transactions will be accepted if the I/O delay/ I/O
3211 + * Split Request outstanding maximum is reached.
3212 + */
3213 + cfg19.s.tdomc = 4;
3214 + /*
3215 + * Master Deferred Read Request Outstanding Max Count
3216 + * (PCI only). CR4C[26:24] Max SAC cycles MAX DAC
3217 + * cycles 000 8 4 001 1 0 010 2 1 011 3 1 100 4 2 101
3218 + * 5 2 110 6 3 111 7 3 For example, if these bits are
3219 + * programmed to 100, the core can support 2 DAC
3220 + * cycles, 4 SAC cycles or a combination of 1 DAC and
3221 + * 2 SAC cycles. NOTE: For the PCI-X maximum
3222 + * outstanding split transactions, refer to
3223 + * CRE0[22:20].
3224 + */
3225 + cfg19.s.mdrrmc = 2;
3226 + /*
3227 + * Master Request (Memory Read) Byte Count/Byte Enable
3228 + * select. 0 = Byte Enables valid. In PCI mode, a
3229 + * burst transaction cannot be performed using Memory
3230 + * Read command=4?h6. 1 = DWORD Byte Count valid
3231 + * (default). In PCI Mode, the memory read byte
3232 + * enables are automatically generated by the
3233 + * core. Note: N3 Master Request transaction sizes are
3234 + * always determined through the
3235 + * am_attr[<35:32>|<7:0>] field.
3236 + */
3237 + cfg19.s.mrbcm = 1;
3238 + octeon_npi_write32(CVMX_NPI_PCI_CFG19, cfg19.u32);
3239 + }
3240 +
3241 +
3242 + cfg01.u32 = 0;
3243 + cfg01.s.msae = 1; /* Memory Space Access Enable */
3244 + cfg01.s.me = 1; /* Master Enable */
3245 + cfg01.s.pee = 1; /* PERR# Enable */
3246 + cfg01.s.see = 1; /* System Error Enable */
3247 + cfg01.s.fbbe = 1; /* Fast Back to Back Transaction Enable */
3248 +
3249 + octeon_npi_write32(CVMX_NPI_PCI_CFG01, cfg01.u32);
3250 +
3251 +#ifdef USE_OCTEON_INTERNAL_ARBITER
3252 + /*
3253 + * When OCTEON is a PCI host, most systems will use OCTEON's
3254 + * internal arbiter, so must enable it before any PCI/PCI-X
3255 + * traffic can occur.
3256 + */
3257 + {
3258 + union cvmx_npi_pci_int_arb_cfg pci_int_arb_cfg;
3259 +
3260 + pci_int_arb_cfg.u64 = 0;
3261 + pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
3262 + cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
3263 + }
3264 +#endif /* USE_OCTEON_INTERNAL_ARBITER */
3265 +
3266 + /*
3267 + * Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
3268 + * TWTAE,TMAE,DPPMR -> must be zero. TILT -> must not be set to
3269 + * 1..7.
3270 + */
3271 + cfg16.u32 = 0;
3272 + cfg16.s.mltd = 1; /* Master Latency Timer Disable */
3273 + octeon_npi_write32(CVMX_NPI_PCI_CFG16, cfg16.u32);
3274 +
3275 + /*
3276 + * Should be written to 0x4ff00. MTTV -> must be zero.
3277 + * FLUSH -> must be 1. MRV -> should be 0xFF.
3278 + */
3279 + cfg22.u32 = 0;
3280 + /* Master Retry Value [1..255] and 0=infinite */
3281 + cfg22.s.mrv = 0xff;
3282 + /*
3283 + * AM_DO_FLUSH_I control NOTE: This bit MUST BE ONE for proper
3284 + * N3K operation.
3285 + */
3286 + cfg22.s.flush = 1;
3287 + octeon_npi_write32(CVMX_NPI_PCI_CFG22, cfg22.u32);
3288 +
3289 + /*
3290 + * MOST Indicates the maximum number of outstanding splits (in -1
3291 + * notation) when OCTEON is in PCI-X mode. PCI-X performance is
3292 + * affected by the MOST selection. Should generally be written
3293 + * with one of 0x3be807, 0x2be807, 0x1be807, or 0x0be807,
3294 + * depending on the desired MOST of 3, 2, 1, or 0, respectively.
3295 + */
3296 + cfg56.u32 = 0;
3297 + cfg56.s.pxcid = 7; /* RO - PCI-X Capability ID */
3298 + cfg56.s.ncp = 0xe8; /* RO - Next Capability Pointer */
3299 + cfg56.s.dpere = 1; /* Data Parity Error Recovery Enable */
3300 + cfg56.s.roe = 1; /* Relaxed Ordering Enable */
3301 + cfg56.s.mmbc = 1; /* Maximum Memory Byte Count
3302 + [0=512B,1=1024B,2=2048B,3=4096B] */
3303 + cfg56.s.most = 3; /* Maximum outstanding Split transactions [0=1
3304 + .. 7=32] */
3305 +
3306 + octeon_npi_write32(CVMX_NPI_PCI_CFG56, cfg56.u32);
3307 +
3308 + /*
3309 + * Affects PCI performance when OCTEON services reads to its
3310 + * BAR1/BAR2. Refer to Section 10.6.1. The recommended values are
3311 + * 0x22, 0x33, and 0x33 for PCI_READ_CMD_6, PCI_READ_CMD_C, and
3312 + * PCI_READ_CMD_E, respectively. Unfortunately due to errata DDR-700,
3313 + * these values need to be changed so they won't possibly prefetch off
3314 + * of the end of memory if PCI is DMAing a buffer at the end of
3315 + * memory. Note that these values differ from their reset values.
3316 + */
3317 + octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_6, 0x21);
3318 + octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_C, 0x31);
3319 + octeon_npi_write32(CVMX_NPI_PCI_READ_CMD_E, 0x31);
3320 +}
3321 +
3322 +
3323 +/**
3324 + * Initialize the Octeon PCI controller
3325 + *
3326 + * Returns
3327 + */
3328 +static int __init octeon_pci_setup(void)
3329 +{
3330 + union cvmx_npi_mem_access_subidx mem_access;
3331 + int index;
3332 +
3333 + /* Only these chips have PCI */
3334 + if (octeon_has_feature(OCTEON_FEATURE_PCIE))
3335 + return 0;
3336 +
3337 + /* Point pcibios_map_irq() to the PCI version of it */
3338 + octeon_pcibios_map_irq = octeon_pci_pcibios_map_irq;
3339 +
3340 + /* Only use the big bars on chips that support it */
3341 + if (OCTEON_IS_MODEL(OCTEON_CN31XX) ||
3342 + OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
3343 + OCTEON_IS_MODEL(OCTEON_CN38XX_PASS1))
3344 + octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_SMALL;
3345 + else
3346 + octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_BIG;
3347 +
3348 + /* PCI I/O and PCI MEM values */
3349 + set_io_port_base(OCTEON_PCI_IOSPACE_BASE);
3350 + ioport_resource.start = 0;
3351 + ioport_resource.end = OCTEON_PCI_IOSPACE_SIZE - 1;
3352 + if (!octeon_is_pci_host()) {
3353 + pr_notice("Not in host mode, PCI Controller not initialized\n");
3354 + return 0;
3355 + }
3356 +
3357 + pr_notice("%s Octeon big bar support\n",
3358 + (octeon_dma_bar_type ==
3359 + OCTEON_DMA_BAR_TYPE_BIG) ? "Enabling" : "Disabling");
3360 +
3361 + octeon_pci_initialize();
3362 +
3363 + mem_access.u64 = 0;
3364 + mem_access.s.esr = 1; /* Endian-Swap on read. */
3365 + mem_access.s.esw = 1; /* Endian-Swap on write. */
3366 + mem_access.s.nsr = 0; /* No-Snoop on read. */
3367 + mem_access.s.nsw = 0; /* No-Snoop on write. */
3368 + mem_access.s.ror = 0; /* Relax Read on read. */
3369 + mem_access.s.row = 0; /* Relax Order on write. */
3370 + mem_access.s.ba = 0; /* PCI Address bits [63:36]. */
3371 + cvmx_write_csr(CVMX_NPI_MEM_ACCESS_SUBID3, mem_access.u64);
3372 +
3373 + /*
3374 + * Remap the Octeon BAR 2 above all 32 bit devices
3375 + * (0x8000000000ul). This is done here so it is remapped
3376 + * before the readl()'s below. We don't want BAR2 overlapping
3377 + * with BAR0/BAR1 during these reads.
3378 + */
3379 + octeon_npi_write32(CVMX_NPI_PCI_CFG08, 0);
3380 + octeon_npi_write32(CVMX_NPI_PCI_CFG09, 0x80);
3381 +
3382 + /* Disable the BAR1 movable mappings */
3383 + for (index = 0; index < 32; index++)
3384 + octeon_npi_write32(CVMX_NPI_PCI_BAR1_INDEXX(index), 0);
3385 +
3386 + if (octeon_dma_bar_type == OCTEON_DMA_BAR_TYPE_BIG) {
3387 + /* Remap the Octeon BAR 0 to 0-2GB */
3388 + octeon_npi_write32(CVMX_NPI_PCI_CFG04, 0);
3389 + octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
3390 +
3391 + /*
3392 + * Remap the Octeon BAR 1 to map 2GB-4GB (minus the
3393 + * BAR 1 hole).
3394 + */
3395 + octeon_npi_write32(CVMX_NPI_PCI_CFG06, 2ul << 30);
3396 + octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
3397 +
3398 + /* Devices go after BAR1 */
3399 + octeon_pci_mem_resource.start =
3400 + OCTEON_PCI_MEMSPACE_OFFSET + (4ul << 30) -
3401 + (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3402 + octeon_pci_mem_resource.end =
3403 + octeon_pci_mem_resource.start + (1ul << 30);
3404 + } else {
3405 + /* Remap the Octeon BAR 0 to map 128MB-(128MB+4KB) */
3406 + octeon_npi_write32(CVMX_NPI_PCI_CFG04, 128ul << 20);
3407 + octeon_npi_write32(CVMX_NPI_PCI_CFG05, 0);
3408 +
3409 + /* Remap the Octeon BAR 1 to map 0-128MB */
3410 + octeon_npi_write32(CVMX_NPI_PCI_CFG06, 0);
3411 + octeon_npi_write32(CVMX_NPI_PCI_CFG07, 0);
3412 +
3413 + /* Devices go after BAR0 */
3414 + octeon_pci_mem_resource.start =
3415 + OCTEON_PCI_MEMSPACE_OFFSET + (128ul << 20) +
3416 + (4ul << 10);
3417 + octeon_pci_mem_resource.end =
3418 + octeon_pci_mem_resource.start + (1ul << 30);
3419 + }
3420 +
3421 + register_pci_controller(&octeon_pci_controller);
3422 +
3423 + /*
3424 + * Clear any errors that might be pending from before the bus
3425 + * was setup properly.
3426 + */
3427 + cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
3428 + return 0;
3429 +}
3430 +
3431 +arch_initcall(octeon_pci_setup);
3432 diff --git a/arch/mips/cavium-octeon/pcie.c b/arch/mips/cavium-octeon/pcie.c
3433 new file mode 100644
3434 index 0000000..cb6662c
3435 --- /dev/null
3436 +++ b/arch/mips/cavium-octeon/pcie.c
3437 @@ -0,0 +1,441 @@
3438 +/*
3439 + * This file is subject to the terms and conditions of the GNU General Public
3440 + * License. See the file "COPYING" in the main directory of this archive
3441 + * for more details.
3442 + *
3443 + * Copyright (C) 2007, 2008 Cavium Networks
3444 + */
3445 +#include <linux/kernel.h>
3446 +#include <linux/init.h>
3447 +#include <linux/pci.h>
3448 +#include <linux/interrupt.h>
3449 +#include <linux/time.h>
3450 +#include <linux/delay.h>
3451 +
3452 +#include <asm/octeon/octeon.h>
3453 +#include <asm/octeon/cvmx-pcie.h>
3454 +#include <asm/octeon/cvmx-npei-defs.h>
3455 +#include <asm/octeon/cvmx-pexp-defs.h>
3456 +
3457 +#include "pci-common.h"
3458 +
3459 +/**
3460 + * Map a PCI device to the appropriate interrupt line
3461 + *
3462 + * @param dev The Linux PCI device structure for the device to map
3463 + * @param slot The slot number for this device on __BUS 0__. Linux
3464 + * enumerates through all the bridges and figures out the
3465 + * slot on Bus 0 where this device eventually hooks to.
3466 + * @param pin The PCI interrupt pin read from the device, then swizzled
3467 + * as it goes through each bridge.
3468 + * @return Interrupt number for the device
3469 + */
3470 +int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
3471 + u8 slot, u8 pin)
3472 +{
3473 + /*
3474 + * The EBH5600 board with the PCI to PCIe bridge mistakenly
3475 + * wires the first slot for both device id 2 and interrupt
3476 + * A. According to the PCI spec, device id 2 should be C. The
3477 + * following kludge attempts to fix this.
3478 + */
3479 + if (strstr(octeon_board_type_string(), "EBH5600") &&
3480 + dev->bus && dev->bus->parent) {
3481 + /*
3482 + * Iterate all the way up the device chain and find
3483 + * the root bus.
3484 + */
3485 + while (dev->bus && dev->bus->parent)
3486 + dev = to_pci_dev(dev->bus->bridge);
3487 + /* If the root bus is number 0 and the PEX 8114 is the
3488 + * root, assume we are behind the miswired bus. We
3489 + * need to correct the swizzle level by two. Yuck.
3490 + */
3491 + if ((dev->bus->number == 0) &&
3492 + (dev->vendor == 0x10b5) && (dev->device == 0x8114)) {
3493 + /*
3494 + * The pin field is one based, not zero. We
3495 + * need to swizzle it by minus two.
3496 + */
3497 + pin = ((pin - 3) & 3) + 1;
3498 + }
3499 + }
3500 + /*
3501 + * The -1 is because pin starts with one, not zero. It might
3502 + * be that this equation needs to include the slot number, but
3503 + * I don't have hardware to check that against.
3504 + */
3505 + return pin - 1 + OCTEON_IRQ_PCI_INT0;
3506 +}
3507 +
3508 +/**
3509 + * Read a value from configuration space
3510 + *
3511 + * @param bus
3512 + * @param devfn
3513 + * @param reg
3514 + * @param size
3515 + * @param val
3516 + * @return
3517 + */
3518 +static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
3519 + unsigned int devfn, int reg, int size,
3520 + u32 *val)
3521 +{
3522 + union octeon_cvmemctl cvmmemctl;
3523 + union octeon_cvmemctl cvmmemctl_save;
3524 + int bus_number = bus->number;
3525 +
3526 + /*
3527 + * We need to force the bus number to be zero on the root
3528 + * bus. Linux numbers the 2nd root bus to start after all
3529 + * buses on root 0.
3530 + */
3531 + if (bus->parent == NULL)
3532 + bus_number = 0;
3533 +
3534 + /*
3535 + * PCIe only has a single device connected to Octeon. It is
3536 + * always device ID 0. Don't bother doing reads for other
3537 + * device IDs on the first segment.
3538 + */
3539 + if ((bus_number == 0) && (devfn >> 3 != 0))
3540 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3541 +
3542 + /*
3543 + * The following is a workaround for the CN57XX, CN56XX,
3544 + * CN55XX, and CN54XX errata with PCIe config reads from non
3545 + * existent devices. These chips will hang the PCIe link if a
3546 + * config read is performed that causes a UR response.
3547 + */
3548 + if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
3549 + OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1)) {
3550 + /*
3551 + * For our EBH5600 board, port 0 has a bridge with two
3552 + * PCI-X slots. We need a new special checks to make
3553 + * sure we only probe valid stuff. The PCIe->PCI-X
3554 + * bridge only respondes to device ID 0, function
3555 + * 0-1
3556 + */
3557 + if ((bus_number == 0) && (devfn >= 2))
3558 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3559 + /*
3560 + * The PCI-X slots are device ID 2,3. Choose one of
3561 + * the below "if" blocks based on what is plugged into
3562 + * the board.
3563 + */
3564 +#if 1
3565 + /* Use this option if you aren't using either slot */
3566 + if (bus_number == 1)
3567 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3568 +#elif 0
3569 + /*
3570 + * Use this option if you are using the first slot but
3571 + * not the second.
3572 + */
3573 + if ((bus_number == 1) && (devfn >> 3 != 2))
3574 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3575 +#elif 0
3576 + /*
3577 + * Use this option if you are using the second slot
3578 + * but not the first.
3579 + */
3580 + if ((bus_number == 1) && (devfn >> 3 != 3))
3581 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3582 +#elif 0
3583 + /* Use this opion if you are using both slots */
3584 + if ((bus_number == 1) &&
3585 + !((devfn == (2 << 3)) || (devfn == (3 << 3))))
3586 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3587 +#endif
3588 +
3589 + /*
3590 + * The following #if gives a more complicated
3591 + * example. This is the required checks for running a
3592 + * Nitrox CN16XX-NHBX in the slot of the EBH5600. This
3593 + * card has a PLX PCIe bridge with four Nitrox PLX
3594 + * parts behind it.
3595 + */
3596 +#if 0
3597 + /* PLX bridge with 4 ports */
3598 + if ((bus_number == 3) &&
3599 + !((devfn >> 3 >= 1) && (devfn >> 3 <= 4)))
3600 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3601 + /* Nitrox behind PLX 1 */
3602 + if ((bus_number == 4) && (devfn >> 3 != 0))
3603 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3604 + /* Nitrox behind PLX 2 */
3605 + if ((bus_number == 5) && (devfn >> 3 != 0))
3606 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3607 + /* Nitrox behind PLX 3 */
3608 + if ((bus_number == 6) && (devfn >> 3 != 0))
3609 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3610 + /* Nitrox behind PLX 4 */
3611 + if ((bus_number == 7) && (devfn >> 3 != 0))
3612 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3613 +#endif
3614 + /*
3615 + * Shorten the DID timeout so bus errors for PCIe
3616 + * config reads from non existent devices happen
3617 + * faster. This allows us to continue booting even if
3618 + * the above "if" checks are wrong. Once one of these
3619 + * errors happens, the PCIe port is dead.
3620 + */
3621 + cvmmemctl_save.u64 = __read_64bit_c0_register($11, 7);
3622 + cvmmemctl.u64 = cvmmemctl_save.u64;
3623 + cvmmemctl.s.didtto = 2;
3624 + __write_64bit_c0_register($11, 7, cvmmemctl.u64);
3625 + }
3626 +
3627 + switch (size) {
3628 + case 4:
3629 + *val = cvmx_pcie_config_read32(pcie_port, bus_number,
3630 + devfn >> 3, devfn & 0x7, reg);
3631 + break;
3632 + case 2:
3633 + *val = cvmx_pcie_config_read16(pcie_port, bus_number,
3634 + devfn >> 3, devfn & 0x7, reg);
3635 + break;
3636 + case 1:
3637 + *val = cvmx_pcie_config_read8(pcie_port, bus_number, devfn >> 3,
3638 + devfn & 0x7, reg);
3639 + break;
3640 + default:
3641 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3642 + }
3643 +
3644 + if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1) ||
3645 + OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_1))
3646 + __write_64bit_c0_register($11, 7, cvmmemctl_save.u64);
3647 + return PCIBIOS_SUCCESSFUL;
3648 +}
3649 +
3650 +static int octeon_pcie0_read_config(struct pci_bus *bus, unsigned int devfn,
3651 + int reg, int size, u32 *val)
3652 +{
3653 + return octeon_pcie_read_config(0, bus, devfn, reg, size, val);
3654 +}
3655 +
3656 +static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
3657 + int reg, int size, u32 *val)
3658 +{
3659 + return octeon_pcie_read_config(1, bus, devfn, reg, size, val);
3660 +}
3661 +
3662 +
3663 +
3664 +/**
3665 + * Write a value to PCI configuration space
3666 + *
3667 + * @param bus
3668 + * @param devfn
3669 + * @param reg
3670 + * @param size
3671 + * @param val
3672 + * @return
3673 + */
3674 +static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
3675 + unsigned int devfn, int reg,
3676 + int size, u32 val)
3677 +{
3678 + int bus_number = bus->number;
3679 + /*
3680 + * We need to force the bus number to be zero on the root
3681 + * bus. Linux numbers the 2nd root bus to start after all
3682 + * busses on root 0.
3683 + */
3684 + if (bus->parent == NULL)
3685 + bus_number = 0;
3686 +
3687 + switch (size) {
3688 + case 4:
3689 + cvmx_pcie_config_write32(pcie_port, bus_number, devfn >> 3,
3690 + devfn & 0x7, reg, val);
3691 + return PCIBIOS_SUCCESSFUL;
3692 + case 2:
3693 + cvmx_pcie_config_write16(pcie_port, bus_number, devfn >> 3,
3694 + devfn & 0x7, reg, val);
3695 + return PCIBIOS_SUCCESSFUL;
3696 + case 1:
3697 + cvmx_pcie_config_write8(pcie_port, bus_number, devfn >> 3,
3698 + devfn & 0x7, reg, val);
3699 + return PCIBIOS_SUCCESSFUL;
3700 + }
3701 +#if PCI_CONFIG_SPACE_DELAY
3702 + udelay(PCI_CONFIG_SPACE_DELAY);
3703 +#endif
3704 + return PCIBIOS_FUNC_NOT_SUPPORTED;
3705 +}
3706 +
3707 +static int octeon_pcie0_write_config(struct pci_bus *bus, unsigned int devfn,
3708 + int reg, int size, u32 val)
3709 +{
3710 + return octeon_pcie_write_config(0, bus, devfn, reg, size, val);
3711 +}
3712 +
3713 +static int octeon_pcie1_write_config(struct pci_bus *bus, unsigned int devfn,
3714 + int reg, int size, u32 val)
3715 +{
3716 + return octeon_pcie_write_config(1, bus, devfn, reg, size, val);
3717 +}
3718 +
3719 +static struct pci_ops octeon_pcie0_ops = {
3720 + octeon_pcie0_read_config,
3721 + octeon_pcie0_write_config,
3722 +};
3723 +
3724 +static struct resource octeon_pcie0_mem_resource = {
3725 + .name = "Octeon PCIe0 MEM",
3726 + .flags = IORESOURCE_MEM,
3727 +};
3728 +
3729 +static struct resource octeon_pcie0_io_resource = {
3730 + .name = "Octeon PCIe0 IO",
3731 + .flags = IORESOURCE_IO,
3732 +};
3733 +
3734 +static struct pci_controller octeon_pcie0_controller = {
3735 + .pci_ops = &octeon_pcie0_ops,
3736 + .mem_resource = &octeon_pcie0_mem_resource,
3737 + .io_resource = &octeon_pcie0_io_resource,
3738 +};
3739 +
3740 +static struct pci_ops octeon_pcie1_ops = {
3741 + octeon_pcie1_read_config,
3742 + octeon_pcie1_write_config,
3743 +};
3744 +
3745 +static struct resource octeon_pcie1_mem_resource = {
3746 + .name = "Octeon PCIe1 MEM",
3747 + .flags = IORESOURCE_MEM,
3748 +};
3749 +
3750 +static struct resource octeon_pcie1_io_resource = {
3751 + .name = "Octeon PCIe1 IO",
3752 + .flags = IORESOURCE_IO,
3753 +};
3754 +
3755 +static struct pci_controller octeon_pcie1_controller = {
3756 + .pci_ops = &octeon_pcie1_ops,
3757 + .mem_resource = &octeon_pcie1_mem_resource,
3758 + .io_resource = &octeon_pcie1_io_resource,
3759 +};
3760 +
3761 +
3762 +/**
3763 + * Initialize the Octeon PCIe controllers
3764 + *
3765 + * @return
3766 + */
3767 +static int __init octeon_pcie_setup(void)
3768 +{
3769 + union cvmx_npei_ctl_status npei_ctl_status;
3770 + int result;
3771 +
3772 + /* These chips don't have PCIe */
3773 + if (!octeon_has_feature(OCTEON_FEATURE_PCIE))
3774 + return 0;
3775 +
3776 + /* Point pcibios_map_irq() to the PCIe version of it */
3777 + octeon_pcibios_map_irq = octeon_pcie_pcibios_map_irq;
3778 +
3779 + /* Use the PCIe based DMA mappings */
3780 + octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_PCIE;
3781 +
3782 + /*
3783 + * PCIe I/O range. It is based on port 0 but includes up until
3784 + * port 1's end.
3785 + */
3786 + set_io_port_base(CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(0)));
3787 + ioport_resource.start = 0;
3788 + ioport_resource.end =
3789 + cvmx_pcie_get_io_base_address(1) -
3790 + cvmx_pcie_get_io_base_address(0) + cvmx_pcie_get_io_size(1) - 1;
3791 +
3792 + npei_ctl_status.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_CTL_STATUS);
3793 + if (npei_ctl_status.s.host_mode) {
3794 + pr_notice("PCIe: Initializing port 0\n");
3795 + result = cvmx_pcie_rc_initialize(0);
3796 + if (result == 0) {
3797 + /* Memory offsets are physical addresses */
3798 + octeon_pcie0_controller.mem_offset =
3799 + cvmx_pcie_get_mem_base_address(0);
3800 + /* IO offsets are Mips virtual addresses */
3801 + octeon_pcie0_controller.io_map_base =
3802 + CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address
3803 + (0));
3804 + octeon_pcie0_controller.io_offset = 0;
3805 + /*
3806 + * To keep things similar to PCI, we start
3807 + * device addresses at the same place as PCI
3808 + * uisng big bar support. This normally
3809 + * translates to 4GB-256MB, which is the same
3810 + * as most x86 PCs.
3811 + */
3812 + octeon_pcie0_controller.mem_resource->start =
3813 + cvmx_pcie_get_mem_base_address(0) +
3814 + (4ul << 30) - (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3815 + octeon_pcie0_controller.mem_resource->end =
3816 + cvmx_pcie_get_mem_base_address(0) +
3817 + cvmx_pcie_get_mem_size(0) - 1;
3818 + /*
3819 + * Ports must be above 16KB for the ISA bus
3820 + * filtering in the PCI-X to PCI bridge.
3821 + */
3822 + octeon_pcie0_controller.io_resource->start = 4 << 10;
3823 + octeon_pcie0_controller.io_resource->end =
3824 + cvmx_pcie_get_io_size(0) - 1;
3825 + register_pci_controller(&octeon_pcie0_controller);
3826 + }
3827 + } else {
3828 + pr_notice("PCIe: Port 0 in endpoint mode, skipping.\n");
3829 + }
3830 +
3831 + /* Skip the 2nd port on CN52XX if port 0 is in 4 lane mode */
3832 + if (OCTEON_IS_MODEL(OCTEON_CN52XX)) {
3833 + union cvmx_npei_dbg_data npei_dbg_data;
3834 + npei_dbg_data.u64 = cvmx_read_csr(CVMX_PEXP_NPEI_DBG_DATA);
3835 + if (npei_dbg_data.cn52xx.qlm0_link_width)
3836 + return 0;
3837 + }
3838 +
3839 + pr_notice("PCIe: Initializing port 1\n");
3840 + result = cvmx_pcie_rc_initialize(1);
3841 + if (result == 0) {
3842 + /* Memory offsets are physical addresses */
3843 + octeon_pcie1_controller.mem_offset =
3844 + cvmx_pcie_get_mem_base_address(1);
3845 + /* IO offsets are Mips virtual addresses */
3846 + octeon_pcie1_controller.io_map_base =
3847 + CVMX_ADD_IO_SEG(cvmx_pcie_get_io_base_address(1));
3848 + octeon_pcie1_controller.io_offset =
3849 + cvmx_pcie_get_io_base_address(1) -
3850 + cvmx_pcie_get_io_base_address(0);
3851 + /*
3852 + * To keep things similar to PCI, we start device
3853 + * addresses at the same place as PCI uisng big bar
3854 + * support. This normally translates to 4GB-256MB,
3855 + * which is the same as most x86 PCs.
3856 + */
3857 + octeon_pcie1_controller.mem_resource->start =
3858 + cvmx_pcie_get_mem_base_address(1) + (4ul << 30) -
3859 + (OCTEON_PCI_BAR1_HOLE_SIZE << 20);
3860 + octeon_pcie1_controller.mem_resource->end =
3861 + cvmx_pcie_get_mem_base_address(1) +
3862 + cvmx_pcie_get_mem_size(1) - 1;
3863 + /*
3864 + * Ports must be above 16KB for the ISA bus filtering
3865 + * in the PCI-X to PCI bridge.
3866 + */
3867 + octeon_pcie1_controller.io_resource->start =
3868 + cvmx_pcie_get_io_base_address(1) -
3869 + cvmx_pcie_get_io_base_address(0);
3870 + octeon_pcie1_controller.io_resource->end =
3871 + octeon_pcie1_controller.io_resource->start +
3872 + cvmx_pcie_get_io_size(1) - 1;
3873 + register_pci_controller(&octeon_pcie1_controller);
3874 + }
3875 + return 0;
3876 +}
3877 +
3878 +arch_initcall(octeon_pcie_setup);
3879 diff --git a/arch/mips/include/asm/octeon/cvmx-asm.h b/arch/mips/include/asm/octeon/cvmx-asm.h
3880 index b21d3fc..093bcaf 100644
3881 --- a/arch/mips/include/asm/octeon/cvmx-asm.h
3882 +++ b/arch/mips/include/asm/octeon/cvmx-asm.h
3883 @@ -119,7 +119,8 @@
3884 asm ("pop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3885 #define CVMX_DPOP(result, input) \
3886 asm ("dpop %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3887 -
3888 +#define CVMX_CLZ(result, input) \
3889 + asm ("clz %[rd],%[rs]" : [rd] "=d" (result) : [rs] "d" (input))
3890 /* some new cop0-like stuff */
3891 #define CVMX_RDHWR(result, regstr) \
3892 asm volatile ("rdhwr %[rt],$" CVMX_TMP_STR(regstr) : [rt] "=d" (result))
3893 diff --git a/arch/mips/include/asm/octeon/cvmx-helper-errata.h b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
3894 new file mode 100644
3895 index 0000000..ce5deea
3896 --- /dev/null
3897 +++ b/arch/mips/include/asm/octeon/cvmx-helper-errata.h
3898 @@ -0,0 +1,92 @@
3899 +/***********************license start***************
3900 + * Author: Cavium Networks
3901 + *
3902 + * Contact: support@caviumnetworks.com
3903 + * This file is part of the OCTEON SDK
3904 + *
3905 + * Copyright (c) 2003-2008 Cavium Networks
3906 + *
3907 + * This file is free software; you can redistribute it and/or modify
3908 + * it under the terms of the GNU General Public License, Version 2, as
3909 + * published by the Free Software Foundation.
3910 + *
3911 + * This file is distributed in the hope that it will be useful, but
3912 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
3913 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
3914 + * NONINFRINGEMENT. See the GNU General Public License for more
3915 + * details.
3916 + *
3917 + * You should have received a copy of the GNU General Public License
3918 + * along with this file; if not, write to the Free Software
3919 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
3920 + * or visit http://www.gnu.org/licenses/.
3921 + *
3922 + * This file may also be available under a different license from Cavium.
3923 + * Contact Cavium Networks for more information
3924 + ***********************license end**************************************/
3925 +
3926 +/**
3927 + * @file
3928 + *
3929 + * Fixes and workaround for Octeon chip errata. This file
3930 + * contains functions called by cvmx-helper to workaround known
3931 + * chip errata. For the most part, code doesn't need to call
3932 + * these functions directly.
3933 + *
3934 + */
3935 +#ifndef __CVMX_HELPER_ERRATA_H__
3936 +#define __CVMX_HELPER_ERRATA_H__
3937 +
3938 +
3939 +#include "cvmx-wqe.h"
3940 +
3941 +/**
3942 + * @INTERNAL
3943 + * Function to adjust internal IPD pointer alignments
3944 + *
3945 + * Returns 0 on success
3946 + * !0 on failure
3947 + */
3948 +extern int __cvmx_helper_errata_fix_ipd_ptr_alignment(void);
3949 +
3950 +/**
3951 + * @INTERNAL
3952 + * Workaround ASX setup errata with CN38XX pass1
3953 + *
3954 + * @interface: Interface to setup
3955 + * @port: Port to setup (0..3)
3956 + * @cpu_clock_hz:
3957 + * Chip frequency in Hertz
3958 + *
3959 + * Returns Zero on success, negative on failure
3960 + */
3961 +extern int __cvmx_helper_errata_asx_pass1(int interface, int port,
3962 + int cpu_clock_hz);
3963 +
3964 +/**
3965 + * This function needs to be called on all Octeon chips with
3966 + * errata PKI-100.
3967 + *
3968 + * The Size field is 8 too large in WQE and next pointers
3969 + *
3970 + * The Size field generated by IPD is 8 larger than it should
3971 + * be. The Size field is <55:40> of both:
3972 + * - WORD3 in the work queue entry, and
3973 + * - the next buffer pointer (which precedes the packet data
3974 + * in each buffer).
3975 + *
3976 + * @work: Work queue entry to fix
3977 + * Returns Zero on success. Negative on failure
3978 + */
3979 +extern int cvmx_helper_fix_ipd_packet_chain(struct cvmx_wqe *work);
3980 +
3981 +/**
3982 + * Due to errata G-720, the 2nd order CDR circuit on CN52XX pass
3983 + * 1 doesn't work properly. The following code disables 2nd order
3984 + * CDR for the specified QLM.
3985 + *
3986 + * @qlm: QLM to disable 2nd order CDR for.
3987 + */
3988 +extern void __cvmx_helper_errata_qlm_disable_2nd_order_cdr(int qlm);
3989 +
3990 +#endif
3991 diff --git a/arch/mips/include/asm/octeon/cvmx-helper-util.h b/arch/mips/include/asm/octeon/cvmx-helper-util.h
3992 new file mode 100644
3993 index 0000000..d720217
3994 --- /dev/null
3995 +++ b/arch/mips/include/asm/octeon/cvmx-helper-util.h
3996 @@ -0,0 +1,266 @@
3997 +/***********************license start***************
3998 + * Author: Cavium Networks
3999 + *
4000 + * Contact: support@caviumnetworks.com
4001 + * This file is part of the OCTEON SDK
4002 + *
4003 + * Copyright (c) 2003-2008 Cavium Networks
4004 + *
4005 + * This file is free software; you can redistribute it and/or modify
4006 + * it under the terms of the GNU General Public License, Version 2, as
4007 + * published by the Free Software Foundation.
4008 + *
4009 + * This file is distributed in the hope that it will be useful, but
4010 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4011 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4012 + * NONINFRINGEMENT. See the GNU General Public License for more
4013 + * details.
4014 + *
4015 + * You should have received a copy of the GNU General Public License
4016 + * along with this file; if not, write to the Free Software
4017 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4018 + * or visit http://www.gnu.org/licenses/.
4019 + *
4020 + * This file may also be available under a different license from Cavium.
4021 + * Contact Cavium Networks for more information
4022 + ***********************license end**************************************/
4023 +
4024 +/**
4025 + *
4026 + * Small helper utilities.
4027 + *
4028 + */
4029 +
4030 +#ifndef __CVMX_HELPER_UTIL_H__
4031 +#define __CVMX_HELPER_UTIL_H__
4032 +
4033 +#ifdef CVMX_ENABLE_HELPER_FUNCTIONS
4034 +
4035 +/**
4036 + * Convert a interface mode into a human readable string
4037 + *
4038 + * @mode: Mode to convert
4039 + *
4040 + * Returns String
4041 + */
4042 +extern const char
4043 + *cvmx_helper_interface_mode_to_string(cvmx_helper_interface_mode_t mode);
4044 +
4045 +/**
4046 + * Debug routine to dump the packet structure to the console
4047 + *
4048 + * @work: Work queue entry containing the packet to dump
4049 + * Returns
4050 + */
4051 +extern int cvmx_helper_dump_packet(cvmx_wqe_t *work);
4052 +
4053 +/**
4054 + * Setup Random Early Drop on a specific input queue
4055 + *
4056 + * @queue: Input queue to setup RED on (0-7)
4057 + * @pass_thresh:
4058 + * Packets will begin slowly dropping when there are less than
4059 + * this many packet buffers free in FPA 0.
4060 + * @drop_thresh:
4061 + * All incomming packets will be dropped when there are less
4062 + * than this many free packet buffers in FPA 0.
4063 + * Returns Zero on success. Negative on failure
4064 + */
4065 +extern int cvmx_helper_setup_red_queue(int queue, int pass_thresh,
4066 + int drop_thresh);
4067 +
4068 +/**
4069 + * Setup Random Early Drop to automatically begin dropping packets.
4070 + *
4071 + * @pass_thresh:
4072 + * Packets will begin slowly dropping when there are less than
4073 + * this many packet buffers free in FPA 0.
4074 + * @drop_thresh:
4075 + * All incomming packets will be dropped when there are less
4076 + * than this many free packet buffers in FPA 0.
4077 + * Returns Zero on success. Negative on failure
4078 + */
4079 +extern int cvmx_helper_setup_red(int pass_thresh, int drop_thresh);
4080 +
4081 +/**
4082 + * Get the version of the CVMX libraries.
4083 + *
4084 + * Returns Version string. Note this buffer is allocated statically
4085 + * and will be shared by all callers.
4086 + */
4087 +extern const char *cvmx_helper_get_version(void);
4088 +
4089 +/**
4090 + * @INTERNAL
4091 + * Setup the common GMX settings that determine the number of
4092 + * ports. These setting apply to almost all configurations of all
4093 + * chips.
4094 + *
4095 + * @interface: Interface to configure
4096 + * @num_ports: Number of ports on the interface
4097 + *
4098 + * Returns Zero on success, negative on failure
4099 + */
4100 +extern int __cvmx_helper_setup_gmx(int interface, int num_ports);
4101 +
4102 +/**
4103 + * Returns the IPD/PKO port number for a port on the given
4104 + * interface.
4105 + *
4106 + * @interface: Interface to use
4107 + * @port: Port on the interface
4108 + *
4109 + * Returns IPD/PKO port number
4110 + */
4111 +extern int cvmx_helper_get_ipd_port(int interface, int port);
4112 +
4113 +/**
4114 + * Returns the IPD/PKO port number for the first port on the given
4115 + * interface.
4116 + *
4117 + * @interface: Interface to use
4118 + *
4119 + * Returns IPD/PKO port number
4120 + */
4121 +static inline int cvmx_helper_get_first_ipd_port(int interface)
4122 +{
4123 + return cvmx_helper_get_ipd_port(interface, 0);
4124 +}
4125 +
4126 +/**
4127 + * Returns the IPD/PKO port number for the last port on the given
4128 + * interface.
4129 + *
4130 + * @interface: Interface to use
4131 + *
4132 + * Returns IPD/PKO port number
4133 + */
4134 +static inline int cvmx_helper_get_last_ipd_port(int interface)
4135 +{
4136 + extern int cvmx_helper_ports_on_interface(int interface);
4137 +
4138 + return cvmx_helper_get_first_ipd_port(interface) +
4139 + cvmx_helper_ports_on_interface(interface) - 1;
4140 +}
4141 +
4142 +/**
4143 + * Free the packet buffers contained in a work queue entry.
4144 + * The work queue entry is not freed.
4145 + *
4146 + * @work: Work queue entry with packet to free
4147 + */
4148 +static inline void cvmx_helper_free_packet_data(cvmx_wqe_t *work)
4149 +{
4150 + uint64_t number_buffers;
4151 + cvmx_buf_ptr_t buffer_ptr;
4152 + cvmx_buf_ptr_t next_buffer_ptr;
4153 + uint64_t start_of_buffer;
4154 +
4155 + number_buffers = work->word2.s.bufs;
4156 + if (number_buffers == 0)
4157 + return;
4158 + buffer_ptr = work->packet_ptr;
4159 +
4160 + /*
4161 + * Since the number of buffers is not zero, we know this is
4162 + * not a dynamic short packet. We need to check if it is a
4163 + * packet received with IPD_CTL_STATUS[NO_WPTR]. If this is
4164 + * true, we need to free all buffers except for the first
4165 + * one. The caller doesn't expect their WQE pointer to be
4166 + * freed.
4167 + */
4168 + start_of_buffer = ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
4169 + if (cvmx_ptr_to_phys(work) == start_of_buffer) {
4170 + next_buffer_ptr =
4171 + *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
4172 + buffer_ptr = next_buffer_ptr;
4173 + number_buffers--;
4174 + }
4175 +
4176 + while (number_buffers--) {
4177 + /*
4178 + * Remember the back pointer is in cache lines, not
4179 + * 64bit words.
4180 + */
4181 + start_of_buffer =
4182 + ((buffer_ptr.s.addr >> 7) - buffer_ptr.s.back) << 7;
4183 + /*
4184 + * Read pointer to next buffer before we free the
4185 + * current buffer.
4186 + */
4187 + next_buffer_ptr =
4188 + *(cvmx_buf_ptr_t *) cvmx_phys_to_ptr(buffer_ptr.s.addr - 8);
4189 + cvmx_fpa_free(cvmx_phys_to_ptr(start_of_buffer),
4190 + buffer_ptr.s.pool, 0);
4191 + buffer_ptr = next_buffer_ptr;
4192 + }
4193 +}
4194 +
4195 +#endif /* CVMX_ENABLE_HELPER_FUNCTIONS */
4196 +
4197 +/**
4198 + * Returns the interface number for an IPD/PKO port number.
4199 + *
4200 + * @ipd_port: IPD/PKO port number
4201 + *
4202 + * Returns Interface number
4203 + */
4204 +extern int cvmx_helper_get_interface_num(int ipd_port);
4205 +
4206 +/**
4207 + * Returns the interface index number for an IPD/PKO port
4208 + * number.
4209 + *
4210 + * @ipd_port: IPD/PKO port number
4211 + *
4212 + * Returns Interface index number
4213 + */
4214 +extern int cvmx_helper_get_interface_index_num(int ipd_port);
4215 +
4216 +/**
4217 + * Initialize the internal QLM JTAG logic to allow programming
4218 + * of the JTAG chain by the cvmx_helper_qlm_jtag_*() functions.
4219 + * These functions should only be used at the direction of Cavium
4220 + * Networks. Programming incorrect values into the JTAG chain
4221 + * can cause chip damage.
4222 + */
4223 +extern void cvmx_helper_qlm_jtag_init(void);
4224 +
4225 +/**
4226 + * Write up to 32bits into the QLM jtag chain. Bits are shifted
4227 + * into the MSB and out the LSB, so you should shift in the low
4228 + * order bits followed by the high order bits. The JTAG chain is
4229 + * 4 * 268 bits long, or 1072.
4230 + *
4231 + * @qlm: QLM to shift value into
4232 + * @bits: Number of bits to shift in (1-32).
4233 + * @data: Data to shift in. Bit 0 enters the chain first, followed by
4234 + * bit 1, etc.
4235 + *
4236 + * Returns The low order bits of the JTAG chain that shifted out of the
4237 + * circle.
4238 + */
4239 +extern uint32_t cvmx_helper_qlm_jtag_shift(int qlm, int bits, uint32_t data);
4240 +
4241 +/**
4242 + * Shift long sequences of zeros into the QLM JTAG chain. It is
4243 + * common to need to shift more than 32 bits of zeros into the
4244 + * chain. This function is a convience wrapper around
4245 + * cvmx_helper_qlm_jtag_shift() to shift more than 32 bits of
4246 + * zeros at a time.
4247 + *
4248 + * @qlm: QLM to shift zeros into
4249 + * @bits:
4250 + */
4251 +extern void cvmx_helper_qlm_jtag_shift_zeros(int qlm, int bits);
4252 +
4253 +/**
4254 + * Program the QLM JTAG chain into all lanes of the QLM. You must
4255 + * have already shifted in 268*4, or 1072 bits into the JTAG
4256 + * chain. Updating invalid values can possibly cause chip damage.
4257 + *
4258 + * @qlm: QLM to program
4259 + */
4260 +extern void cvmx_helper_qlm_jtag_update(int qlm);
4261 +
4262 +#endif /* __CVMX_HELPER_H__ */
4263 diff --git a/arch/mips/include/asm/octeon/cvmx-packet.h b/arch/mips/include/asm/octeon/cvmx-packet.h
4264 index 38aefa1..1cb3419 100644
4265 --- a/arch/mips/include/asm/octeon/cvmx-packet.h
4266 +++ b/arch/mips/include/asm/octeon/cvmx-packet.h
4267 @@ -25,7 +25,8 @@
4268 * Contact Cavium Networks for more information
4269 ***********************license end**************************************/
4270
4271 -/*
4272 +/**
4273 + *
4274 * Packet buffer defines.
4275 */
4276
4277 @@ -39,18 +40,23 @@ union cvmx_buf_ptr {
4278 void *ptr;
4279 uint64_t u64;
4280 struct {
4281 - /* if set, invert the "free" pick of the overall
4282 + /*
4283 + * If set, invert the "free" pick of the overall
4284 * packet. HW always sets this bit to 0 on inbound
4285 - * packet */
4286 + * packet.
4287 + */
4288 uint64_t i:1;
4289
4290 - /* Indicates the amount to back up to get to the
4291 + /*
4292 + * Indicates the amount to back up to get to the
4293 * buffer start in cache lines. In most cases this is
4294 * less than one complete cache line, so the value is
4295 - * zero */
4296 + * zero.
4297 + */
4298 uint64_t back:4;
4299 /* The pool that the buffer came from / goes to */
4300 uint64_t pool:3;
4301 +
4302 /* The size of the segment pointed to by addr (in bytes) */
4303 uint64_t size:16;
4304 /* Pointer to the first byte of the data, NOT buffer */
4305 diff --git a/arch/mips/include/asm/octeon/cvmx-pcie.h b/arch/mips/include/asm/octeon/cvmx-pcie.h
4306 new file mode 100644
4307 index 0000000..55a5ac1
4308 --- /dev/null
4309 +++ b/arch/mips/include/asm/octeon/cvmx-pcie.h
4310 @@ -0,0 +1,284 @@
4311 +/***********************license start***************
4312 + * Author: Cavium Networks
4313 + *
4314 + * Contact: support@caviumnetworks.com
4315 + * This file is part of the OCTEON SDK
4316 + *
4317 + * Copyright (c) 2003-2008 Cavium Networks
4318 + *
4319 + * This file is free software; you can redistribute it and/or modify
4320 + * it under the terms of the GNU General Public License, Version 2, as
4321 + * published by the Free Software Foundation.
4322 + *
4323 + * This file is distributed in the hope that it will be useful, but
4324 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4325 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4326 + * NONINFRINGEMENT. See the GNU General Public License for more
4327 + * details.
4328 + *
4329 + * You should have received a copy of the GNU General Public License
4330 + * along with this file; if not, write to the Free Software
4331 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4332 + * or visit http://www.gnu.org/licenses/.
4333 + *
4334 + * This file may also be available under a different license from Cavium.
4335 + * Contact Cavium Networks for more information
4336 + ***********************license end**************************************/
4337 +
4338 +/**
4339 + * @file
4340 + *
4341 + * Interface to PCIe as a host(RC) or target(EP)
4342 + *
4343 + */
4344 +
4345 +#ifndef __CVMX_PCIE_H__
4346 +#define __CVMX_PCIE_H__
4347 +
4348 +union cvmx_pcie_address {
4349 + uint64_t u64;
4350 + struct {
4351 + uint64_t upper:2; /* Normally 2 for XKPHYS */
4352 + uint64_t reserved_49_61:13; /* Must be zero */
4353 + uint64_t io:1; /* 1 for IO space access */
4354 + uint64_t did:5; /* PCIe DID = 3 */
4355 + uint64_t subdid:3; /* PCIe SubDID = 1 */
4356 + uint64_t reserved_36_39:4; /* Must be zero */
4357 + uint64_t es:2; /* Endian swap = 1 */
4358 + uint64_t port:2; /* PCIe port 0,1 */
4359 + uint64_t reserved_29_31:3; /* Must be zero */
4360 + /*
4361 + * Selects the type of the configuration request (0 = type 0,
4362 + * 1 = type 1).
4363 + */
4364 + uint64_t ty:1;
4365 + /* Target bus number sent in the ID in the request. */
4366 + uint64_t bus:8;
4367 + /*
4368 + * Target device number sent in the ID in the
4369 + * request. Note that Dev must be zero for type 0
4370 + * configuration requests.
4371 + */
4372 + uint64_t dev:5;
4373 + /* Target function number sent in the ID in the request. */
4374 + uint64_t func:3;
4375 + /*
4376 + * Selects a register in the configuration space of
4377 + * the target.
4378 + */
4379 + uint64_t reg:12;
4380 + } config;
4381 + struct {
4382 + uint64_t upper:2; /* Normally 2 for XKPHYS */
4383 + uint64_t reserved_49_61:13; /* Must be zero */
4384 + uint64_t io:1; /* 1 for IO space access */
4385 + uint64_t did:5; /* PCIe DID = 3 */
4386 + uint64_t subdid:3; /* PCIe SubDID = 2 */
4387 + uint64_t reserved_36_39:4; /* Must be zero */
4388 + uint64_t es:2; /* Endian swap = 1 */
4389 + uint64_t port:2; /* PCIe port 0,1 */
4390 + uint64_t address:32; /* PCIe IO address */
4391 + } io;
4392 + struct {
4393 + uint64_t upper:2; /* Normally 2 for XKPHYS */
4394 + uint64_t reserved_49_61:13; /* Must be zero */
4395 + uint64_t io:1; /* 1 for IO space access */
4396 + uint64_t did:5; /* PCIe DID = 3 */
4397 + uint64_t subdid:3; /* PCIe SubDID = 3-6 */
4398 + uint64_t reserved_36_39:4; /* Must be zero */
4399 + uint64_t address:36; /* PCIe Mem address */
4400 + } mem;
4401 +};
4402 +
4403 +/**
4404 + * Return the Core virtual base address for PCIe IO access. IOs are
4405 + * read/written as an offset from this address.
4406 + *
4407 + * @pcie_port: PCIe port the IO is for
4408 + *
4409 + * Returns 64bit Octeon IO base address for read/write
4410 + */
4411 +uint64_t cvmx_pcie_get_io_base_address(int pcie_port);
4412 +
4413 +/**
4414 + * Size of the IO address region returned at address
4415 + * cvmx_pcie_get_io_base_address()
4416 + *
4417 + * @pcie_port: PCIe port the IO is for
4418 + *
4419 + * Returns Size of the IO window
4420 + */
4421 +uint64_t cvmx_pcie_get_io_size(int pcie_port);
4422 +
4423 +/**
4424 + * Return the Core virtual base address for PCIe MEM access. Memory is
4425 + * read/written as an offset from this address.
4426 + *
4427 + * @pcie_port: PCIe port the IO is for
4428 + *
4429 + * Returns 64bit Octeon IO base address for read/write
4430 + */
4431 +uint64_t cvmx_pcie_get_mem_base_address(int pcie_port);
4432 +
4433 +/**
4434 + * Size of the Mem address region returned at address
4435 + * cvmx_pcie_get_mem_base_address()
4436 + *
4437 + * @pcie_port: PCIe port the IO is for
4438 + *
4439 + * Returns Size of the Mem window
4440 + */
4441 +uint64_t cvmx_pcie_get_mem_size(int pcie_port);
4442 +
4443 +/**
4444 + * Initialize a PCIe port for use in host(RC) mode. It doesn't
4445 + * enumerate the bus.
4446 + *
4447 + * @pcie_port: PCIe port to initialize
4448 + *
4449 + * Returns Zero on success
4450 + */
4451 +int cvmx_pcie_rc_initialize(int pcie_port);
4452 +
4453 +/**
4454 + * Shutdown a PCIe port and put it in reset
4455 + *
4456 + * @pcie_port: PCIe port to shutdown
4457 + *
4458 + * Returns Zero on success
4459 + */
4460 +int cvmx_pcie_rc_shutdown(int pcie_port);
4461 +
4462 +/**
4463 + * Read 8bits from a Device's config space
4464 + *
4465 + * @pcie_port: PCIe port the device is on
4466 + * @bus: Sub bus
4467 + * @dev: Device ID
4468 + * @fn: Device sub function
4469 + * @reg: Register to access
4470 + *
4471 + * Returns Result of the read
4472 + */
4473 +uint8_t cvmx_pcie_config_read8(int pcie_port, int bus, int dev, int fn,
4474 + int reg);
4475 +
4476 +/**
4477 + * Read 16bits from a Device's config space
4478 + *
4479 + * @pcie_port: PCIe port the device is on
4480 + * @bus: Sub bus
4481 + * @dev: Device ID
4482 + * @fn: Device sub function
4483 + * @reg: Register to access
4484 + *
4485 + * Returns Result of the read
4486 + */
4487 +uint16_t cvmx_pcie_config_read16(int pcie_port, int bus, int dev, int fn,
4488 + int reg);
4489 +
4490 +/**
4491 + * Read 32bits from a Device's config space
4492 + *
4493 + * @pcie_port: PCIe port the device is on
4494 + * @bus: Sub bus
4495 + * @dev: Device ID
4496 + * @fn: Device sub function
4497 + * @reg: Register to access
4498 + *
4499 + * Returns Result of the read
4500 + */
4501 +uint32_t cvmx_pcie_config_read32(int pcie_port, int bus, int dev, int fn,
4502 + int reg);
4503 +
4504 +/**
4505 + * Write 8bits to a Device's config space
4506 + *
4507 + * @pcie_port: PCIe port the device is on
4508 + * @bus: Sub bus
4509 + * @dev: Device ID
4510 + * @fn: Device sub function
4511 + * @reg: Register to access
4512 + * @val: Value to write
4513 + */
4514 +void cvmx_pcie_config_write8(int pcie_port, int bus, int dev, int fn, int reg,
4515 + uint8_t val);
4516 +
4517 +/**
4518 + * Write 16bits to a Device's config space
4519 + *
4520 + * @pcie_port: PCIe port the device is on
4521 + * @bus: Sub bus
4522 + * @dev: Device ID
4523 + * @fn: Device sub function
4524 + * @reg: Register to access
4525 + * @val: Value to write
4526 + */
4527 +void cvmx_pcie_config_write16(int pcie_port, int bus, int dev, int fn, int reg,
4528 + uint16_t val);
4529 +
4530 +/**
4531 + * Write 32bits to a Device's config space
4532 + *
4533 + * @pcie_port: PCIe port the device is on
4534 + * @bus: Sub bus
4535 + * @dev: Device ID
4536 + * @fn: Device sub function
4537 + * @reg: Register to access
4538 + * @val: Value to write
4539 + */
4540 +void cvmx_pcie_config_write32(int pcie_port, int bus, int dev, int fn, int reg,
4541 + uint32_t val);
4542 +
4543 +/**
4544 + * Read a PCIe config space register indirectly. This is used for
4545 + * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
4546 + *
4547 + * @pcie_port: PCIe port to read from
4548 + * @cfg_offset: Address to read
4549 + *
4550 + * Returns Value read
4551 + */
4552 +uint32_t cvmx_pcie_cfgx_read(int pcie_port, uint32_t cfg_offset);
4553 +
4554 +/**
4555 + * Write a PCIe config space register indirectly. This is used for
4556 + * registers of the form PCIEEP_CFG??? and PCIERC?_CFG???.
4557 + *
4558 + * @pcie_port: PCIe port to write to
4559 + * @cfg_offset: Address to write
4560 + * @val: Value to write
4561 + */
4562 +void cvmx_pcie_cfgx_write(int pcie_port, uint32_t cfg_offset, uint32_t val);
4563 +
4564 +/**
4565 + * Write a 32bit value to the Octeon NPEI register space
4566 + *
4567 + * @address: Address to write to
4568 + * @val: Value to write
4569 + */
4570 +static inline void cvmx_pcie_npei_write32(uint64_t address, uint32_t val)
4571 +{
4572 + cvmx_write64_uint32(address ^ 4, val);
4573 + cvmx_read64_uint32(address ^ 4);
4574 +}
4575 +
4576 +/**
4577 + * Read a 32bit value from the Octeon NPEI register space
4578 + *
4579 + * @address: Address to read
4580 + * Returns The result
4581 + */
4582 +static inline uint32_t cvmx_pcie_npei_read32(uint64_t address)
4583 +{
4584 + return cvmx_read64_uint32(address ^ 4);
4585 +}
4586 +
4587 +/**
4588 + * Initialize a PCIe port for use in target(EP) mode.
4589 + *
4590 + * Returns Zero on success
4591 + */
4592 +int cvmx_pcie_ep_initialize(void);
4593 +
4594 +#endif
4595 diff --git a/arch/mips/include/asm/octeon/cvmx-wqe.h b/arch/mips/include/asm/octeon/cvmx-wqe.h
4596 new file mode 100644
4597 index 0000000..fadc700
4598 --- /dev/null
4599 +++ b/arch/mips/include/asm/octeon/cvmx-wqe.h
4600 @@ -0,0 +1,422 @@
4601 +/***********************license start***************
4602 + * Author: Cavium Networks
4603 + *
4604 + * Contact: support@caviumnetworks.com
4605 + * This file is part of the OCTEON SDK
4606 + *
4607 + * Copyright (c) 2003-2008 Cavium Networks
4608 + *
4609 + * This file is free software; you can redistribute it and/or modify
4610 + * it under the terms of the GNU General Public License, Version 2, as
4611 + * published by the Free Software Foundation.
4612 + *
4613 + * This file is distributed in the hope that it will be useful, but
4614 + * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
4615 + * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, TITLE, or
4616 + * NONINFRINGEMENT. See the GNU General Public License for more
4617 + * details.
4618 + *
4619 + * You should have received a copy of the GNU General Public License
4620 + * along with this file; if not, write to the Free Software
4621 + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
4622 + * or visit http://www.gnu.org/licenses/.
4623 + *
4624 + * This file may also be available under a different license from Cavium.
4625 + * Contact Cavium Networks for more information
4626 + ***********************license end**************************************/
4627 +
4628 +/**
4629 + *
4630 + * This header file defines the work queue entry (wqe) data structure.
4631 + * Since this is a commonly used structure that depends on structures
4632 + * from several hardware blocks, those definitions have been placed
4633 + * in this file to create a single point of definition of the wqe
4634 + * format.
4635 + *
4636 + * Data structures are still named according to the block that they
4637 + * relate to.
4638 + *
4639 + */
4640 +
4641 +#ifndef __CVMX_WQE_H__
4642 +#define __CVMX_WQE_H__
4643 +
4644 +#include "cvmx-packet.h"
4645 +
4646 +#define OCT_TAG_TYPE_STRING(x) ( \
4647 + { \
4648 + const char *r; \
4649 + switch (x) { \
4650 + case CVMX_POW_TAG_TYPE_ORDERED: \
4651 + r = "ORDERED"; \
4652 + break; \
4653 + case CVMX_POW_TAG_TYPE_ATOMIC: \
4654 + r = "ATOMIC"; \
4655 + break; \
4656 + case CVMX_POW_TAG_TYPE_NULL: \
4657 + r = "NULL"; \
4658 + break; \
4659 + default: \
4660 + r = "NULL_NULL"; \
4661 + break; \
4662 + } \
4663 + r; \
4664 + })
4665 +
4666 +/**
4667 + * HW decode / err_code in work queue entry
4668 + */
4669 +union cvmx_pip_wqe_word2{
4670 + uint64_t u64;
4671 +
4672 + /* Use this struct if the hardware determines that the packet is IP */
4673 + struct {
4674 + /* HW sets this to the number of buffers used by this packet */
4675 + uint64_t bufs:8;
4676 + /* HW sets to the number of L2 bytes prior to the IP */
4677 + uint64_t ip_offset:8;
4678 + /* Set to 1 if we found VLAN in the L2 */
4679 + uint64_t vlan_valid:1;
4680 + uint64_t unassigned:2;
4681 + /* HW sets to the VLAN CFI flag (valid when vlan_valid) */
4682 + uint64_t vlan_cfi:1;
4683 + /* HW sets to the VLAN_ID field (valid when vlan_valid) */
4684 + uint64_t vlan_id:12;
4685 +
4686 + uint64_t unassigned2:12;
4687 + /* The packet needs to be decompressed */
4688 + uint64_t dec_ipcomp:1;
4689 + /* The packet is either TCP or UDP */
4690 + uint64_t tcp_or_udp:1;
4691 + /* The packet needs to be decrypted (ESP or AH) */
4692 + uint64_t dec_ipsec:1;
4693 + /* The packet is IPv6 */
4694 + uint64_t is_v6:1;
4695 +
4696 + /*
4697 + * rcv_error, not_IP, IP_exc, is_frag, L4_error,
4698 + * software, etc.
4699 + */
4700 +
4701 + /*
4702 + * Reserved for software use, hardware will clear on
4703 + * packet creation.
4704 + */
4705 + uint64_t software:1;
4706 + /* exceptional conditions below. */
4707 +
4708 + /*
4709 + * The receive interface hardware detected an L4 error
4710 + * (only applies if !is_frag) (only applies if
4711 + * !rcv_error && !not_IP && !IP_exc && !is_frag)
4712 + * failure indicated in err_code below, decode:
4713 + *
4714 + * - 1 = Malformed L4
4715 + *
4716 + * - 2 = L4 Checksum Error: the L4 checksum value is
4717 + *
4718 + * - 3 = UDP Length Error: The UDP length field would
4719 + * make the UDP data longer than what remains in
4720 + * the IP packet (as defined by the IP header
4721 + * length field).
4722 + *
4723 + * - 4 = Bad L4 Port: either the source or destination
4724 + * TCP/UDP port is 0.
4725 + *
4726 + * - 8 = TCP FIN Only: the packet is TCP and only the
4727 + * FIN flag set.
4728 + *
4729 + * - 9 = TCP No Flags: the packet is TCP and no flags
4730 + * are set.
4731 + *
4732 + * - 10 = TCP FIN RST: the packet is TCP and both FIN
4733 + * and RST are set.
4734 + *
4735 + * - 11 = TCP SYN URG: the packet is TCP and both SYN
4736 + * and URG are set.
4737 + *
4738 + * - 12 = TCP SYN RST: the packet is TCP and both SYN
4739 + * and RST are set.
4740 + *
4741 + * - 13 = TCP SYN FIN: the packet is TCP and both SYN
4742 + * and FIN are set.
4743 + *
4744 + */
4745 + uint64_t L4_error:1;
4746 + /* Set if the packet is a fragment */
4747 + uint64_t is_frag:1;
4748 +
4749 + /*
4750 + * The receive interface hardware detected an IP error
4751 + * / exception (only applies if !rcv_error && !not_IP)
4752 + * failure indicated in err_code below, decode:
4753 + *
4754 + * - 1 = Not IP: the IP version field is neither 4 nor
4755 + * 6.
4756 + *
4757 + * - 2 = IPv4 Header Checksum Error: the IPv4 header
4758 + * has a checksum violation.
4759 + *
4760 + * - 3 = IP Malformed Header: the packet is not long
4761 + * enough to contain the IP header.
4762 + *
4763 + * - 4 = IP Malformed: the packet is not long enough
4764 + * to contain the bytes indicated by the IP
4765 + * header. Pad is allowed.
4766 + *
4767 + * - 5 = IP TTL Hop: the IPv4 TTL field or the IPv6
4768 + * Hop Count field are zero.
4769 + *
4770 + * - 6 = IP Options.
4771 + */
4772 + uint64_t IP_exc:1;
4773 + /*
4774 + * Set if the hardware determined that the packet is a
4775 + * broadcast.
4776 + */
4777 + uint64_t is_bcast:1;
4778 + /*
4779 + * Set if the hardware determined that the packet is a
4780 + * multi-cast.
4781 + */
4782 + uint64_t is_mcast:1;
4783 + /*
4784 + * Set if the packet may not be IP (must be zero in
4785 + * this case).
4786 + */
4787 + uint64_t not_IP:1;
4788 + /*
4789 + * The receive interface hardware detected a receive
4790 + * error (must be zero in this case)
4791 + *
4792 + * lower err_code = first-level descriptor of the work
4793 + *
4794 + * zero for packet submitted by hardware that isn't on
4795 + * the slow path.
4796 + */
4797 + uint64_t rcv_error:1;
4798 +
4799 + /* Type is cvmx_pip_err_t */
4800 + uint64_t err_code:8;
4801 + } s;
4802 +
4803 + /* Use this to get at the 16 vlan bits */
4804 + struct {
4805 + uint64_t unused1:16;
4806 + uint64_t vlan:16;
4807 + uint64_t unused2:32;
4808 + } svlan;
4809 +
4810 + /*
4811 + * Use this struct if the hardware could not determine that
4812 + * the packet is ip.
4813 + */
4814 + struct {
4815 + /* HW sets this to the number of buffers used by this packet. */
4816 + uint64_t bufs:8;
4817 + uint64_t unused:8;
4818 + /* Set to 1 if we found VLAN in the L2. */
4819 + uint64_t vlan_valid:1;
4820 + uint64_t unassigned:2;
4821 + /* HW sets to the VLAN CFI flag (valid when vlan_valid). */
4822 + uint64_t vlan_cfi:1;
4823 + /* HW sets to the VLAN_ID field (valid when vlan_valid). */
4824 + uint64_t vlan_id:12;
4825 +
4826 + uint64_t unassigned2:16;
4827 + /*
4828 + * Reserved for software use, hardware will clear on
4829 + * packet creation.
4830 + */
4831 + uint64_t software:1;
4832 + uint64_t unassigned3:1;
4833 + /* Set if the hardware determined that the packet is rarp. */
4834 + uint64_t is_rarp:1;
4835 + /* Set if the hardware determined that the packet is arp. */
4836 + uint64_t is_arp:1;
4837 + /*
4838 + * Set if the hardware determined that the packet is a
4839 + * broadcast.
4840 + */
4841 + uint64_t is_bcast:1;
4842 + /*
4843 + * Set if the hardware determined that the packet is a
4844 + * multi-cast.
4845 + */
4846 + uint64_t is_mcast:1;
4847 + /*
4848 + * Set if the packet may not be IP (must be one in
4849 + * this case).
4850 + */
4851 + uint64_t not_IP:1;
4852 + /*
4853 + * The receive interface hardware detected a receive
4854 + * error. Failure indicated in err_code below, decode:
4855 + *
4856 + * - 1 = partial error: a packet was partially
4857 + * received, but internal buffering / bandwidth
4858 + * was not adequate to receive the entire
4859 + * packet.
4860 + *
4861 + * - 2 = jabber error: the RGMII packet was too large
4862 + * and is truncated.
4863 + *
4864 + * - 3 = overrun error: the RGMII packet is longer
4865 + * than allowed and had an FCS error.
4866 + *
4867 + * - 4 = oversize error: the RGMII packet is longer
4868 + * than allowed.
4869 + *
4870 + * - 5 = alignment error: the RGMII packet is not an
4871 + * integer number of bytes and had an FCS error
4872 + * (100M and 10M only).
4873 + *
4874 + * - 6 = fragment error: the RGMII packet is shorter
4875 + * than allowed and had an FCS error.
4876 + *
4877 + * - 7 = GMX FCS error: the RGMII packet had an FCS
4878 + * error.
4879 + *
4880 + * - 8 = undersize error: the RGMII packet is shorter
4881 + * than allowed.
4882 + *
4883 + * - 9 = extend error: the RGMII packet had an extend
4884 + * error.
4885 + *
4886 + * - 10 = length mismatch error: the RGMII packet had
4887 + * a length that did not match the length field
4888 + * in the L2 HDR.
4889 + *
4890 + * - 11 = RGMII RX error/SPI4 DIP4 Error: the RGMII
4891 + * packet had one or more data reception errors
4892 + * (RXERR) or the SPI4 packet had one or more
4893 + * DIP4 errors.
4894 + *
4895 + * - 12 = RGMII skip error/SPI4 Abort Error: the RGMII
4896 + * packet was not large enough to cover the
4897 + * skipped bytes or the SPI4 packet was
4898 + * terminated with an About EOPS.
4899 + *
4900 + * - 13 = RGMII nibble error/SPI4 Port NXA Error: the
4901 + * RGMII packet had a studder error (data not
4902 + * repeated - 10/100M only) or the SPI4 packet
4903 + * was sent to an NXA.
4904 + *
4905 + * - 16 = FCS error: a SPI4.2 packet had an FCS error.
4906 + *
4907 + * - 17 = Skip error: a packet was not large enough to
4908 + * cover the skipped bytes.
4909 + *
4910 + * - 18 = L2 header malformed: the packet is not long
4911 + * enough to contain the L2
4912 + */
4913 +
4914 + /*
4915 + * lower err_code = first-level descriptor of the
4916 + * work.
4917 + *
4918 + * zero for packet submitted by hardware that isn't on
4919 + * the slow path.
4920 + */
4921 + uint64_t rcv_error:1;
4922 +
4923 + /* Type is cvmx_pip_err_t (union, so can't use directly. */
4924 + uint64_t err_code:8;
4925 + } snoip;
4926 +
4927 +};
4928 +
4929 +/**
4930 + * Work queue entry format
4931 + *
4932 + * must be 8-byte aligned
4933 + */
4934 +struct cvmx_wqe {
4935 +
4936 + /*****************************************************************
4937 + * WORD 0
4938 + * HW WRITE: the following 64 bits are filled by HW when a packet arrives
4939 + */
4940 +
4941 + /**
4942 + * raw chksum result generated by the HW
4943 + */
4944 + uint16_t hw_chksum;
4945 + /**
4946 + * Field unused by hardware - available for software
4947 + */
4948 + uint8_t unused;
4949 + /**
4950 + * Next pointer used by hardware for list maintenance.
4951 + * May be written/read by HW before the work queue
4952 + * entry is scheduled to a PP
4953 + * (Only 36 bits used in Octeon 1)
4954 + */
4955 + uint64_t next_ptr:40;
4956 +
4957 + /*****************************************************************
4958 + * WORD 1
4959 + * HW WRITE: the following 64 bits are filled by HW when a packet arrives
4960 + */
4961 +
4962 + /**
4963 + * HW sets to the total number of bytes in the packet
4964 + */
4965 + uint64_t len:16;
4966 + /**
4967 + * HW sets this to input physical port
4968 + */
4969 + uint64_t ipprt:6;
4970 +
4971 + /**
4972 + * HW sets this to what it thought the priority of the input packet was
4973 + */
4974 + uint64_t qos:3;
4975 +
4976 + /**
4977 + * the group that the work queue entry will be scheduled to
4978 + */
4979 + uint64_t grp:4;
4980 + /**
4981 + * the type of the tag (ORDERED, ATOMIC, NULL)
4982 + */
4983 + uint64_t tag_type:3;
4984 + /**
4985 + * the synchronization/ordering tag
4986 + */
4987 + uint64_t tag:32;
4988 +
4989 + /**
4990 + * WORD 2 HW WRITE: the following 64-bits are filled in by
4991 + * hardware when a packet arrives This indicates a variety of
4992 + * status and error conditions.
4993 + */
4994 + union cvmx_pip_wqe_word2 word2;
4995 +
4996 + /**
4997 + * Pointer to the first segment of the packet.
4998 + */
4999 + union cvmx_buf_ptr packet_ptr;
5000 +
5001 + /**
5002 + * HW WRITE: octeon will fill in a programmable amount from the
5003 + * packet, up to (at most, but perhaps less) the amount
5004 + * needed to fill the work queue entry to 128 bytes
5005 + * If the packet is recognized to be IP, the hardware starts (except that
5006 + * the IPv4 header is padded for appropriate alignment) writing here where
5007 + * the IP header starts.
5008 + * If the packet is not recognized to be IP, the hardware starts writing
5009 + * the beginning of the packet here.
5010 + */
5011 + uint8_t packet_data[96];
5012 +
5013 + /**
5014 + * If desired, SW can make the work Q entry any length. For the
5015 + * purposes of discussion here, Assume 128B always, as this is all that
5016 + * the hardware deals with.
5017 + *
5018 + */
5019 +
5020 +} CVMX_CACHE_LINE_ALIGNED;
5021 +
5022 +#endif /* __CVMX_WQE_H__ */
5023 diff --git a/arch/mips/include/asm/octeon/cvmx.h b/arch/mips/include/asm/octeon/cvmx.h
5024 index 03fddfa..e31e3fe 100644
5025 --- a/arch/mips/include/asm/octeon/cvmx.h
5026 +++ b/arch/mips/include/asm/octeon/cvmx.h
5027 @@ -376,6 +376,18 @@ static inline uint64_t cvmx_get_cycle(void)
5028 }
5029
5030 /**
5031 + * Wait for the specified number of cycle
5032 + *
5033 + */
5034 +static inline void cvmx_wait(uint64_t cycles)
5035 +{
5036 + uint64_t done = cvmx_get_cycle() + cycles;
5037 +
5038 + while (cvmx_get_cycle() < done)
5039 + ; /* Spin */
5040 +}
5041 +
5042 +/**
5043 * Reads a chip global cycle counter. This counts CPU cycles since
5044 * chip reset. The counter is 64 bit.
5045 * This register does not exist on CN38XX pass 1 silicion
5046 diff --git a/arch/mips/include/asm/octeon/octeon.h b/arch/mips/include/asm/octeon/octeon.h
5047 index edc6760..cac9b1a 100644
5048 --- a/arch/mips/include/asm/octeon/octeon.h
5049 +++ b/arch/mips/include/asm/octeon/octeon.h
5050 @@ -245,4 +245,6 @@ static inline uint32_t octeon_npi_read32(uint64_t address)
5051 return cvmx_read64_uint32(address ^ 4);
5052 }
5053
5054 +extern struct cvmx_bootinfo *octeon_bootinfo;
5055 +
5056 #endif /* __ASM_OCTEON_OCTEON_H */
5057 --
5058 1.5.6.5
5059
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