cns21xx: add initial support for the Cavium CNS21xx SoC
[openwrt/svn-archive/archive.git] / target / linux / cns21xx / patches-2.6.37 / 302-cns21xx-mach-nsb3ast.patch
1 --- a/arch/arm/mach-cns21xx/Kconfig
2 +++ b/arch/arm/mach-cns21xx/Kconfig
3 @@ -2,6 +2,15 @@ if ARCH_CNS21XX
4
5 menu "Cavium Networks CNS21xx based machines"
6
7 +config MACH_NSB3AST
8 + bool "AGESTAR NSB3AST support"
9 + select CNS21XX_DEV_GEC
10 + select CNS21XX_DEV_SPI_MASTER
11 + select CNS21XX_DEV_USB
12 + help
13 + Say Y here if you intend to run this kernel on the
14 + AGESTAR NSB3AST board.
15 +
16 config MACH_NS_K330
17 bool "NS-K330 NAS"
18 select CNS21XX_DEV_GEC
19 --- /dev/null
20 +++ b/arch/arm/mach-cns21xx/mach-nsb3ast.c
21 @@ -0,0 +1,179 @@
22 +/*
23 + * AGESTAR NSB3AST board support
24 + *
25 + * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
26 + *
27 + * This file is free software; you can redistribute it and/or modify
28 + * it under the terms of the GNU General Public License, Version 2, as
29 + * published by the Free Software Foundation.
30 + */
31 +
32 +#include <linux/kernel.h>
33 +#include <linux/init.h>
34 +#include <linux/mtd/mtd.h>
35 +#include <linux/mtd/map.h>
36 +#include <linux/mtd/partitions.h>
37 +#include <linux/spi/spi.h>
38 +#include <linux/spi/flash.h>
39 +#include <linux/platform_device.h>
40 +#include <linux/gpio.h>
41 +#include <linux/leds.h>
42 +#include <linux/gpio_keys.h>
43 +#include <linux/input.h>
44 +
45 +#include <asm/setup.h>
46 +#include <asm/mach-types.h>
47 +#include <asm/mach/arch.h>
48 +#include <asm/mach/time.h>
49 +#include <mach/hardware.h>
50 +#include <mach/cns21xx.h>
51 +#include <mach/cns21xx_misc.h>
52 +
53 +#include "common.h"
54 +#include "dev-gec.h"
55 +
56 +#ifdef CONFIG_MTD_PARTITIONS
57 +static struct mtd_partition nsb3ast_partitions[] = {
58 + {
59 + .name = "armboot",
60 + .offset = 0x0,
61 + .size = 0x040000,
62 + .mask_flags = MTD_WRITEABLE,
63 + }, {
64 + .name = "kernel",
65 + .offset = 0x040000,
66 + .size = 0x100000,
67 + }, {
68 + .name = "rootfs",
69 + .offset = 0x140000,
70 + .size = 0x6c0000,
71 + }, {
72 + .name = "firmware",
73 + .offset = 0x040000,
74 + .size = 0x7c0000,
75 + }, {
76 + .name = "wholeflash",
77 + .offset = 0x0,
78 + .size = 0x800000,
79 + .mask_flags = MTD_WRITEABLE,
80 + },
81 +};
82 +#else
83 +#define nsb3ast_partitions NULL
84 +#define nsb3ast_num_partitions 0
85 +#endif /* CONFIG_MTD_PARTITIONS */
86 +
87 +static struct flash_platform_data nsb3ast_flash_data = {
88 + .parts = nsb3ast_partitions,
89 + .nr_parts = ARRAY_SIZE(nsb3ast_partitions),
90 +};
91 +
92 +static struct spi_board_info nsb3ast_spi_board_info[] = {
93 + {
94 + .bus_num = 0,
95 + .chip_select = 0,
96 + .max_speed_hz = 25000000,
97 + .modalias = "m25p80",
98 + .platform_data = &nsb3ast_flash_data,
99 + }
100 +};
101 +
102 +static struct gpio_led nsb3ast_gpio_leds[] = {
103 + {
104 + .name = "nsb3ast:red:d1",
105 + .gpio = 15,
106 + .active_low = 1,
107 + }, {
108 + .name = "nsb3ast:amber:eth",
109 + .gpio = 22,
110 + .active_low = 1,
111 + }
112 +};
113 +
114 +static struct gpio_led_platform_data nsb3ast_gpio_leds_data = {
115 + .num_leds = ARRAY_SIZE(nsb3ast_gpio_leds),
116 + .leds = nsb3ast_gpio_leds,
117 +};
118 +
119 +static struct platform_device nsb3ast_gpio_leds_device = {
120 + .name = "leds-gpio",
121 + .id = -1,
122 + .dev.platform_data = &nsb3ast_gpio_leds_data,
123 +};
124 +
125 +static struct gpio_keys_button nsb3ast_gpio_keys[] = {
126 + {
127 + .code = KEY_RESTART,
128 + .gpio = 0,
129 + .desc = "Reset Button",
130 + .active_low = 1,
131 + },
132 + {
133 + .code = BTN_0,
134 + .gpio = 2,
135 + .desc = "USB Button",
136 + .active_low = 0,
137 + },
138 +};
139 +
140 +static struct gpio_keys_platform_data nsb3ast_gpio_keys_data = {
141 + .buttons = nsb3ast_gpio_keys,
142 + .nbuttons = ARRAY_SIZE(nsb3ast_gpio_keys),
143 +};
144 +
145 +static struct platform_device nsb3ast_gpio_keys_device = {
146 + .name = "gpio-keys",
147 + .id = -1,
148 + .num_resources = 0,
149 + .dev = {
150 + .platform_data = &nsb3ast_gpio_keys_data,
151 + },
152 +};
153 +
154 +static void __init nsb3ast_fixup(struct machine_desc *desc,
155 + struct tag *tags, char **cmdline,
156 + struct meminfo *mi)
157 +{
158 + struct tag *t;
159 +
160 + /* The board has 32MB of RAM mapped at 0. */
161 + mi->nr_banks = 1;
162 + mi->bank[0].start = 0;
163 + mi->bank[0].size = SZ_32M;
164 +
165 + for (t = tags; t->hdr.size; t = tag_next(t)) {
166 + switch (t->hdr.tag) {
167 + case ATAG_CORE:
168 + if (t->u.core.rootdev == 255)
169 + t->u.core.rootdev = 0;
170 + break;
171 + }
172 + }
173 +}
174 +
175 +static void __init nsb3ast_init(void)
176 +{
177 + cns21xx_gpio_init();
178 + cns21xx_register_uart0();
179 + cns21xx_register_uart1();
180 + cns21xx_register_wdt();
181 + cns21xx_register_usb();
182 + cns21xx_register_spi_master(-1, nsb3ast_spi_board_info,
183 + ARRAY_SIZE(nsb3ast_spi_board_info));
184 +
185 + cns21xx_gec_data.phy_type = CNS21XX_GEC_PHY_TYPE_INTERNAL;
186 + cns21xx_register_gec();
187 +
188 + HAL_MISC_DISABLE_LED012_PINS();
189 + platform_device_register(&nsb3ast_gpio_leds_device);
190 + platform_device_register(&nsb3ast_gpio_keys_device);
191 +}
192 +
193 +MACHINE_START(NSB3AST, "AGESTAR NSB3AST")
194 + .boot_params = 0x100,
195 + .fixup = nsb3ast_fixup,
196 + .map_io = cns21xx_map_io,
197 + .init_irq = cns21xx_init_irq,
198 + .timer = &cns21xx_timer,
199 + .init_machine = nsb3ast_init,
200 +MACHINE_END
201 --- a/arch/arm/mach-cns21xx/Makefile
202 +++ b/arch/arm/mach-cns21xx/Makefile
203 @@ -13,3 +13,4 @@ obj-$(CONFIG_CNS21XX_DEV_SPI_MASTER) +=
204
205 # machine specific files
206 obj-$(CONFIG_MACH_NS_K330) += mach-ns-k330.o
207 +obj-$(CONFIG_MACH_NSB3AST) += mach-nsb3ast.o