16ad5626513e9df96eb8def0a2b611b0593c7100
[openwrt/svn-archive/archive.git] / target / linux / cns3xxx / files / arch / arm / mach-cns3xxx / platsmp.c
1 /*
2 * linux/arch/arm/mach-cns3xxx/platsmp.c
3 *
4 * Copyright (C) 2002 ARM Ltd.
5 * Copyright 2012 Gateworks Corporation
6 * Chris Lang <clang@gateworks.com>
7 * Tim Harvey <tharvey@gateworks.com>
8 *
9 * All Rights Reserved
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/jiffies.h>
20 #include <linux/smp.h>
21 #include <linux/io.h>
22
23 #include <asm/cacheflush.h>
24 #include <asm/hardware/gic.h>
25 #include <asm/smp_scu.h>
26 #include <asm/unified.h>
27 #include <asm/fiq.h>
28 #include <mach/smp.h>
29 #include <mach/cns3xxx.h>
30
31 static struct fiq_handler fh = {
32 .name = "cns3xxx-fiq"
33 };
34
35 static unsigned int fiq_buffer[8];
36
37 #define FIQ_ENABLED 0x80000000
38 #define FIQ_GENERATE 0x00010000
39 #define CNS3XXX_MAP_AREA 0x01000000
40 #define CNS3XXX_UNMAP_AREA 0x02000000
41 #define CNS3XXX_FLUSH_RANGE 0x03000000
42
43 extern void cns3xxx_secondary_startup(void);
44 extern unsigned char cns3xxx_fiq_start, cns3xxx_fiq_end;
45 extern unsigned int fiq_number[2];
46 extern struct cpu_cache_fns cpu_cache;
47 struct cpu_cache_fns cpu_cache_save;
48
49 #define SCU_CPU_STATUS 0x08
50 static void __iomem *scu_base;
51
52 /*
53 * control for which core is the next to come out of the secondary
54 * boot "holding pen"
55 */
56 volatile int __cpuinitdata pen_release = -1;
57
58 static void __init cns3xxx_set_fiq_regs(void)
59 {
60 struct pt_regs FIQ_regs;
61 unsigned int cpu = smp_processor_id();
62
63 if (cpu) {
64 FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[4];
65 FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(0);
66 } else {
67 FIQ_regs.ARM_ip = (unsigned int)&fiq_buffer[0];
68 FIQ_regs.ARM_sp = (unsigned int)MISC_FIQ_CPU(1);
69 }
70 set_fiq_regs(&FIQ_regs);
71 }
72
73 static void __init cns3xxx_init_fiq(void)
74 {
75 void *fiqhandler_start;
76 unsigned int fiqhandler_length;
77 int ret;
78
79 fiqhandler_start = &cns3xxx_fiq_start;
80 fiqhandler_length = &cns3xxx_fiq_end - &cns3xxx_fiq_start;
81
82 ret = claim_fiq(&fh);
83
84 if (ret) {
85 return;
86 }
87
88 set_fiq_handler(fiqhandler_start, fiqhandler_length);
89 fiq_buffer[0] = (unsigned int)&fiq_number[0];
90 fiq_buffer[3] = 0;
91 fiq_buffer[4] = (unsigned int)&fiq_number[1];
92 fiq_buffer[7] = 0;
93 }
94
95
96 /*
97 * Write pen_release in a way that is guaranteed to be visible to all
98 * observers, irrespective of whether they're taking part in coherency
99 * or not. This is necessary for the hotplug code to work reliably.
100 */
101 static void __cpuinit write_pen_release(int val)
102 {
103 pen_release = val;
104 smp_wmb();
105 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
106 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
107 }
108
109 static DEFINE_SPINLOCK(boot_lock);
110
111 void __cpuinit platform_secondary_init(unsigned int cpu)
112 {
113 /*
114 * if any interrupts are already enabled for the primary
115 * core (e.g. timer irq), then they will not have been enabled
116 * for us: do so
117 */
118 gic_secondary_init(0);
119
120 /*
121 * Setup Secondary Core FIQ regs
122 */
123 cns3xxx_set_fiq_regs();
124
125 /*
126 * let the primary processor know we're out of the
127 * pen, then head off into the C entry point
128 */
129 write_pen_release(-1);
130
131 /*
132 * Fixup DMA Operations
133 *
134 */
135 cpu_cache.dma_map_area = (void *)smp_dma_map_area;
136 cpu_cache.dma_unmap_area = (void *)smp_dma_unmap_area;
137 cpu_cache.dma_flush_range = (void *)smp_dma_flush_range;
138
139 /*
140 * Synchronise with the boot thread.
141 */
142 spin_lock(&boot_lock);
143 spin_unlock(&boot_lock);
144 }
145
146 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
147 {
148 unsigned long timeout;
149
150 /*
151 * Set synchronisation state between this boot processor
152 * and the secondary one
153 */
154 spin_lock(&boot_lock);
155
156 /*
157 * The secondary processor is waiting to be released from
158 * the holding pen - release it, then wait for it to flag
159 * that it has been released by resetting pen_release.
160 *
161 * Note that "pen_release" is the hardware CPU ID, whereas
162 * "cpu" is Linux's internal ID.
163 */
164 write_pen_release(cpu);
165
166 /*
167 * Send the secondary CPU a soft interrupt, thereby causing
168 * the boot monitor to read the system wide flags register,
169 * and branch to the address found there.
170 */
171 gic_raise_softirq(cpumask_of(cpu), 1);
172
173 timeout = jiffies + (1 * HZ);
174 while (time_before(jiffies, timeout)) {
175 smp_rmb();
176 if (pen_release == -1)
177 break;
178
179 udelay(10);
180 }
181
182 /*
183 * now the secondary core is starting up let it run its
184 * calibrations, then wait for it to finish
185 */
186 spin_unlock(&boot_lock);
187
188 return pen_release != -1 ? -ENOSYS : 0;
189 }
190
191 /*
192 * Initialise the CPU possible map early - this describes the CPUs
193 * which may be present or become present in the system.
194 */
195 void __init smp_init_cpus(void)
196 {
197 unsigned int i, ncores;
198 unsigned int status;
199
200 scu_base = (void __iomem *) CNS3XXX_TC11MP_SCU_BASE_VIRT;
201
202 /* for CNS3xxx SCU_CPU_STATUS must be examined instead of SCU_CONFIGURATION
203 * used in scu_get_core_count
204 */
205 status = __raw_readl(scu_base + SCU_CPU_STATUS);
206 for (i = 0; i < NR_CPUS+1; i++) {
207 if (((status >> (i*2)) & 0x3) == 0)
208 set_cpu_possible(i, true);
209 else
210 break;
211 }
212 ncores = i;
213
214 set_smp_cross_call(gic_raise_softirq);
215 }
216
217 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
218 {
219 int i;
220
221 /*
222 * Initialise the present map, which describes the set of CPUs
223 * actually populated at the present time.
224 */
225 for (i = 0; i < max_cpus; i++) {
226 set_cpu_present(i, true);
227 }
228
229 /*
230 * enable SCU
231 */
232 scu_enable(scu_base);
233
234 /*
235 * Write the address of secondary startup into the
236 * system-wide flags register. The boot monitor waits
237 * until it receives a soft interrupt, and then the
238 * secondary CPU branches to this address.
239 */
240 __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
241 (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
242
243 /*
244 * Setup FIQ's for main cpu
245 */
246 cns3xxx_init_fiq();
247 cns3xxx_set_fiq_regs();
248 memcpy((void *)&cpu_cache_save, (void *)&cpu_cache, sizeof(struct cpu_cache_fns));
249 }
250
251
252 static inline unsigned long cns3xxx_cpu_id(void)
253 {
254 unsigned long cpu;
255
256 asm volatile(
257 " mrc p15, 0, %0, c0, c0, 5 @ cns3xxx_cpu_id\n"
258 : "=r" (cpu) : : "memory", "cc");
259 return (cpu & 0xf);
260 }
261
262 void smp_dma_map_area(const void *addr, size_t size, int dir)
263 {
264 unsigned int cpu;
265 unsigned long flags;
266 raw_local_irq_save(flags);
267 cpu = cns3xxx_cpu_id();
268 if (cpu) {
269 fiq_buffer[1] = (unsigned int)addr;
270 fiq_buffer[2] = size;
271 fiq_buffer[3] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
272 smp_mb();
273 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
274
275 cpu_cache_save.dma_map_area(addr, size, dir);
276 while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
277 } else {
278
279 fiq_buffer[5] = (unsigned int)addr;
280 fiq_buffer[6] = size;
281 fiq_buffer[7] = dir | CNS3XXX_MAP_AREA | FIQ_ENABLED;
282 smp_mb();
283 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
284
285 cpu_cache_save.dma_map_area(addr, size, dir);
286 while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
287 }
288 raw_local_irq_restore(flags);
289 }
290
291 void smp_dma_unmap_area(const void *addr, size_t size, int dir)
292 {
293 unsigned int cpu;
294 unsigned long flags;
295
296 raw_local_irq_save(flags);
297 cpu = cns3xxx_cpu_id();
298 if (cpu) {
299
300 fiq_buffer[1] = (unsigned int)addr;
301 fiq_buffer[2] = size;
302 fiq_buffer[3] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
303 smp_mb();
304 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
305
306 cpu_cache_save.dma_unmap_area(addr, size, dir);
307 while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
308 } else {
309
310 fiq_buffer[5] = (unsigned int)addr;
311 fiq_buffer[6] = size;
312 fiq_buffer[7] = dir | CNS3XXX_UNMAP_AREA | FIQ_ENABLED;
313 smp_mb();
314 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
315
316 cpu_cache_save.dma_unmap_area(addr, size, dir);
317 while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
318 }
319 raw_local_irq_restore(flags);
320 }
321
322 void smp_dma_flush_range(const void *start, const void *end)
323 {
324 unsigned int cpu;
325 unsigned long flags;
326 raw_local_irq_save(flags);
327 cpu = cns3xxx_cpu_id();
328 if (cpu) {
329
330 fiq_buffer[1] = (unsigned int)start;
331 fiq_buffer[2] = (unsigned int)end;
332 fiq_buffer[3] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
333 smp_mb();
334 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(1));
335
336 cpu_cache_save.dma_flush_range(start, end);
337 while ((fiq_buffer[3]) & FIQ_ENABLED) { barrier(); }
338 } else {
339
340 fiq_buffer[5] = (unsigned int)start;
341 fiq_buffer[6] = (unsigned int)end;
342 fiq_buffer[7] = CNS3XXX_FLUSH_RANGE | FIQ_ENABLED;
343 smp_mb();
344 __raw_writel(FIQ_GENERATE, MISC_FIQ_CPU(0));
345
346 cpu_cache_save.dma_flush_range(start, end);
347 while ((fiq_buffer[7]) & FIQ_ENABLED) { barrier(); }
348 }
349 raw_local_irq_restore(flags);
350 }