target/linux/cns3xxx/patches-3.0/049-cns3xxx_smp_support.patch

   1 --- a/arch/arm/mach-cns3xxx/Makefile
   2 +++ b/arch/arm/mach-cns3xxx/Makefile
   3 @@ -1,3 +1,6 @@
   4  obj-$(CONFIG_ARCH_CNS3XXX)             += core.o pm.o devices.o
   5  obj-$(CONFIG_PCI)                      += pcie.o
   6  obj-$(CONFIG_MACH_CNS3420VB)           += cns3420vb.o
   7 +obj-$(CONFIG_SMP)                      += platsmp.o headsmp.o
   8 +obj-$(CONFIG_HOTPLUG_CPU)              += hotplug.o
   9 +obj-$(CONFIG_LOCAL_TIMERS)             += localtimer.o
  10 --- /dev/null
  11 +++ b/arch/arm/mach-cns3xxx/headsmp.S
  12 @@ -0,0 +1,43 @@
  13 +/*
  14 + *  linux/arch/arm/mach-cns3xxx/headsmp.S
  15 + *
  16 + *  Copyright (c) 2003 ARM Limited
  17 + *  Copyright 2011 Gateworks Corporation
  18 + *                Chris Lang <clang@gateworks.com
  19 + *
  20 + *  All Rights Reserved
  21 + *
  22 + * This program is free software; you can redistribute it and/or modify
  23 + * it under the terms of the GNU General Public License version 2 as
  24 + * published by the Free Software Foundation.
  25 + */
  26 +#include <linux/linkage.h>
  27 +#include <linux/init.h>
  28 +
  29 +       __INIT
  30 +
  31 +/*
  32 + * CNS3XXX specific entry point for secondary CPUs.  This
  33 + * provides a "holding pen" into which all secondary cores are held
  34 + * until we're ready for them to initialise.
  35 + */
  36 +ENTRY(cns3xxx_secondary_startup)
  37 +       mrc     p15, 0, r0, c0, c0, 5
  38 +       and     r0, r0, #15
  39 +       adr     r4, 1f
  40 +       ldmia   r4, {r5, r6}
  41 +       sub     r4, r4, r5
  42 +       add     r6, r6, r4
  43 +pen:   ldr     r7, [r6]
  44 +       cmp     r7, r0
  45 +       bne     pen
  46 +
  47 +       /*
  48 +        * we've been released from the holding pen: secondary_stack
  49 +        * should now contain the SVC stack for this core
  50 +        */
  51 +       b       secondary_startup
  52 +
  53 +       .align
  54 +1:     .long   .
  55 +       .long   pen_release
  56 --- /dev/null
  57 +++ b/arch/arm/mach-cns3xxx/hotplug.c
  58 @@ -0,0 +1,131 @@
  59 +/*
  60 + *  linux/arch/arm/mach-cns3xxx/hotplug.c
  61 + *
  62 + *  Copyright (C) 2002 ARM Ltd.
  63 + *  Copyright 2011 Gateworks Corporation
  64 + *                Chris Lang <clang@gateworks.com>
  65 + *
  66 + *  All Rights Reserved
  67 + *
  68 + * This program is free software; you can redistribute it and/or modify
  69 + * it under the terms of the GNU General Public License version 2 as
  70 + * published by the Free Software Foundation.
  71 + */
  72 +#include <linux/kernel.h>
  73 +#include <linux/errno.h>
  74 +#include <linux/smp.h>
  75 +
  76 +#include <asm/cacheflush.h>
  77 +
  78 +extern volatile int pen_release;
  79 +
  80 +static inline void cpu_enter_lowpower(void)
  81 +{
  82 +       unsigned int v;
  83 +
  84 +       flush_cache_all();
  85 +       asm volatile(
  86 +               "mcr    p15, 0, %1, c7, c5, 0\n"
  87 +       "       mcr     p15, 0, %1, c7, c10, 4\n"
  88 +       /*
  89 +        * Turn off coherency
  90 +        */
  91 +       "       mrc     p15, 0, %0, c1, c0, 1\n"
  92 +       "       bic     %0, %0, %3\n"
  93 +       "       mcr     p15, 0, %0, c1, c0, 1\n"
  94 +       "       mrc     p15, 0, %0, c1, c0, 0\n"
  95 +       "       bic     %0, %0, %2\n"
  96 +       "       mcr     p15, 0, %0, c1, c0, 0\n"
  97 +         : "=&r" (v)
  98 +         : "r" (0), "Ir" (CR_C), "Ir" (0x40)
  99 +         : "cc");
 100 +}
 101 +
 102 +static inline void cpu_leave_lowpower(void)
 103 +{
 104 +       unsigned int v;
 105 +
 106 +       asm volatile(
 107 +               "mrc    p15, 0, %0, c1, c0, 0\n"
 108 +       "       orr     %0, %0, %1\n"
 109 +       "       mcr     p15, 0, %0, c1, c0, 0\n"
 110 +       "       mrc     p15, 0, %0, c1, c0, 1\n"
 111 +       "       orr     %0, %0, %2\n"
 112 +       "       mcr     p15, 0, %0, c1, c0, 1\n"
 113 +         : "=&r" (v)
 114 +         : "Ir" (CR_C), "Ir" (0x40)
 115 +         : "cc");
 116 +}
 117 +
 118 +static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
 119 +{
 120 +       /*
 121 +        * there is no power-control hardware on this platform, so all
 122 +        * we can do is put the core into WFI; this is safe as the calling
 123 +        * code will have already disabled interrupts
 124 +        */
 125 +       for (;;) {
 126 +               /*
 127 +                * here's the WFI
 128 +                */
 129 +               asm(".word      0xe320f003\n"
 130 +                   :
 131 +                   :
 132 +                   : "memory", "cc");
 133 +
 134 +               if (pen_release == cpu) {
 135 +                       /*
 136 +                        * OK, proper wakeup, we're done
 137 +                        */
 138 +                       break;
 139 +               }
 140 +
 141 +               /*
 142 +                * Getting here, means that we have come out of WFI without
 143 +                * having been woken up - this shouldn't happen
 144 +                *
 145 +                * Just note it happening - when we're woken, we can report
 146 +                * its occurrence.
 147 +                */
 148 +               (*spurious)++;
 149 +       }
 150 +}
 151 +
 152 +int platform_cpu_kill(unsigned int cpu)
 153 +{
 154 +       return 1;
 155 +}
 156 +
 157 +/*
 158 + * platform-specific code to shutdown a CPU
 159 + *
 160 + * Called with IRQs disabled
 161 + */
 162 +void platform_cpu_die(unsigned int cpu)
 163 +{
 164 +       int spurious = 0;
 165 +
 166 +       /*
 167 +        * we're ready for shutdown now, so do it
 168 +        */
 169 +       cpu_enter_lowpower();
 170 +       platform_do_lowpower(cpu, &spurious);
 171 +
 172 +       /*
 173 +        * bring this CPU back into the world of cache
 174 +        * coherency, and then restore interrupts
 175 +        */
 176 +       cpu_leave_lowpower();
 177 +
 178 +       if (spurious)
 179 +               pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
 180 +}
 181 +
 182 +int platform_cpu_disable(unsigned int cpu)
 183 +{
 184 +       /*
 185 +        * we don't allow CPU 0 to be shutdown (it is still too special
 186 +        * e.g. clock tick interrupts)
 187 +        */
 188 +       return cpu == 0 ? -EPERM : 0;
 189 +}
 190 --- /dev/null
 191 +++ b/arch/arm/mach-cns3xxx/localtimer.c
 192 @@ -0,0 +1,29 @@
 193 +/*
 194 + *  linux/arch/arm/mach-cns3xxx/localtimer.c
 195 + *
 196 + *  Copyright (C) 2002 ARM Ltd.
 197 + *  Copyright 2011 Gateworks Corporation
 198 + *                Chris Lang <clang@gateworks.com>
 199 + *
 200 + *  All Rights Reserved
 201 + *
 202 + * This program is free software; you can redistribute it and/or modify
 203 + * it under the terms of the GNU General Public License version 2 as
 204 + * published by the Free Software Foundation.
 205 + */
 206 +#include <linux/init.h>
 207 +#include <linux/smp.h>
 208 +#include <linux/clockchips.h>
 209 +
 210 +#include <asm/smp_twd.h>
 211 +#include <asm/localtimer.h>
 212 +#include <mach/irqs.h>
 213 +
 214 +/*
 215 + * Setup the local clock events for a CPU.
 216 + */
 217 +void __cpuinit local_timer_setup(struct clock_event_device *evt)
 218 +{
 219 +       evt->irq = IRQ_LOCALTIMER;
 220 +       twd_timer_setup(evt);
 221 +}
 222 --- /dev/null
 223 +++ b/arch/arm/mach-cns3xxx/platsmp.c
 224 @@ -0,0 +1,168 @@
 225 +/*
 226 + *  linux/arch/arm/mach-cns3xxx/platsmp.c
 227 + *
 228 + *  Copyright (C) 2002 ARM Ltd.
 229 + *  Copyright 2011 Gateworks Corporation
 230 + *                Chris Lang <clang@gateworks.com>
 231 + *
 232 + *  All Rights Reserved
 233 + *
 234 + * This program is free software; you can redistribute it and/or modify
 235 + * it under the terms of the GNU General Public License version 2 as
 236 + * published by the Free Software Foundation.
 237 + */
 238 +#include <linux/init.h>
 239 +#include <linux/errno.h>
 240 +#include <linux/delay.h>
 241 +#include <linux/device.h>
 242 +#include <linux/jiffies.h>
 243 +#include <linux/smp.h>
 244 +#include <linux/io.h>
 245 +
 246 +#include <asm/cacheflush.h>
 247 +#include <asm/smp_scu.h>
 248 +#include <asm/unified.h>
 249 +#include <mach/hardware.h>
 250 +#include <mach/cns3xxx.h>
 251 +
 252 +#include "core.h"
 253 +
 254 +extern void cns3xxx_secondary_startup(void);
 255 +
 256 +/*
 257 + * control for which core is the next to come out of the secondary
 258 + * boot "holding pen"
 259 + */
 260 +volatile int __cpuinitdata pen_release = -1;
 261 +
 262 +/*
 263 + * Write pen_release in a way that is guaranteed to be visible to all
 264 + * observers, irrespective of whether they're taking part in coherency
 265 + * or not.  This is necessary for the hotplug code to work reliably.
 266 + */
 267 +static void __cpuinit write_pen_release(int val)
 268 +{
 269 +       pen_release = val;
 270 +       smp_wmb();
 271 +       __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
 272 +       outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
 273 +}
 274 +
 275 +static void __iomem *scu_base_addr(void)
 276 +{
 277 +       return (void __iomem *)(CNS3XXX_TC11MP_SCU_BASE_VIRT);
 278 +}
 279 +
 280 +static DEFINE_SPINLOCK(boot_lock);
 281 +
 282 +void __cpuinit platform_secondary_init(unsigned int cpu)
 283 +{
 284 +       /*
 285 +        * if any interrupts are already enabled for the primary
 286 +        * core (e.g. timer irq), then they will not have been enabled
 287 +        * for us: do so
 288 +        */
 289 +       gic_secondary_init(0);
 290 +
 291 +       /*
 292 +        * let the primary processor know we're out of the
 293 +        * pen, then head off into the C entry point
 294 +        */
 295 +       write_pen_release(-1);
 296 +
 297 +       /*
 298 +        * Synchronise with the boot thread.
 299 +        */
 300 +       spin_lock(&boot_lock);
 301 +       spin_unlock(&boot_lock);
 302 +}
 303 +
 304 +int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
 305 +{
 306 +       unsigned long timeout;
 307 +
 308 +       /*
 309 +        * Set synchronisation state between this boot processor
 310 +        * and the secondary one
 311 +        */
 312 +       spin_lock(&boot_lock);
 313 +
 314 +       /*
 315 +        * This is really belt and braces; we hold unintended secondary
 316 +        * CPUs in the holding pen until we're ready for them.  However,
 317 +        * since we haven't sent them a soft interrupt, they shouldn't
 318 +        * be there.
 319 +        */
 320 +       write_pen_release(cpu);
 321 +
 322 +       /*
 323 +        * Send the secondary CPU a soft interrupt, thereby causing
 324 +        * the boot monitor to read the system wide flags register,
 325 +        * and branch to the address found there.
 326 +        */
 327 +       smp_cross_call(cpumask_of(cpu), 1);
 328 +
 329 +       timeout = jiffies + (1 * HZ);
 330 +       while (time_before(jiffies, timeout)) {
 331 +               smp_rmb();
 332 +               if (pen_release == -1)
 333 +                       break;
 334 +
 335 +               udelay(10);
 336 +       }
 337 +
 338 +       /*
 339 +        * now the secondary core is starting up let it run its
 340 +        * calibrations, then wait for it to finish
 341 +        */
 342 +       spin_unlock(&boot_lock);
 343 +
 344 +       return pen_release != -1 ? -ENOSYS : 0;
 345 +}
 346 +
 347 +/*
 348 + * Initialise the CPU possible map early - this describes the CPUs
 349 + * which may be present or become present in the system.
 350 + */
 351 +void __init smp_init_cpus(void)
 352 +{
 353 +       void __iomem *scu_base = scu_base_addr();
 354 +       unsigned int i, ncores;
 355 +
 356 +       ncores = scu_base ? scu_get_core_count(scu_base) : 1;
 357 +
 358 +       /* sanity check */
 359 +       if (ncores > NR_CPUS) {
 360 +               printk(KERN_WARNING
 361 +                      "cns3xxx: no. of cores (%d) greater than configured "
 362 +                      "maximum of %d - clipping\n",
 363 +                      ncores, NR_CPUS);
 364 +               ncores = NR_CPUS;
 365 +       }
 366 +
 367 +       for (i = 0; i < ncores; i++)
 368 +               set_cpu_possible(i, true);
 369 +}
 370 +
 371 +void __init platform_smp_prepare_cpus(unsigned int max_cpus)
 372 +{
 373 +       int i;
 374 +
 375 +       /*
 376 +        * Initialise the present map, which describes the set of CPUs
 377 +        * actually populated at the present time.
 378 +        */
 379 +       for (i = 0; i < max_cpus; i++)
 380 +               set_cpu_present(i, true);
 381 +
 382 +       scu_enable(scu_base_addr());
 383 +
 384 +       /*
 385 +        * Write the address of secondary startup into the
 386 +        * system-wide flags register. The boot monitor waits
 387 +        * until it receives a soft interrupt, and then the
 388 +        * secondary CPU branches to this address.
 389 +        */
 390 +       __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
 391 +                       (void __iomem *)(0xFFF07000 + 0x0600));
 392 +}
 393 --- /dev/null
 394 +++ b/arch/arm/mach-cns3xxx/include/mach/smp.h
 395 @@ -0,0 +1,13 @@
 396 +#ifndef __MACH_SMP_H
 397 +#define __MACH_SMP_H
 398 +
 399 +#include <asm/hardware/gic.h>
 400 +
 401 +/*
 402 + * We use IRQ1 as the IPI
 403 + */
 404 +static inline void smp_cross_call(const struct cpumask *mask, int ipi)
 405 +{
 406 +       gic_raise_softirq(mask, ipi);
 407 +}
 408 +#endif
 409 --- a/arch/arm/Kconfig
 410 +++ b/arch/arm/Kconfig
 411 @@ -1311,7 +1311,7 @@ config SMP
 412         depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
 413                  MACH_REALVIEW_PB11MP || MACH_REALVIEW_PBX || ARCH_OMAP4 || \
 414                  ARCH_EXYNOS4 || ARCH_TEGRA || ARCH_U8500 || ARCH_VEXPRESS_CA9X4 || \
 415 -                ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE
 416 +                ARCH_MSM_SCORPIONMP || ARCH_SHMOBILE || ARCH_CNS3XXX
 417         select USE_GENERIC_SMP_HELPERS
 418         select HAVE_ARM_SCU if !ARCH_MSM_SCORPIONMP
 419         help