target/linux/cns3xxx/patches-3.10/310-pci_isolated_interrupts.patch

   1 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
   2 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
   3 @@ -274,7 +274,7 @@ static int __init cns3420vb_pcie_init(vo
   4         if (!machine_is_cns3420vb())
   5                 return 0;
   6
   7 -       return cns3xxx_pcie_init();
   8 +       return cns3xxx_pcie_init(NULL, NULL);
   9  }
  10  subsys_initcall(cns3420vb_pcie_init);
  11
  12 --- a/arch/arm/mach-cns3xxx/core.h
  13 +++ b/arch/arm/mach-cns3xxx/core.h
  14 @@ -17,7 +17,7 @@ extern void cns3xxx_pcie_iotable_init(vo
  15
  16  void __init cns3xxx_map_io(void);
  17  void __init cns3xxx_init_irq(void);
  18 -int  __init cns3xxx_pcie_init(void);
  19 +int  __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs);
  20  void cns3xxx_power_off(void);
  21  void cns3xxx_restart(char, const char *);
  22
  23 --- a/arch/arm/mach-cns3xxx/laguna.c
  24 +++ b/arch/arm/mach-cns3xxx/laguna.c
  25 @@ -21,6 +21,7 @@
  26  #include <linux/kernel.h>
  27  #include <linux/compiler.h>
  28  #include <linux/io.h>
  29 +#include <linux/irq.h>
  30  #include <linux/gpio.h>
  31  #include <linux/dma-mapping.h>
  32  #include <linux/serial_core.h>
  33 @@ -869,12 +870,45 @@ static int laguna_register_gpio(struct g
  34         return ret;
  35  }
  36
  37 +/* allow disabling of external isolated PCIe IRQs */
  38 +static int cns3xxx_pciextirq = 1;
  39 +static int __init cns3xxx_pciextirq_disable(char *s)
  40 +{
  41 +        cns3xxx_pciextirq = 0;
  42 +        return 1;
  43 +}
  44 +__setup("noextirq", cns3xxx_pciextirq_disable);
  45 +
  46  static int __init laguna_pcie_init(void)
  47  {
  48 +       u32 __iomem *mem = (void __iomem *)(CNS3XXX_GPIOB_BASE_VIRT + 0x0004);
  49 +       u32 reg = (__raw_readl(mem) >> 26) & 0xf;
  50 +       int irqs[] = {
  51 +               IRQ_CNS3XXX_EXTERNAL_PIN0,
  52 +               IRQ_CNS3XXX_EXTERNAL_PIN1,
  53 +               IRQ_CNS3XXX_EXTERNAL_PIN2,
  54 +               154,
  55 +       };
  56 +
  57         if (!machine_is_gw2388())
  58                 return 0;
  59
  60 -       return cns3xxx_pcie_init();
  61 +       /* Verify GPIOB[26:29] == 0001b indicating support for ext irqs */
  62 +       if (cns3xxx_pciextirq && reg != 1)
  63 +               cns3xxx_pciextirq = 0;
  64 +
  65 +       if (cns3xxx_pciextirq) {
  66 +               printk("laguna: using isolated PCI interrupts:"
  67 +                      " irq%d/irq%d/irq%d/irq%d\n",
  68 +                      irqs[0], irqs[1], irqs[2], irqs[3]);
  69 +               return cns3xxx_pcie_init(irqs, NULL);
  70 +       }
  71 +       printk("laguna: using shared PCI interrupts: irq%d\n",
  72 +              IRQ_CNS3XXX_PCIE0_DEVICE);
  73 +       irqs[0] = IRQ_CNS3XXX_PCIE0_DEVICE;
  74 +       irqs[1] = IRQ_CNS3XXX_PCIE0_DEVICE;
  75 +       irqs[2] = IRQ_CNS3XXX_PCIE0_DEVICE;
  76 +       return cns3xxx_pcie_init(irqs, NULL);
  77  }
  78  subsys_initcall(laguna_pcie_init);
  79
  80 @@ -889,8 +923,33 @@ static int __init laguna_model_setup(voi
  81         printk("Running on Gateworks Laguna %s\n", laguna_info.model);
  82         cns3xxx_gpio_init( 0, 32, CNS3XXX_GPIOA_BASE_VIRT, IRQ_CNS3XXX_GPIOA,
  83                 NR_IRQS_CNS3XXX);
  84 -       cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT, IRQ_CNS3XXX_GPIOB,
  85 -               NR_IRQS_CNS3XXX + 32);
  86 +
  87 +       /*
  88 +        * If pcie external interrupts are supported and desired
  89 +        * configure IRQ types and configure pin function.
  90 +        * Note that cns3xxx_pciextirq is enabled by default, but can be
  91 +        * unset via the 'noextirq' kernel param or by laguna_pcie_init() if
  92 +        * the baseboard model does not support this hardware feature.
  93 +        */
  94 +       if (cns3xxx_pciextirq) {
  95 +               mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0018);
  96 +               reg = __raw_readl(mem);
  97 +               /* GPIO26 is gpio, EXT_INT[0:2] not gpio func */
  98 +               reg &= ~0x3c000000;
  99 +               reg |= 0x38000000;
 100 +               __raw_writel(reg, mem);
 101 +
 102 +               cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
 103 +                                 IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
 104 +
 105 +               irq_set_irq_type(154, IRQ_TYPE_LEVEL_LOW);
 106 +               irq_set_irq_type(93, IRQ_TYPE_LEVEL_HIGH);
 107 +               irq_set_irq_type(94, IRQ_TYPE_LEVEL_HIGH);
 108 +               irq_set_irq_type(95, IRQ_TYPE_LEVEL_HIGH);
 109 +       } else {
 110 +               cns3xxx_gpio_init(32, 32, CNS3XXX_GPIOB_BASE_VIRT,
 111 +                                 IRQ_CNS3XXX_GPIOB, NR_IRQS_CNS3XXX + 32);
 112 +       }
 113
 114         if (strncmp(laguna_info.model, "GW", 2) == 0) {
 115                 if (laguna_info.config_bitmap & ETH0_LOAD)
 116 --- a/arch/arm/mach-cns3xxx/pcie.c
 117 +++ b/arch/arm/mach-cns3xxx/pcie.c
 118 @@ -18,6 +18,7 @@
 119  #include <linux/io.h>
 120  #include <linux/ioport.h>
 121  #include <linux/interrupt.h>
 122 +#include <linux/irq.h>
 123  #include <linux/ptrace.h>
 124  #include <asm/mach/map.h>
 125  #include "cns3xxx.h"
 126 @@ -32,7 +33,7 @@ enum cns3xxx_access_type {
 127
 128  struct cns3xxx_pcie {
 129         struct map_desc cfg_bases[CNS3XXX_NUM_ACCESS_TYPES];
 130 -       unsigned int irqs[2];
 131 +       unsigned int irqs[6];
 132         struct resource res_io;
 133         struct resource res_mem;
 134         struct hw_pci hw_pci;
 135 @@ -255,7 +256,7 @@ static struct pci_ops cns3xxx_pcie_ops =
 136  static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 137  {
 138         struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev);
 139 -       int irq = cnspci->irqs[slot];
 140 +       int irq = cnspci->irqs[slot+pin-1];
 141
 142         pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n",
 143                 pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn),
 144 @@ -298,7 +299,12 @@ static struct cns3xxx_pcie cns3xxx_pcie[
 145                         .end = CNS3XXX_PCIE0_MEM_BASE + SZ_16M - 1,
 146                         .flags = IORESOURCE_MEM,
 147                 },
 148 -               .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, },
 149 +               .irqs = { IRQ_CNS3XXX_PCIE0_RC,
 150 +                         IRQ_CNS3XXX_PCIE0_DEVICE,
 151 +                         IRQ_CNS3XXX_PCIE0_DEVICE,
 152 +                         IRQ_CNS3XXX_PCIE0_DEVICE,
 153 +                         IRQ_CNS3XXX_PCIE0_DEVICE,
 154 +                       },
 155                 .hw_pci = {
 156                         .domain = 0,
 157                         .nr_controllers = 1,
 158 @@ -340,7 +346,13 @@ static struct cns3xxx_pcie cns3xxx_pcie[
 159                         .end = CNS3XXX_PCIE1_MEM_BASE + SZ_16M - 1,
 160                         .flags = IORESOURCE_MEM,
 161                 },
 162 -               .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, },
 163 +               .irqs = {
 164 +                       IRQ_CNS3XXX_PCIE1_RC,
 165 +                       IRQ_CNS3XXX_PCIE1_DEVICE,
 166 +                       IRQ_CNS3XXX_PCIE1_DEVICE,
 167 +                       IRQ_CNS3XXX_PCIE1_DEVICE,
 168 +                       IRQ_CNS3XXX_PCIE1_DEVICE,
 169 +               },
 170                 .hw_pci = {
 171                         .domain = 1,
 172                         .nr_controllers = 1,
 173 @@ -460,13 +472,22 @@ void __init cns3xxx_pcie_iotable_init()
 174         }
 175  }
 176
 177 -int __init cns3xxx_pcie_init(void)
 178 +int __init cns3xxx_pcie_init(int *pcie0_irqs, int *pcie1_irqs)
 179  {
 180         int i;
 181
 182         pcibios_min_io = 0;
 183         pcibios_min_mem = 0;
 184
 185 +       if (pcie0_irqs) {
 186 +               for (i = 0; i < 4; i++)
 187 +                       cns3xxx_pcie[0].irqs[i+1] = pcie0_irqs[i];
 188 +       }
 189 +       if (pcie1_irqs) {
 190 +               for (i = 0; i < 4; i++)
 191 +                       cns3xxx_pcie[1].irqs[i+1] = pcie1_irqs[i];
 192 +       }
 193 +
 194         hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0,
 195                         "imprecise external abort");
 196