cns3xxx: reorganize patches, fix pcie io space init order
[openwrt/svn-archive/archive.git] / target / linux / cns3xxx / patches-3.3 / 104-cns3xxx_gpio.patch
1 --- a/arch/arm/mach-cns3xxx/cns3420vb.c
2 +++ b/arch/arm/mach-cns3xxx/cns3420vb.c
3 @@ -216,7 +216,7 @@ static struct map_desc cns3420_io_desc[]
4
5 static void __init cns3420_map_io(void)
6 {
7 - cns3xxx_map_io();
8 + cns3xxx_common_init();
9 iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc));
10
11 cns3420_early_serial_setup();
12 --- a/arch/arm/mach-cns3xxx/core.c
13 +++ b/arch/arm/mach-cns3xxx/core.c
14 @@ -21,6 +21,7 @@
15 #include <asm/hardware/gic.h>
16 #include <asm/smp_twd.h>
17 #include <asm/hardware/cache-l2x0.h>
18 +#include <asm/gpio.h>
19 #include <mach/cns3xxx.h>
20 #include "core.h"
21
22 @@ -72,12 +73,73 @@ static struct map_desc cns3xxx_io_desc[]
23 },
24 };
25
26 -void __init cns3xxx_map_io(void)
27 +static inline void gpio_line_config(u8 line, u32 direction)
28 +{
29 + u32 reg;
30 + if (direction) {
31 + if (line < 32) {
32 + reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
33 + reg |= (1 << line);
34 + __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
35 + } else {
36 + reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
37 + reg |= (1 << (line - 32));
38 + __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
39 + }
40 + } else {
41 + if (line < 32) {
42 + reg = __raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
43 + reg &= ~(1 << line);
44 + __raw_writel(reg, CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_DIR);
45 + } else {
46 + reg = __raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
47 + reg &= ~(1 << (line - 32));
48 + __raw_writel(reg, CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_DIR);
49 + }
50 + }
51 +}
52 +
53 +static int cns3xxx_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
54 +{
55 + gpio_line_config(gpio, CNS3XXX_GPIO_IN);
56 + return 0;
57 +}
58 +
59 +static int cns3xxx_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int level)
60 +{
61 + gpio_line_set(gpio, level);
62 + gpio_line_config(gpio, CNS3XXX_GPIO_OUT);
63 + return 0;
64 +}
65 +
66 +static int cns3xxx_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
67 +{
68 + return gpio_get_value(gpio);
69 +}
70 +
71 +static void cns3xxx_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
72 +{
73 + gpio_set_value(gpio, value);
74 +}
75 +
76 +static struct gpio_chip cns3xxx_gpio_chip = {
77 + .label = "CNS3XXX_GPIO_CHIP",
78 + .direction_input = cns3xxx_gpio_direction_input,
79 + .direction_output = cns3xxx_gpio_direction_output,
80 + .get = cns3xxx_gpio_get_value,
81 + .set = cns3xxx_gpio_set_value,
82 + .base = 0,
83 + .ngpio = 64,
84 +};
85 +
86 +void __init cns3xxx_common_init(void)
87 {
88 #ifdef CONFIG_LOCAL_TIMERS
89 twd_base = (void __iomem *) CNS3XXX_TC11MP_TWD_BASE_VIRT;
90 #endif
91 iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc));
92 +
93 + gpiochip_add(&cns3xxx_gpio_chip);
94 }
95
96 /* used by entry-macro.S */
97 --- a/arch/arm/mach-cns3xxx/core.h
98 +++ b/arch/arm/mach-cns3xxx/core.h
99 @@ -21,7 +21,7 @@ void __init cns3xxx_l2x0_init(void);
100 static inline void cns3xxx_l2x0_init(void) {}
101 #endif /* CONFIG_CACHE_L2X0 */
102
103 -void __init cns3xxx_map_io(void);
104 +void __init cns3xxx_common_init(void);
105 void __init cns3xxx_init_irq(void);
106 void cns3xxx_power_off(void);
107 void cns3xxx_restart(char, const char *);