Update board support for Gateworks Laguna Product family
[openwrt/svn-archive/archive.git] / target / linux / cns3xxx / patches-3.3 / 300-laguna_support.patch
1 --- /dev/null
2 +++ b/arch/arm/mach-cns3xxx/laguna.c
3 @@ -0,0 +1,919 @@
4 +/*
5 + * Gateworks Corporation Laguna Platform
6 + *
7 + * Copyright 2000 Deep Blue Solutions Ltd
8 + * Copyright 2008 ARM Limited
9 + * Copyright 2008 Cavium Networks
10 + * Scott Shu
11 + * Copyright 2010 MontaVista Software, LLC.
12 + * Anton Vorontsov <avorontsov@mvista.com>
13 + * Copyright 2011 Gateworks Corporation
14 + * Chris Lang <clang@gateworks.com>
15 + * Copyright 2012 Gateworks Corporation
16 + * Tim Harvey <tharvey@gateworks.com>
17 + *
18 + * This file is free software; you can redistribute it and/or modify
19 + * it under the terms of the GNU General Public License, Version 2, as
20 + * published by the Free Software Foundation.
21 + */
22 +
23 +#include <linux/init.h>
24 +#include <linux/kernel.h>
25 +#include <linux/compiler.h>
26 +#include <linux/io.h>
27 +#include <linux/gpio.h>
28 +#include <linux/dma-mapping.h>
29 +#include <linux/serial_core.h>
30 +#include <linux/serial_8250.h>
31 +#include <linux/platform_device.h>
32 +#include <linux/mtd/mtd.h>
33 +#include <linux/mtd/physmap.h>
34 +#include <linux/mtd/partitions.h>
35 +#include <linux/leds.h>
36 +#include <linux/i2c.h>
37 +#include <linux/i2c/at24.h>
38 +#include <linux/i2c/pca953x.h>
39 +#include <linux/spi/spi.h>
40 +#include <linux/spi/flash.h>
41 +#include <linux/if_ether.h>
42 +#include <asm/setup.h>
43 +#include <asm/mach-types.h>
44 +#include <asm/mach/arch.h>
45 +#include <asm/mach/map.h>
46 +#include <asm/mach/time.h>
47 +#include <mach/cns3xxx.h>
48 +#include <mach/irqs.h>
49 +#include <mach/platform.h>
50 +#include <mach/pm.h>
51 +#include <asm/hardware/gic.h>
52 +#include "core.h"
53 +#include "devices.h"
54 +
55 +#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
56 +
57 +// Config 1 Bitmap
58 +#define ETH0_LOAD BIT(0)
59 +#define ETH1_LOAD BIT(1)
60 +#define ETH2_LOAD BIT(2)
61 +#define SATA0_LOAD BIT(3)
62 +#define SATA1_LOAD BIT(4)
63 +#define PCM_LOAD BIT(5)
64 +#define I2S_LOAD BIT(6)
65 +#define SPI0_LOAD BIT(7)
66 +#define SPI1_LOAD BIT(8)
67 +#define PCIE0_LOAD BIT(9)
68 +#define PCIE1_LOAD BIT(10)
69 +#define USB0_LOAD BIT(11)
70 +#define USB1_LOAD BIT(12)
71 +#define USB1_ROUTE BIT(13)
72 +#define SD_LOAD BIT(14)
73 +#define UART0_LOAD BIT(15)
74 +#define UART1_LOAD BIT(16)
75 +#define UART2_LOAD BIT(17)
76 +#define MPCI0_LOAD BIT(18)
77 +#define MPCI1_LOAD BIT(19)
78 +#define MPCI2_LOAD BIT(20)
79 +#define MPCI3_LOAD BIT(21)
80 +#define FP_BUT_LOAD BIT(22)
81 +#define FP_BUT_HEADER_LOAD BIT(23)
82 +#define FP_LED_LOAD BIT(24)
83 +#define FP_LED_HEADER_LOAD BIT(25)
84 +#define FP_TAMPER_LOAD BIT(26)
85 +#define HEADER_33V_LOAD BIT(27)
86 +#define SATA_POWER_LOAD BIT(28)
87 +#define FP_POWER_LOAD BIT(29)
88 +#define GPIO_HEADER_LOAD BIT(30)
89 +#define GSP_BAT_LOAD BIT(31)
90 +
91 +// Config 2 Bitmap
92 +#define FAN_LOAD BIT(0)
93 +#define SPI_FLASH_LOAD BIT(1)
94 +#define NOR_FLASH_LOAD BIT(2)
95 +#define GPS_LOAD BIT(3)
96 +#define SUPPLY_5V_LOAD BIT(6)
97 +#define SUPPLY_33V_LOAD BIT(7)
98 +
99 +struct laguna_board_info {
100 + char model[16];
101 + u32 config_bitmap;
102 + u32 config2_bitmap;
103 + u8 nor_flash_size;
104 + u8 spi_flash_size;
105 +};
106 +
107 +static struct laguna_board_info laguna_info __initdata;
108 +
109 +/*
110 + * NOR Flash
111 + */
112 +static struct mtd_partition laguna_nor_partitions[] = {
113 + {
114 + .name = "uboot",
115 + .size = SZ_256K,
116 + .offset = 0,
117 + .mask_flags = MTD_WRITEABLE,
118 + }, {
119 + .name = "params",
120 + .size = SZ_128K,
121 + .offset = SZ_256K,
122 + }, {
123 + .name = "kernel",
124 + .size = SZ_2M,
125 + .offset = SZ_256K + SZ_128K,
126 + }, {
127 + .name = "rootfs",
128 + .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
129 + .offset = SZ_256K + SZ_128K + SZ_2M,
130 + },
131 +};
132 +
133 +static struct physmap_flash_data laguna_nor_pdata = {
134 + .width = 2,
135 + .parts = laguna_nor_partitions,
136 + .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
137 +};
138 +
139 +static struct resource laguna_nor_res = {
140 + .start = CNS3XXX_FLASH_BASE,
141 + .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
142 + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
143 +};
144 +
145 +static struct platform_device laguna_nor_pdev = {
146 + .name = "physmap-flash",
147 + .id = 0,
148 + .resource = &laguna_nor_res,
149 + .num_resources = 1,
150 + .dev = {
151 + .platform_data = &laguna_nor_pdata,
152 + },
153 +};
154 +
155 +/*
156 + * SPI
157 + */
158 +static struct mtd_partition laguna_spi_partitions[] = {
159 + {
160 + .name = "uboot",
161 + .size = SZ_256K,
162 + .offset = 0,
163 + .mask_flags = MTD_WRITEABLE,
164 + }, {
165 + .name = "params",
166 + .size = SZ_256K,
167 + .offset = SZ_256K,
168 + }, {
169 + .name = "kernel",
170 + .size = SZ_1M + SZ_512K,
171 + .offset = SZ_512K,
172 + }, {
173 + .name = "rootfs",
174 + .size = SZ_16M - SZ_2M,
175 + .offset = SZ_2M,
176 + },
177 +};
178 +
179 +static struct flash_platform_data laguna_spi_pdata = {
180 + .parts = laguna_spi_partitions,
181 + .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
182 +};
183 +
184 +static struct spi_board_info __initdata laguna_spi_devices[] = {
185 + {
186 + .modalias = "m25p80",
187 + .platform_data = &laguna_spi_pdata,
188 + .max_speed_hz = 50000000,
189 + .bus_num = 1,
190 + .chip_select = 0,
191 + },
192 +};
193 +
194 +static struct platform_device laguna_spi_controller = {
195 + .name = "cns3xxx_spi",
196 +};
197 +
198 +/*
199 + * LED's
200 + */
201 +static struct gpio_led laguna_gpio_leds[] = {
202 + {
203 + .name = "user1", /* Green Led */
204 + .gpio = 115,
205 + .active_low = 1,
206 + },{
207 + .name = "user2", /* Red Led */
208 + .gpio = 114,
209 + .active_low = 1,
210 + },{
211 + .name = "pwr1", /* Green Led */
212 + .gpio = 116,
213 + .active_low = 1,
214 + },{
215 + .name = "pwr2", /* Yellow Led */
216 + .gpio = 117,
217 + .active_low = 1,
218 + },{
219 + .name = "txd1", /* Green Led */
220 + .gpio = 118,
221 + .active_low = 1,
222 + },{
223 + .name = "txd2", /* Yellow Led */
224 + .gpio = 119,
225 + .active_low = 1,
226 + },{
227 + .name = "rxd1", /* Green Led */
228 + .gpio = 120,
229 + .active_low = 1,
230 + },{
231 + .name = "rxd2", /* Yellow Led */
232 + .gpio = 121,
233 + .active_low = 1,
234 + },{
235 + .name = "ser1", /* Green Led */
236 + .gpio = 122,
237 + .active_low = 1,
238 + },{
239 + .name = "ser2", /* Yellow Led */
240 + .gpio = 123,
241 + .active_low = 1,
242 + },{
243 + .name = "enet1", /* Green Led */
244 + .gpio = 124,
245 + .active_low = 1,
246 + },{
247 + .name = "enet2", /* Yellow Led */
248 + .gpio = 125,
249 + .active_low = 1,
250 + },{
251 + .name = "sig1_1", /* Green Led */
252 + .gpio = 126,
253 + .active_low = 1,
254 + },{
255 + .name = "sig1_2", /* Yellow Led */
256 + .gpio = 127,
257 + .active_low = 1,
258 + },{
259 + .name = "sig2_1", /* Green Led */
260 + .gpio = 128,
261 + .active_low = 1,
262 + },{
263 + .name = "sig2_2", /* Yellow Led */
264 + .gpio = 129,
265 + .active_low = 1,
266 + },{
267 + .name = "sig3_1", /* Green Led */
268 + .gpio = 130,
269 + .active_low = 1,
270 + },{
271 + .name = "sig3_2", /* Yellow Led */
272 + .gpio = 131,
273 + .active_low = 1,
274 + },{
275 + .name = "net1", /*Green Led */
276 + .gpio = 109,
277 + .active_low = 1,
278 + },{
279 + .name = "net2", /* Red Led */
280 + .gpio = 110,
281 + .active_low = 1,
282 + },{
283 + .name = "mod1", /* Green Led */
284 + .gpio = 111,
285 + .active_low = 1,
286 + },{
287 + .name = "mod2", /* Red Led */
288 + .gpio = 112,
289 + .active_low = 1,
290 + },
291 +};
292 +
293 +static struct gpio_led_platform_data laguna_gpio_leds_data = {
294 + .num_leds = 22,
295 + .leds = laguna_gpio_leds,
296 +};
297 +
298 +static struct platform_device laguna_gpio_leds_device = {
299 + .name = "leds-gpio",
300 + .id = -1,
301 + .dev.platform_data = &laguna_gpio_leds_data,
302 +};
303 +
304 +/*
305 + * Ethernet
306 + */
307 +static struct cns3xxx_plat_info laguna_net_data = {
308 + .ports = 0,
309 + .phy = {
310 + 0,
311 + 1,
312 + 2,
313 + },
314 +};
315 +
316 +static struct platform_device laguna_net_device = {
317 + .name = "cns3xxx_eth",
318 + .id = 0,
319 + .dev.platform_data = &laguna_net_data,
320 +};
321 +
322 +/*
323 + * UART
324 + */
325 +static void __init laguna_early_serial_setup(void)
326 +{
327 +#ifdef CONFIG_SERIAL_8250_CONSOLE
328 + static struct uart_port laguna_serial_port = {
329 + .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
330 + .mapbase = CNS3XXX_UART0_BASE,
331 + .irq = IRQ_CNS3XXX_UART0,
332 + .iotype = UPIO_MEM,
333 + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
334 + .regshift = 2,
335 + .uartclk = 24000000,
336 + .line = 0,
337 + .type = PORT_16550A,
338 + .fifosize = 16,
339 + };
340 +
341 + early_serial_setup(&laguna_serial_port);
342 +#endif
343 +}
344 +
345 +static struct resource laguna_uart_resources[] = {
346 + {
347 + .start = CNS3XXX_UART0_BASE,
348 + .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
349 + .flags = IORESOURCE_MEM
350 + },{
351 + .start = CNS3XXX_UART2_BASE,
352 + .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
353 + .flags = IORESOURCE_MEM
354 + },{
355 + .start = CNS3XXX_UART2_BASE,
356 + .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
357 + .flags = IORESOURCE_MEM
358 + },
359 +};
360 +
361 +static struct plat_serial8250_port laguna_uart_data[] = {
362 + {
363 + .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
364 + .mapbase = (CNS3XXX_UART0_BASE),
365 + .irq = IRQ_CNS3XXX_UART0,
366 + .iotype = UPIO_MEM,
367 + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
368 + .regshift = 2,
369 + .uartclk = 24000000,
370 + .type = PORT_16550A,
371 + },{
372 + .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
373 + .mapbase = (CNS3XXX_UART1_BASE),
374 + .irq = IRQ_CNS3XXX_UART1,
375 + .iotype = UPIO_MEM,
376 + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
377 + .regshift = 2,
378 + .uartclk = 24000000,
379 + .type = PORT_16550A,
380 + },{
381 + .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
382 + .mapbase = (CNS3XXX_UART2_BASE),
383 + .irq = IRQ_CNS3XXX_UART2,
384 + .iotype = UPIO_MEM,
385 + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
386 + .regshift = 2,
387 + .uartclk = 24000000,
388 + .type = PORT_16550A,
389 + },
390 +};
391 +
392 +static struct platform_device laguna_uart = {
393 + .name = "serial8250",
394 + .id = PLAT8250_DEV_PLATFORM,
395 + .dev.platform_data = laguna_uart_data,
396 + .num_resources = 3,
397 + .resource = laguna_uart_resources
398 +};
399 +
400 +/*
401 + * USB
402 + */
403 +static struct resource cns3xxx_usb_ehci_resources[] = {
404 + [0] = {
405 + .start = CNS3XXX_USB_BASE,
406 + .end = CNS3XXX_USB_BASE + SZ_16M - 1,
407 + .flags = IORESOURCE_MEM,
408 + },
409 + [1] = {
410 + .start = IRQ_CNS3XXX_USB_EHCI,
411 + .flags = IORESOURCE_IRQ,
412 + },
413 +};
414 +
415 +static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
416 +
417 +static struct platform_device cns3xxx_usb_ehci_device = {
418 + .name = "cns3xxx-ehci",
419 + .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
420 + .resource = cns3xxx_usb_ehci_resources,
421 + .dev = {
422 + .dma_mask = &cns3xxx_usb_ehci_dma_mask,
423 + .coherent_dma_mask = DMA_BIT_MASK(32),
424 + },
425 +};
426 +
427 +static struct resource cns3xxx_usb_ohci_resources[] = {
428 + [0] = {
429 + .start = CNS3XXX_USB_OHCI_BASE,
430 + .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
431 + .flags = IORESOURCE_MEM,
432 + },
433 + [1] = {
434 + .start = IRQ_CNS3XXX_USB_OHCI,
435 + .flags = IORESOURCE_IRQ,
436 + },
437 +};
438 +
439 +static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
440 +
441 +static struct platform_device cns3xxx_usb_ohci_device = {
442 + .name = "cns3xxx-ohci",
443 + .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
444 + .resource = cns3xxx_usb_ohci_resources,
445 + .dev = {
446 + .dma_mask = &cns3xxx_usb_ohci_dma_mask,
447 + .coherent_dma_mask = DMA_BIT_MASK(32),
448 + },
449 +};
450 +
451 +static struct resource cns3xxx_usb_otg_resources[] = {
452 + [0] = {
453 + .start = CNS3XXX_USBOTG_BASE,
454 + .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
455 + .flags = IORESOURCE_MEM,
456 + },
457 + [1] = {
458 + .start = IRQ_CNS3XXX_USB_OTG,
459 + .flags = IORESOURCE_IRQ,
460 + },
461 +};
462 +
463 +static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
464 +
465 +static struct platform_device cns3xxx_usb_otg_device = {
466 + .name = "dwc_otg",
467 + .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
468 + .resource = cns3xxx_usb_otg_resources,
469 + .dev = {
470 + .dma_mask = &cns3xxx_usb_otg_dma_mask,
471 + .coherent_dma_mask = DMA_BIT_MASK(32),
472 + },
473 +};
474 +
475 +/*
476 + * I2C
477 + */
478 +static struct resource laguna_i2c_resource[] = {
479 + {
480 + .start = CNS3XXX_SSP_BASE + 0x20,
481 + .end = 0x7100003f,
482 + .flags = IORESOURCE_MEM,
483 + },{
484 + .start = IRQ_CNS3XXX_I2C,
485 + .flags = IORESOURCE_IRQ,
486 + },
487 +};
488 +
489 +static struct platform_device laguna_i2c_controller = {
490 + .name = "cns3xxx-i2c",
491 + .num_resources = 2,
492 + .resource = laguna_i2c_resource,
493 +};
494 +
495 +static struct memory_accessor *at24_mem_acc;
496 +
497 +static void at24_setup(struct memory_accessor *mem_acc, void *context)
498 +{
499 + char buf[16];
500 +
501 + at24_mem_acc = mem_acc;
502 +
503 + /* Read MAC addresses */
504 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
505 + memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
506 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
507 + memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
508 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
509 + memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
510 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
511 + memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
512 +
513 + /* Read out Model Information */
514 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
515 + memcpy(&laguna_info.model, buf, 16);
516 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
517 + memcpy(&laguna_info.nor_flash_size, buf, 1);
518 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
519 + memcpy(&laguna_info.spi_flash_size, buf, 1);
520 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
521 + memcpy(&laguna_info.config_bitmap, buf, 4);
522 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
523 + memcpy(&laguna_info.config2_bitmap, buf, 4);
524 +};
525 +
526 +static struct at24_platform_data laguna_eeprom_info = {
527 + .byte_len = 1024,
528 + .page_size = 16,
529 + .flags = AT24_FLAG_READONLY,
530 + .setup = at24_setup,
531 +};
532 +
533 +static struct pca953x_platform_data laguna_pca_data = {
534 + .gpio_base = 100,
535 + .irq_base = -1,
536 +};
537 +
538 +static struct pca953x_platform_data laguna_pca2_data = {
539 + .gpio_base = 116,
540 + .irq_base = -1,
541 +};
542 +
543 +static struct i2c_board_info __initdata laguna_i2c_devices[] = {
544 + {
545 + I2C_BOARD_INFO("pca9555", 0x23),
546 + .platform_data = &laguna_pca_data,
547 + },{
548 + I2C_BOARD_INFO("pca9555", 0x27),
549 + .platform_data = &laguna_pca2_data,
550 + },{
551 + I2C_BOARD_INFO("gsp", 0x29),
552 + },{
553 + I2C_BOARD_INFO ("24c08",0x50),
554 + .platform_data = &laguna_eeprom_info,
555 + },{
556 + I2C_BOARD_INFO("ds1672", 0x68),
557 + },
558 +};
559 +
560 +/*
561 + * Watchdog
562 + */
563 +
564 +static struct resource laguna_watchdog_resources[] = {
565 + [0] = {
566 + .start = CNS3XXX_TC11MP_TWD_BASE,
567 + .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
568 + .flags = IORESOURCE_MEM,
569 + },
570 + [1] = {
571 + .start = IRQ_LOCALWDOG,
572 + .end = IRQ_LOCALWDOG,
573 + .flags = IORESOURCE_IRQ,
574 + }
575 +};
576 +
577 +static struct platform_device laguna_watchdog = {
578 + .name = "mpcore_wdt",
579 + .id = -1,
580 + .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
581 + .resource = laguna_watchdog_resources,
582 +};
583 +
584 +/*
585 + * GPIO
586 + */
587 +static struct platform_device laguna_gpio_dev = {
588 + .name = "GPIODEV",
589 + .id = -1,
590 +};
591 +
592 +static struct gpio laguna_gpio_gw2391[] = {
593 + { 0, GPIOF_IN , "*GPS_PPS" },
594 + { 1, GPIOF_IN , "*GSC_IRQ#" },
595 + { 2, GPIOF_IN , "*USB_FAULT#" },
596 + { 5, GPIOF_OUT_INIT_LOW , "*USB0_PCI_SEL" },
597 + { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
598 + { 7, GPIOF_OUT_INIT_LOW , "*USB1_PCI_SEL" },
599 + { 8, GPIOF_OUT_INIT_HIGH, "*PERST#" },
600 + { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN#" },
601 + { 100, GPIOF_IN , "*USER_PB#" },
602 + { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
603 + { 108, GPIOF_IN , "DIO0" },
604 + { 109, GPIOF_IN , "DIO1" },
605 + { 110, GPIOF_IN , "DIO2" },
606 + { 111, GPIOF_IN , "DIO3" },
607 + { 112, GPIOF_IN , "DIO4" },
608 +};
609 +
610 +static struct gpio laguna_gpio_gw2388[] = {
611 + { 0, GPIOF_IN , "*GPS_PPS" },
612 + { 1, GPIOF_IN , "*GSC_IRQ#" },
613 + { 3, GPIOF_IN , "*USB_FAULT#" },
614 + { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
615 + { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
616 + { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
617 + { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
618 + { 100, GPIOF_OUT_INIT_HIGH, "*USER_PB#" },
619 + { 108, GPIOF_IN , "DIO0" },
620 + { 109, GPIOF_IN , "DIO1" },
621 + { 110, GPIOF_IN , "DIO2" },
622 + { 111, GPIOF_IN , "DIO3" },
623 + { 112, GPIOF_IN , "DIO4" },
624 +};
625 +
626 +static struct gpio laguna_gpio_gw2387[] = {
627 + { 0, GPIOF_IN , "*GPS_PPS" },
628 + { 1, GPIOF_IN , "*GSC_IRQ#" },
629 + { 2, GPIOF_IN , "*USB_FAULT#" },
630 + { 5, GPIOF_OUT_INIT_LOW , "*USB_PCI_SEL" },
631 + { 6, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
632 + { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
633 + { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
634 + { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
635 + { 100, GPIOF_IN , "*USER_PB#" },
636 + { 103, GPIOF_OUT_INIT_HIGH, "*V5_EN" },
637 + { 108, GPIOF_IN , "DIO0" },
638 + { 109, GPIOF_IN , "DIO1" },
639 + { 110, GPIOF_IN , "DIO2" },
640 + { 111, GPIOF_IN , "DIO3" },
641 + { 112, GPIOF_IN , "DIO4" },
642 + { 113, GPIOF_IN , "DIO5" },
643 +};
644 +
645 +static struct gpio laguna_gpio_gw2384[] = {
646 + { 0, GPIOF_IN , "*GSC_IRQ#" },
647 + { 1, GPIOF_OUT_INIT_HIGH, "*USB_HST_VBUS_EN" },
648 + { 2, GPIOF_IN , "*USB_HST_FAULT#" },
649 + { 5, GPIOF_IN , "*USB_OTG_FAULT#" },
650 + { 6, GPIOF_OUT_INIT_LOW , "*USB_HST_PCI_SEL" },
651 + { 7, GPIOF_OUT_INIT_LOW , "*GSM_SEL0" },
652 + { 8, GPIOF_OUT_INIT_LOW , "*GSM_SEL1" },
653 + { 9, GPIOF_OUT_INIT_LOW , "*FP_SER_EN" },
654 + { 12, GPIOF_OUT_INIT_LOW , "J10_DIOLED0" },
655 + { 13, GPIOF_OUT_INIT_HIGH, "*I2CMUX_RST#" },
656 + { 14, GPIOF_OUT_INIT_LOW , "J10_DIOLED1" },
657 + { 15, GPIOF_OUT_INIT_LOW , "J10_DIOLED2" },
658 + { 100, GPIOF_IN , "*USER_PB#" },
659 + { 103, GPIOF_OUT_INIT_HIGH, "V5_EN" },
660 + { 108, GPIOF_IN , "J9_DIOGSC0" },
661 +};
662 +
663 +static struct gpio laguna_gpio_gw2382[] = {
664 + { 0, GPIOF_IN , "*GPS_PPS" },
665 + { 1, GPIOF_IN , "*GSC_IRQ#" },
666 + { 2, GPIOF_OUT_INIT_HIGH, "*PCIE_RST#" },
667 + { 3, GPIOF_IN , "GPIO0" },
668 + { 4, GPIOF_IN , "GPIO1" },
669 + { 9, GPIOF_OUT_INIT_HIGH, "*USB_VBUS_EN" },
670 + { 10, GPIOF_OUT_INIT_HIGH, "*USB_PCI_SEL#" },
671 + { 100, GPIOF_IN , "DIO0" },
672 + { 101, GPIOF_IN , "DIO1" },
673 +};
674 +
675 +static struct gpio laguna_gpio_gw2380[] = {
676 + { 0, GPIOF_IN , "*GPS_PPS" },
677 + { 1, GPIOF_IN , "*GSC_IRQ#" },
678 + { 3, GPIOF_IN , "GPIO0" },
679 + { 8, GPIOF_IN , "GPIO1" },
680 + { 100, GPIOF_IN , "DIO0" },
681 + { 101, GPIOF_IN , "DIO1" },
682 + { 102, GPIOF_IN , "DIO2" },
683 + { 103, GPIOF_IN , "DIO3" },
684 +};
685 +
686 +/*
687 + * Initialization
688 + */
689 +static void __init laguna_init(void)
690 +{
691 + cns3xxx_l2x0_init();
692 +
693 + platform_device_register(&laguna_watchdog);
694 +
695 + platform_device_register(&laguna_i2c_controller);
696 +
697 + i2c_register_board_info(0, ARRAY_AND_SIZE(laguna_i2c_devices));
698 +
699 + pm_power_off = cns3xxx_power_off;
700 +}
701 +
702 +static struct map_desc laguna_io_desc[] __initdata = {
703 + {
704 + .virtual = CNS3XXX_UART0_BASE_VIRT,
705 + .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
706 + .length = SZ_4K,
707 + .type = MT_DEVICE,
708 + },{
709 + .virtual = CNS3XXX_UART1_BASE_VIRT,
710 + .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
711 + .length = SZ_4K,
712 + .type = MT_DEVICE,
713 + },{
714 + .virtual = CNS3XXX_UART2_BASE_VIRT,
715 + .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
716 + .length = SZ_4K,
717 + .type = MT_DEVICE,
718 + },
719 +};
720 +
721 +static void __init laguna_map_io(void)
722 +{
723 + cns3xxx_common_init();
724 + cns3xxx_pcie_iotable_init(0x3);
725 + iotable_init(ARRAY_AND_SIZE(laguna_io_desc));
726 + laguna_early_serial_setup();
727 +}
728 +
729 +static int laguna_register_gpio(struct gpio *array, size_t num)
730 +{
731 + int i, err, ret;
732 +
733 + ret = 0;
734 + for (i = 0; i < num; i++, array++) {
735 + const char *label = array->label;
736 + if (label[0] == '*')
737 + label++;
738 + err = gpio_request_one(array->gpio, array->flags, label);
739 + if (err)
740 + ret = err;
741 + else {
742 + err = gpio_export(array->gpio, array->label[0] != '*');
743 + }
744 + }
745 + return ret;
746 +}
747 +
748 +static int __init laguna_model_setup(void)
749 +{
750 + u32 __iomem *mem;
751 + u32 reg;
752 + u8 pcie_bitmap = 0;
753 +
754 + printk("Running on Gateworks Laguna %s\n", laguna_info.model);
755 +
756 + if (strncmp(laguna_info.model, "GW", 2) == 0) {
757 + if (laguna_info.config_bitmap & ETH0_LOAD)
758 + laguna_net_data.ports |= BIT(0);
759 + if (laguna_info.config_bitmap & ETH1_LOAD)
760 + laguna_net_data.ports |= BIT(1);
761 + if (laguna_info.config_bitmap & ETH2_LOAD)
762 + laguna_net_data.ports |= BIT(2);
763 + if (laguna_net_data.ports)
764 + platform_device_register(&laguna_net_device);
765 +
766 + if ((laguna_info.config_bitmap & SATA0_LOAD) ||
767 + (laguna_info.config_bitmap & SATA1_LOAD))
768 + cns3xxx_ahci_init();
769 +
770 + if (laguna_info.config_bitmap & (PCIE0_LOAD))
771 + pcie_bitmap |= 0x1;
772 +
773 + if (laguna_info.config_bitmap & (PCIE1_LOAD))
774 + pcie_bitmap |= 0x2;
775 +
776 + cns3xxx_pcie_init(pcie_bitmap);
777 +
778 + if (laguna_info.config_bitmap & (USB0_LOAD)) {
779 + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
780 +
781 + /* DRVVBUS pins share with GPIOA */
782 + mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
783 + reg = __raw_readl(mem);
784 + reg |= 0x8;
785 + __raw_writel(reg, mem);
786 +
787 + /* Enable OTG */
788 + mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
789 + reg = __raw_readl(mem);
790 + reg &= ~(1 << 10);
791 + __raw_writel(reg, mem);
792 +
793 + platform_device_register(&cns3xxx_usb_otg_device);
794 + }
795 +
796 + if (laguna_info.config_bitmap & (USB1_LOAD)) {
797 + platform_device_register(&cns3xxx_usb_ehci_device);
798 + platform_device_register(&cns3xxx_usb_ohci_device);
799 + }
800 +
801 + if (laguna_info.config_bitmap & (SD_LOAD))
802 + cns3xxx_sdhci_init();
803 +
804 + if (laguna_info.config_bitmap & (UART0_LOAD))
805 + laguna_uart.num_resources = 1;
806 + if (laguna_info.config_bitmap & (UART1_LOAD))
807 + laguna_uart.num_resources = 2;
808 + if (laguna_info.config_bitmap & (UART2_LOAD))
809 + laguna_uart.num_resources = 3;
810 + platform_device_register(&laguna_uart);
811 +
812 + if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
813 + switch (laguna_info.nor_flash_size) {
814 + case 1:
815 + laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
816 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
817 + break;
818 + case 2:
819 + laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
820 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
821 + break;
822 + case 3:
823 + laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
824 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
825 + break;
826 + case 4:
827 + laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
828 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
829 + break;
830 + case 5:
831 + laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
832 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
833 + break;
834 + }
835 + platform_device_register(&laguna_nor_pdev);
836 + }
837 +
838 + if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
839 + switch (laguna_info.spi_flash_size) {
840 + case 1:
841 + laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
842 + break;
843 + case 2:
844 + laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
845 + break;
846 + case 3:
847 + laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
848 + break;
849 + case 4:
850 + laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
851 + break;
852 + case 5:
853 + laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
854 + break;
855 + }
856 + spi_register_board_info(ARRAY_AND_SIZE(laguna_spi_devices));
857 + }
858 +
859 + if ((laguna_info.config_bitmap & SPI0_LOAD) ||
860 + (laguna_info.config_bitmap & SPI1_LOAD))
861 + platform_device_register(&laguna_spi_controller);
862 +
863 + /*
864 + * Do any model specific setup not known by the bitmap by matching
865 + * the first 6 characters of the model name
866 + */
867 +
868 + if ( (strncmp(laguna_info.model, "GW2388", 6) == 0)
869 + || (strncmp(laguna_info.model, "GW2389", 6) == 0) )
870 + {
871 + // configure GPIO's
872 + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2388));
873 + // configure LED's
874 + laguna_gpio_leds_data.num_leds = 2;
875 + } else if (strncmp(laguna_info.model, "GW2387", 6) == 0) {
876 + // configure GPIO's
877 + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2387));
878 + // configure LED's
879 + laguna_gpio_leds_data.num_leds = 2;
880 + } else if (strncmp(laguna_info.model, "GW2384", 6) == 0) {
881 + // configure GPIO's
882 + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2384));
883 + // configure LED's
884 + laguna_gpio_leds_data.num_leds = 1;
885 + } else if (strncmp(laguna_info.model, "GW2382", 6) == 0) {
886 + // configure GPIO's
887 + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2382));
888 + // configure LED's
889 + laguna_gpio_leds[0].gpio = 107;
890 + laguna_gpio_leds_data.num_leds = 1;
891 + } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
892 + // configure GPIO's
893 + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2380));
894 + // configure LED's
895 + laguna_gpio_leds[0].gpio = 107;
896 + laguna_gpio_leds[1].gpio = 106;
897 + laguna_gpio_leds_data.num_leds = 2;
898 + } else if (strncmp(laguna_info.model, "GW2391", 6) == 0) {
899 + // configure GPIO's
900 + laguna_register_gpio(ARRAY_AND_SIZE(laguna_gpio_gw2391));
901 + // configure LED's
902 + laguna_gpio_leds_data.num_leds = 2;
903 + }
904 + platform_device_register(&laguna_gpio_leds_device);
905 + platform_device_register(&laguna_gpio_dev);
906 + } else {
907 + // Do some defaults here, not sure what yet
908 + }
909 + return 0;
910 +}
911 +
912 +late_initcall(laguna_model_setup);
913 +
914 +MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
915 + .atag_offset = 0x100,
916 + .map_io = laguna_map_io,
917 + .init_irq = cns3xxx_init_irq,
918 + .timer = &cns3xxx_timer,
919 + .handle_irq = gic_handle_irq,
920 + .init_machine = laguna_init,
921 + .restart = cns3xxx_restart,
922 +MACHINE_END
923 --- a/arch/arm/mach-cns3xxx/Kconfig
924 +++ b/arch/arm/mach-cns3xxx/Kconfig
925 @@ -11,4 +11,14 @@ config MACH_CNS3420VB
926 This is a platform with an on-board ARM11 MPCore and has support
927 for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
928
929 +config MACH_GW2388
930 + bool "Support for Gateworks Laguna Platform"
931 + select HAVE_ARM_SCU if SMP
932 + select MIGHT_HAVE_PCI
933 + help
934 + Include support for the Gateworks Laguna Platform
935 +
936 + This is a platform with an on-board ARM11 MPCore and has support
937 + for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
938 +
939 endmenu
940 --- a/arch/arm/mach-cns3xxx/Makefile
941 +++ b/arch/arm/mach-cns3xxx/Makefile
942 @@ -1,6 +1,7 @@
943 obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
944 obj-$(CONFIG_PCI) += pcie.o
945 obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
946 +obj-$(CONFIG_MACH_GW2388) += laguna.o
947 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
948 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
949 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o