cns3xxx: reorganize patches, fix pcie io space init order
[openwrt/svn-archive/archive.git] / target / linux / cns3xxx / patches-3.3 / 300-laguna_support.patch
1 --- /dev/null
2 +++ b/arch/arm/mach-cns3xxx/laguna.c
3 @@ -0,0 +1,765 @@
4 +/*
5 + * Gateworks Corporation Laguna Platform
6 + *
7 + * Copyright 2000 Deep Blue Solutions Ltd
8 + * Copyright 2008 ARM Limited
9 + * Copyright 2008 Cavium Networks
10 + * Scott Shu
11 + * Copyright 2010 MontaVista Software, LLC.
12 + * Anton Vorontsov <avorontsov@mvista.com>
13 + * Copyright 2011 Gateworks Corporation
14 + * Chris Lang <clang@gateworks.com>
15 + *
16 + * This file is free software; you can redistribute it and/or modify
17 + * it under the terms of the GNU General Public License, Version 2, as
18 + * published by the Free Software Foundation.
19 + */
20 +
21 +#include <linux/init.h>
22 +#include <linux/kernel.h>
23 +#include <linux/compiler.h>
24 +#include <linux/io.h>
25 +#include <linux/dma-mapping.h>
26 +#include <linux/serial_core.h>
27 +#include <linux/serial_8250.h>
28 +#include <linux/platform_device.h>
29 +#include <linux/mtd/mtd.h>
30 +#include <linux/mtd/physmap.h>
31 +#include <linux/mtd/partitions.h>
32 +#include <linux/leds.h>
33 +#include <linux/i2c.h>
34 +#include <linux/i2c/at24.h>
35 +#include <linux/i2c/pca953x.h>
36 +#include <linux/spi/spi.h>
37 +#include <linux/spi/flash.h>
38 +#include <linux/if_ether.h>
39 +#include <asm/setup.h>
40 +#include <asm/mach-types.h>
41 +#include <asm/mach/arch.h>
42 +#include <asm/mach/map.h>
43 +#include <asm/mach/time.h>
44 +#include <mach/cns3xxx.h>
45 +#include <mach/irqs.h>
46 +#include <mach/platform.h>
47 +#include <mach/pm.h>
48 +#include <asm/hardware/gic.h>
49 +#include "core.h"
50 +#include "devices.h"
51 +
52 +// Config 1 Bitmap
53 +#define ETH0_LOAD BIT(0)
54 +#define ETH1_LOAD BIT(1)
55 +#define ETH2_LOAD BIT(2)
56 +#define SATA0_LOAD BIT(3)
57 +#define SATA1_LOAD BIT(4)
58 +#define PCM_LOAD BIT(5)
59 +#define I2S_LOAD BIT(6)
60 +#define SPI0_LOAD BIT(7)
61 +#define SPI1_LOAD BIT(8)
62 +#define PCIE0_LOAD BIT(9)
63 +#define PCIE1_LOAD BIT(10)
64 +#define USB0_LOAD BIT(11)
65 +#define USB1_LOAD BIT(12)
66 +#define USB1_ROUTE BIT(13)
67 +#define SD_LOAD BIT(14)
68 +#define UART0_LOAD BIT(15)
69 +#define UART1_LOAD BIT(16)
70 +#define UART2_LOAD BIT(17)
71 +#define MPCI0_LOAD BIT(18)
72 +#define MPCI1_LOAD BIT(19)
73 +#define MPCI2_LOAD BIT(20)
74 +#define MPCI3_LOAD BIT(21)
75 +#define FP_BUT_LOAD BIT(22)
76 +#define FP_BUT_HEADER_LOAD BIT(23)
77 +#define FP_LED_LOAD BIT(24)
78 +#define FP_LED_HEADER_LOAD BIT(25)
79 +#define FP_TAMPER_LOAD BIT(26)
80 +#define HEADER_33V_LOAD BIT(27)
81 +#define SATA_POWER_LOAD BIT(28)
82 +#define FP_POWER_LOAD BIT(29)
83 +#define GPIO_HEADER_LOAD BIT(30)
84 +#define GSP_BAT_LOAD BIT(31)
85 +
86 +// Config 2 Bitmap
87 +#define FAN_LOAD BIT(0)
88 +#define SPI_FLASH_LOAD BIT(1)
89 +#define NOR_FLASH_LOAD BIT(2)
90 +#define GPS_LOAD BIT(3)
91 +#define SUPPLY_5V_LOAD BIT(6)
92 +#define SUPPLY_33V_LOAD BIT(7)
93 +
94 +struct laguna_board_info {
95 + char model[16];
96 + u32 config_bitmap;
97 + u32 config2_bitmap;
98 + u8 nor_flash_size;
99 + u8 spi_flash_size;
100 +};
101 +
102 +static struct laguna_board_info laguna_info;
103 +
104 +/*
105 + * NOR Flash
106 + */
107 +static struct mtd_partition laguna_nor_partitions[] = {
108 + {
109 + .name = "uboot",
110 + .size = SZ_256K,
111 + .offset = 0,
112 + .mask_flags = MTD_WRITEABLE,
113 + }, {
114 + .name = "params",
115 + .size = SZ_128K,
116 + .offset = SZ_256K,
117 + }, {
118 + .name = "kernel",
119 + .size = SZ_2M,
120 + .offset = SZ_256K + SZ_128K,
121 + }, {
122 + .name = "rootfs",
123 + .size = SZ_16M - SZ_256K - SZ_128K - SZ_2M,
124 + .offset = SZ_256K + SZ_128K + SZ_2M,
125 + },
126 +};
127 +
128 +static struct physmap_flash_data laguna_nor_pdata = {
129 + .width = 2,
130 + .parts = laguna_nor_partitions,
131 + .nr_parts = ARRAY_SIZE(laguna_nor_partitions),
132 +};
133 +
134 +static struct resource laguna_nor_res = {
135 + .start = CNS3XXX_FLASH_BASE,
136 + .end = CNS3XXX_FLASH_BASE + SZ_128M - 1,
137 + .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT,
138 +};
139 +
140 +static struct platform_device laguna_nor_pdev = {
141 + .name = "physmap-flash",
142 + .id = 0,
143 + .resource = &laguna_nor_res,
144 + .num_resources = 1,
145 + .dev = {
146 + .platform_data = &laguna_nor_pdata,
147 + },
148 +};
149 +
150 +/*
151 + * SPI
152 + */
153 +static struct mtd_partition laguna_spi_partitions[] = {
154 + {
155 + .name = "uboot",
156 + .size = SZ_256K,
157 + .offset = 0,
158 + .mask_flags = MTD_WRITEABLE,
159 + }, {
160 + .name = "params",
161 + .size = SZ_256K,
162 + .offset = SZ_256K,
163 + }, {
164 + .name = "kernel",
165 + .size = SZ_1M + SZ_512K,
166 + .offset = SZ_512K,
167 + }, {
168 + .name = "rootfs",
169 + .size = SZ_16M - SZ_2M,
170 + .offset = SZ_2M,
171 + },
172 +};
173 +
174 +static struct flash_platform_data laguna_spi_pdata = {
175 + .parts = laguna_spi_partitions,
176 + .nr_parts = ARRAY_SIZE(laguna_spi_partitions),
177 +};
178 +
179 +static struct spi_board_info __initdata laguna_spi_devices[] = {
180 + {
181 + .modalias = "m25p80",
182 + .platform_data = &laguna_spi_pdata,
183 + .max_speed_hz = 50000000,
184 + .bus_num = 1,
185 + .chip_select = 0,
186 + },
187 +};
188 +
189 +static struct platform_device laguna_spi_controller = {
190 + .name = "cns3xxx_spi",
191 +};
192 +
193 +/*
194 + * LED's
195 + */
196 +static struct gpio_led laguna_gpio_leds[] = {
197 + {
198 + .name = "user1", /* Green Led */
199 + .gpio = 115,
200 + .active_low = 1,
201 + },{
202 + .name = "user2", /* Red Led */
203 + .gpio = 114,
204 + .active_low = 1,
205 + },{
206 + .name = "pwr1", /* Green Led */
207 + .gpio = 116,
208 + .active_low = 1,
209 + },{
210 + .name = "pwr2", /* Yellow Led */
211 + .gpio = 117,
212 + .active_low = 1,
213 + },{
214 + .name = "txd1", /* Green Led */
215 + .gpio = 118,
216 + .active_low = 1,
217 + },{
218 + .name = "txd2", /* Yellow Led */
219 + .gpio = 119,
220 + .active_low = 1,
221 + },{
222 + .name = "rxd1", /* Green Led */
223 + .gpio = 120,
224 + .active_low = 1,
225 + },{
226 + .name = "rxd2", /* Yellow Led */
227 + .gpio = 121,
228 + .active_low = 1,
229 + },{
230 + .name = "ser1", /* Green Led */
231 + .gpio = 122,
232 + .active_low = 1,
233 + },{
234 + .name = "ser2", /* Yellow Led */
235 + .gpio = 123,
236 + .active_low = 1,
237 + },{
238 + .name = "enet1", /* Green Led */
239 + .gpio = 124,
240 + .active_low = 1,
241 + },{
242 + .name = "enet2", /* Yellow Led */
243 + .gpio = 125,
244 + .active_low = 1,
245 + },{
246 + .name = "sig1_1", /* Green Led */
247 + .gpio = 126,
248 + .active_low = 1,
249 + },{
250 + .name = "sig1_2", /* Yellow Led */
251 + .gpio = 127,
252 + .active_low = 1,
253 + },{
254 + .name = "sig2_1", /* Green Led */
255 + .gpio = 128,
256 + .active_low = 1,
257 + },{
258 + .name = "sig2_2", /* Yellow Led */
259 + .gpio = 129,
260 + .active_low = 1,
261 + },{
262 + .name = "sig3_1", /* Green Led */
263 + .gpio = 130,
264 + .active_low = 1,
265 + },{
266 + .name = "sig3_2", /* Yellow Led */
267 + .gpio = 131,
268 + .active_low = 1,
269 + },{
270 + .name = "net1", /*Green Led */
271 + .gpio = 109,
272 + .active_low = 1,
273 + },{
274 + .name = "net2", /* Red Led */
275 + .gpio = 110,
276 + .active_low = 1,
277 + },{
278 + .name = "mod1", /* Green Led */
279 + .gpio = 111,
280 + .active_low = 1,
281 + },{
282 + .name = "mod2", /* Red Led */
283 + .gpio = 112,
284 + .active_low = 1,
285 + },
286 +};
287 +
288 +static struct gpio_led_platform_data laguna_gpio_leds_data = {
289 + .num_leds = 22,
290 + .leds = laguna_gpio_leds,
291 +};
292 +
293 +static struct platform_device laguna_gpio_leds_device = {
294 + .name = "leds-gpio",
295 + .id = -1,
296 + .dev.platform_data = &laguna_gpio_leds_data,
297 +};
298 +
299 +/*
300 + * Ethernet
301 + */
302 +static struct cns3xxx_plat_info laguna_net_data = {
303 + .ports = 0,
304 + .phy = {
305 + 0,
306 + 1,
307 + 2,
308 + },
309 +};
310 +
311 +static struct platform_device laguna_net_device = {
312 + .name = "cns3xxx_eth",
313 + .id = 0,
314 + .dev.platform_data = &laguna_net_data,
315 +};
316 +
317 +/*
318 + * UART
319 + */
320 +static void __init laguna_early_serial_setup(void)
321 +{
322 +#ifdef CONFIG_SERIAL_8250_CONSOLE
323 + static struct uart_port laguna_serial_port = {
324 + .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT,
325 + .mapbase = CNS3XXX_UART0_BASE,
326 + .irq = IRQ_CNS3XXX_UART0,
327 + .iotype = UPIO_MEM,
328 + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE,
329 + .regshift = 2,
330 + .uartclk = 24000000,
331 + .line = 0,
332 + .type = PORT_16550A,
333 + .fifosize = 16,
334 + };
335 +
336 + early_serial_setup(&laguna_serial_port);
337 +#endif
338 +}
339 +
340 +static struct resource laguna_uart_resources[] = {
341 + {
342 + .start = CNS3XXX_UART0_BASE,
343 + .end = CNS3XXX_UART0_BASE + SZ_4K - 1,
344 + .flags = IORESOURCE_MEM
345 + },{
346 + .start = CNS3XXX_UART2_BASE,
347 + .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
348 + .flags = IORESOURCE_MEM
349 + },{
350 + .start = CNS3XXX_UART2_BASE,
351 + .end = CNS3XXX_UART2_BASE + SZ_4K - 1,
352 + .flags = IORESOURCE_MEM
353 + },
354 +};
355 +
356 +static struct plat_serial8250_port laguna_uart_data[] = {
357 + {
358 + .membase = (char*) (CNS3XXX_UART0_BASE_VIRT),
359 + .mapbase = (CNS3XXX_UART0_BASE),
360 + .irq = IRQ_CNS3XXX_UART0,
361 + .iotype = UPIO_MEM,
362 + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
363 + .regshift = 2,
364 + .uartclk = 24000000,
365 + .type = PORT_16550A,
366 + },{
367 + .membase = (char*) (CNS3XXX_UART1_BASE_VIRT),
368 + .mapbase = (CNS3XXX_UART1_BASE),
369 + .irq = IRQ_CNS3XXX_UART1,
370 + .iotype = UPIO_MEM,
371 + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
372 + .regshift = 2,
373 + .uartclk = 24000000,
374 + .type = PORT_16550A,
375 + },{
376 + .membase = (char*) (CNS3XXX_UART2_BASE_VIRT),
377 + .mapbase = (CNS3XXX_UART2_BASE),
378 + .irq = IRQ_CNS3XXX_UART2,
379 + .iotype = UPIO_MEM,
380 + .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE | UPF_NO_TXEN_TEST,
381 + .regshift = 2,
382 + .uartclk = 24000000,
383 + .type = PORT_16550A,
384 + },
385 +};
386 +
387 +static struct platform_device laguna_uart = {
388 + .name = "serial8250",
389 + .id = PLAT8250_DEV_PLATFORM,
390 + .dev.platform_data = laguna_uart_data,
391 + .num_resources = 3,
392 + .resource = laguna_uart_resources
393 +};
394 +
395 +/*
396 + * USB
397 + */
398 +static struct resource cns3xxx_usb_ehci_resources[] = {
399 + [0] = {
400 + .start = CNS3XXX_USB_BASE,
401 + .end = CNS3XXX_USB_BASE + SZ_16M - 1,
402 + .flags = IORESOURCE_MEM,
403 + },
404 + [1] = {
405 + .start = IRQ_CNS3XXX_USB_EHCI,
406 + .flags = IORESOURCE_IRQ,
407 + },
408 +};
409 +
410 +static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32);
411 +
412 +static struct platform_device cns3xxx_usb_ehci_device = {
413 + .name = "cns3xxx-ehci",
414 + .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources),
415 + .resource = cns3xxx_usb_ehci_resources,
416 + .dev = {
417 + .dma_mask = &cns3xxx_usb_ehci_dma_mask,
418 + .coherent_dma_mask = DMA_BIT_MASK(32),
419 + },
420 +};
421 +
422 +static struct resource cns3xxx_usb_ohci_resources[] = {
423 + [0] = {
424 + .start = CNS3XXX_USB_OHCI_BASE,
425 + .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1,
426 + .flags = IORESOURCE_MEM,
427 + },
428 + [1] = {
429 + .start = IRQ_CNS3XXX_USB_OHCI,
430 + .flags = IORESOURCE_IRQ,
431 + },
432 +};
433 +
434 +static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32);
435 +
436 +static struct platform_device cns3xxx_usb_ohci_device = {
437 + .name = "cns3xxx-ohci",
438 + .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources),
439 + .resource = cns3xxx_usb_ohci_resources,
440 + .dev = {
441 + .dma_mask = &cns3xxx_usb_ohci_dma_mask,
442 + .coherent_dma_mask = DMA_BIT_MASK(32),
443 + },
444 +};
445 +
446 +static struct resource cns3xxx_usb_otg_resources[] = {
447 + [0] = {
448 + .start = CNS3XXX_USBOTG_BASE,
449 + .end = CNS3XXX_USBOTG_BASE + SZ_16M - 1,
450 + .flags = IORESOURCE_MEM,
451 + },
452 + [1] = {
453 + .start = IRQ_CNS3XXX_USB_OTG,
454 + .flags = IORESOURCE_IRQ,
455 + },
456 +};
457 +
458 +static u64 cns3xxx_usb_otg_dma_mask = DMA_BIT_MASK(32);
459 +
460 +static struct platform_device cns3xxx_usb_otg_device = {
461 + .name = "dwc_otg",
462 + .num_resources = ARRAY_SIZE(cns3xxx_usb_otg_resources),
463 + .resource = cns3xxx_usb_otg_resources,
464 + .dev = {
465 + .dma_mask = &cns3xxx_usb_otg_dma_mask,
466 + .coherent_dma_mask = DMA_BIT_MASK(32),
467 + },
468 +};
469 +
470 +/*
471 + * I2C
472 + */
473 +static struct resource laguna_i2c_resource[] = {
474 + {
475 + .start = CNS3XXX_SSP_BASE + 0x20,
476 + .end = 0x7100003f,
477 + .flags = IORESOURCE_MEM,
478 + },{
479 + .start = IRQ_CNS3XXX_I2C,
480 + .flags = IORESOURCE_IRQ,
481 + },
482 +};
483 +
484 +static struct platform_device laguna_i2c_controller = {
485 + .name = "cns3xxx-i2c",
486 + .num_resources = 2,
487 + .resource = laguna_i2c_resource,
488 +};
489 +
490 +static struct memory_accessor *at24_mem_acc;
491 +
492 +static void at24_setup(struct memory_accessor *mem_acc, void *context)
493 +{
494 + char buf[16];
495 +
496 + at24_mem_acc = mem_acc;
497 +
498 + /* Read MAC addresses */
499 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x100, 6) == 6)
500 + memcpy(&laguna_net_data.hwaddr[0], buf, ETH_ALEN);
501 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x106, 6) == 6)
502 + memcpy(&laguna_net_data.hwaddr[1], buf, ETH_ALEN);
503 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x10C, 6) == 6)
504 + memcpy(&laguna_net_data.hwaddr[2], buf, ETH_ALEN);
505 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x112, 6) == 6)
506 + memcpy(&laguna_net_data.hwaddr[3], buf, ETH_ALEN);
507 +
508 + /* Read out Model Information */
509 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x130, 16) == 16)
510 + memcpy(&laguna_info.model, buf, 16);
511 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x140, 1) == 1)
512 + memcpy(&laguna_info.nor_flash_size, buf, 1);
513 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x141, 1) == 1)
514 + memcpy(&laguna_info.spi_flash_size, buf, 1);
515 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x142, 4) == 4)
516 + memcpy(&laguna_info.config_bitmap, buf, 4);
517 + if (at24_mem_acc->read(at24_mem_acc, buf, 0x146, 4) == 4)
518 + memcpy(&laguna_info.config2_bitmap, buf, 4);
519 +};
520 +
521 +static struct at24_platform_data laguna_eeprom_info = {
522 + .byte_len = 1024,
523 + .page_size = 16,
524 + .flags = AT24_FLAG_READONLY,
525 + .setup = at24_setup,
526 +};
527 +
528 +static struct pca953x_platform_data laguna_pca_data = {
529 + .gpio_base = 100,
530 + .irq_base = -1,
531 +};
532 +
533 +static struct pca953x_platform_data laguna_pca2_data = {
534 + .gpio_base = 116,
535 + .irq_base = -1,
536 +};
537 +
538 +static struct i2c_board_info __initdata laguna_i2c_devices[] = {
539 + {
540 + I2C_BOARD_INFO("pca9555", 0x23),
541 + .platform_data = &laguna_pca_data,
542 + },{
543 + I2C_BOARD_INFO("pca9555", 0x27),
544 + .platform_data = &laguna_pca2_data,
545 + },{
546 + I2C_BOARD_INFO("gsp", 0x29),
547 + },{
548 + I2C_BOARD_INFO ("24c08",0x50),
549 + .platform_data = &laguna_eeprom_info,
550 + },{
551 + I2C_BOARD_INFO("ds1672", 0x68),
552 + },
553 +};
554 +
555 +/*
556 + * Watchdog
557 + */
558 +
559 +static struct resource laguna_watchdog_resources[] = {
560 + [0] = {
561 + .start = CNS3XXX_TC11MP_TWD_BASE,
562 + .end = CNS3XXX_TC11MP_TWD_BASE + SZ_4K - 1,
563 + .flags = IORESOURCE_MEM,
564 + },
565 + [1] = {
566 + .start = IRQ_LOCALWDOG,
567 + .end = IRQ_LOCALWDOG,
568 + .flags = IORESOURCE_IRQ,
569 + }
570 +};
571 +
572 +static struct platform_device laguna_watchdog = {
573 + .name = "mpcore_wdt",
574 + .id = -1,
575 + .num_resources = ARRAY_SIZE(laguna_watchdog_resources),
576 + .resource = laguna_watchdog_resources,
577 +};
578 +
579 +/*
580 + * Initialization
581 + */
582 +
583 +static void __init laguna_init(void)
584 +{
585 + cns3xxx_l2x0_init();
586 +
587 + platform_device_register(&laguna_watchdog);
588 +
589 + platform_device_register(&laguna_i2c_controller);
590 +
591 + i2c_register_board_info(0, laguna_i2c_devices,
592 + ARRAY_SIZE(laguna_i2c_devices));
593 +
594 + pm_power_off = cns3xxx_power_off;
595 +}
596 +
597 +static struct map_desc laguna_io_desc[] __initdata = {
598 + {
599 + .virtual = CNS3XXX_UART0_BASE_VIRT,
600 + .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE),
601 + .length = SZ_4K,
602 + .type = MT_DEVICE,
603 + },{
604 + .virtual = CNS3XXX_UART1_BASE_VIRT,
605 + .pfn = __phys_to_pfn(CNS3XXX_UART1_BASE),
606 + .length = SZ_4K,
607 + .type = MT_DEVICE,
608 + },{
609 + .virtual = CNS3XXX_UART2_BASE_VIRT,
610 + .pfn = __phys_to_pfn(CNS3XXX_UART2_BASE),
611 + .length = SZ_4K,
612 + .type = MT_DEVICE,
613 + },
614 +};
615 +
616 +static void __init laguna_map_io(void)
617 +{
618 + cns3xxx_common_init();
619 + cns3xxx_pcie_iotable_init(0x3);
620 + iotable_init(laguna_io_desc, ARRAY_SIZE(laguna_io_desc));
621 + laguna_early_serial_setup();
622 +}
623 +
624 +static int __init laguna_model_setup(void)
625 +{
626 + u32 __iomem *mem;
627 + u32 reg;
628 + u8 pcie_bitmap = 0;
629 +
630 + printk("Running on Gateworks Laguna %s\n", laguna_info.model);
631 +
632 + if (strncmp(laguna_info.model, "GW", 2) == 0) {
633 + if (laguna_info.config_bitmap & ETH0_LOAD)
634 + laguna_net_data.ports |= BIT(0);
635 + if (laguna_info.config_bitmap & ETH1_LOAD)
636 + laguna_net_data.ports |= BIT(1);
637 + if (laguna_info.config_bitmap & ETH2_LOAD)
638 + laguna_net_data.ports |= BIT(2);
639 + if (laguna_net_data.ports)
640 + platform_device_register(&laguna_net_device);
641 +
642 + if ((laguna_info.config_bitmap & SATA0_LOAD) ||
643 + (laguna_info.config_bitmap & SATA1_LOAD))
644 + cns3xxx_ahci_init();
645 +
646 + if (laguna_info.config_bitmap & (PCIE0_LOAD))
647 + pcie_bitmap |= 0x1;
648 +
649 + if (laguna_info.config_bitmap & (PCIE1_LOAD))
650 + pcie_bitmap |= 0x2;
651 +
652 + cns3xxx_pcie_init(pcie_bitmap);
653 +
654 + if (laguna_info.config_bitmap & (USB0_LOAD)) {
655 + cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB);
656 +
657 + /* DRVVBUS pins share with GPIOA */
658 + mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0014);
659 + reg = __raw_readl(mem);
660 + reg |= 0x8;
661 + __raw_writel(reg, mem);
662 +
663 + /* Enable OTG */
664 + mem = (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0808);
665 + reg = __raw_readl(mem);
666 + reg &= ~(1 << 10);
667 + __raw_writel(reg, mem);
668 +
669 + platform_device_register(&cns3xxx_usb_otg_device);
670 + }
671 +
672 + if (laguna_info.config_bitmap & (USB1_LOAD)) {
673 + platform_device_register(&cns3xxx_usb_ehci_device);
674 + platform_device_register(&cns3xxx_usb_ohci_device);
675 + }
676 +
677 + if (laguna_info.config_bitmap & (SD_LOAD))
678 + cns3xxx_sdhci_init();
679 +
680 + if (laguna_info.config_bitmap & (UART0_LOAD))
681 + laguna_uart.num_resources = 1;
682 + if (laguna_info.config_bitmap & (UART1_LOAD))
683 + laguna_uart.num_resources = 2;
684 + if (laguna_info.config_bitmap & (UART2_LOAD))
685 + laguna_uart.num_resources = 3;
686 + platform_device_register(&laguna_uart);
687 +
688 + if (laguna_info.config2_bitmap & (NOR_FLASH_LOAD)) {
689 + switch (laguna_info.nor_flash_size) {
690 + case 1:
691 + laguna_nor_partitions[3].size = SZ_8M - SZ_256K - SZ_128K - SZ_2M;
692 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_8M - 1;
693 + break;
694 + case 2:
695 + laguna_nor_partitions[3].size = SZ_16M - SZ_256K - SZ_128K - SZ_2M;
696 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_16M - 1;
697 + break;
698 + case 3:
699 + laguna_nor_partitions[3].size = SZ_32M - SZ_256K - SZ_128K - SZ_2M;
700 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_32M - 1;
701 + break;
702 + case 4:
703 + laguna_nor_partitions[3].size = SZ_64M - SZ_256K - SZ_128K - SZ_2M;
704 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_64M - 1;
705 + break;
706 + case 5:
707 + laguna_nor_partitions[3].size = SZ_128M - SZ_256K - SZ_128K - SZ_2M;
708 + laguna_nor_res.end = CNS3XXX_FLASH_BASE + SZ_128M - 1;
709 + break;
710 + }
711 + platform_device_register(&laguna_nor_pdev);
712 + }
713 +
714 + if (laguna_info.config2_bitmap & (SPI_FLASH_LOAD)) {
715 + switch (laguna_info.spi_flash_size) {
716 + case 1:
717 + laguna_spi_partitions[3].size = SZ_4M - SZ_2M;
718 + break;
719 + case 2:
720 + laguna_spi_partitions[3].size = SZ_8M - SZ_2M;
721 + break;
722 + case 3:
723 + laguna_spi_partitions[3].size = SZ_16M - SZ_2M;
724 + break;
725 + case 4:
726 + laguna_spi_partitions[3].size = SZ_32M - SZ_2M;
727 + break;
728 + case 5:
729 + laguna_spi_partitions[3].size = SZ_64M - SZ_2M;
730 + break;
731 + }
732 + spi_register_board_info(laguna_spi_devices, ARRAY_SIZE(laguna_spi_devices));
733 + }
734 +
735 + if ((laguna_info.config_bitmap & SPI0_LOAD) ||
736 + (laguna_info.config_bitmap & SPI1_LOAD))
737 + platform_device_register(&laguna_spi_controller);
738 +
739 + /*
740 + * Do any model specific setup not known by the bitmap by matching
741 + * the first 6 characters of the model name
742 + */
743 +
744 + if (strncmp(laguna_info.model, "GW2388", 6) == 0) {
745 + laguna_gpio_leds_data.num_leds = 2;
746 + } else if (strncmp(laguna_info.model, "GW2380", 6) == 0) {
747 + laguna_gpio_leds[0].gpio = 107;
748 + laguna_gpio_leds[1].gpio = 106;
749 + laguna_gpio_leds_data.num_leds = 2;
750 + }
751 + platform_device_register(&laguna_gpio_leds_device);
752 + } else {
753 + // Do some defaults here, not sure what yet
754 + }
755 + return 0;
756 +}
757 +
758 +late_initcall(laguna_model_setup);
759 +
760 +MACHINE_START(GW2388, "Gateworks Corporation Laguna Platform")
761 + .atag_offset = 0x100,
762 + .map_io = laguna_map_io,
763 + .init_irq = cns3xxx_init_irq,
764 + .timer = &cns3xxx_timer,
765 + .handle_irq = gic_handle_irq,
766 + .init_machine = laguna_init,
767 + .restart = cns3xxx_restart,
768 +MACHINE_END
769 --- a/arch/arm/mach-cns3xxx/Kconfig
770 +++ b/arch/arm/mach-cns3xxx/Kconfig
771 @@ -11,4 +11,14 @@ config MACH_CNS3420VB
772 This is a platform with an on-board ARM11 MPCore and has support
773 for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc.
774
775 +config MACH_GW2388
776 + bool "Support for Gateworks Laguna Platform"
777 + select HAVE_ARM_SCU if SMP
778 + select MIGHT_HAVE_PCI
779 + help
780 + Include support for the Gateworks Laguna Platform
781 +
782 + This is a platform with an on-board ARM11 MPCore and has support
783 + for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, I2C, GIG, etc.
784 +
785 endmenu
786 --- a/arch/arm/Kconfig
787 +++ b/arch/arm/Kconfig
788 @@ -366,6 +366,7 @@ config ARCH_CLPS711X
789 config ARCH_CNS3XXX
790 bool "Cavium Networks CNS3XXX family"
791 select CPU_V6K
792 + select ARCH_WANT_OPTIONAL_GPIOLIB
793 select GENERIC_CLOCKEVENTS
794 select ARM_GIC
795 select CLKDEV_LOOKUP
796 --- /dev/null
797 +++ b/arch/arm/mach-cns3xxx/include/mach/gpio.h
798 @@ -0,0 +1,98 @@
799 +/*
800 + * arch/arm/mach-cns3xxx/include/mach/gpio.h
801 + *
802 + * CNS3xxx GPIO wrappers for arch-neutral GPIO calls
803 + *
804 + * Copyright 2011 Gateworks Corporation
805 + * Chris Lang <clang@gateworks.com>
806 + *
807 + * Based on IXP implementation by Milan Svoboda <msvoboda@ra.rockwell.com>
808 + * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
809 + *
810 + * This program is free software; you can redistribute it and/or modify
811 + * it under the terms of the GNU General Public License as published by
812 + * the Free Software Foundation; either version 2 of the License, or
813 + * (at your option) any later version.
814 + *
815 + * This program is distributed in the hope that it will be useful,
816 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
817 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
818 + * GNU General Public License for more details.
819 + *
820 + * You should have received a copy of the GNU General Public License
821 + * along with this program; if not, write to the Free Software
822 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
823 + *
824 + */
825 +
826 +#ifndef __ASM_ARCH_CNS3XXX_GPIO_H
827 +#define __ASM_ARCH_CNS3XXX_GPIO_H
828 +
829 +#include <linux/kernel.h>
830 +#include <linux/io.h>
831 +#include <mach/platform.h>
832 +#include <asm-generic/gpio.h> /* cansleep wrappers */
833 +
834 +#define NR_BUILTIN_GPIO 64
835 +
836 +#define CNS3XXX_GPIO_IN 0x0
837 +#define CNS3XXX_GPIO_OUT 0x1
838 +
839 +#define CNS3XXX_GPIO_LO 0
840 +#define CNS3XXX_GPIO_HI 1
841 +
842 +#define CNS3XXX_GPIO_OUTPUT 0x00
843 +#define CNS3XXX_GPIO_INPUT 0x04
844 +#define CNS3XXX_GPIO_DIR 0x08
845 +#define CNS3XXX_GPIO_SET 0x10
846 +#define CNS3XXX_GPIO_CLEAR 0x14
847 +
848 +static inline void gpio_line_get(u8 line, int *value)
849 +{
850 + if (line < 32)
851 + *value = ((__raw_readl(CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> line) & 0x1);
852 + else
853 + *value = ((__raw_readl(CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_INPUT) >> (line - 32)) & 0x1);
854 +}
855 +
856 +static inline void gpio_line_set(u8 line, int value)
857 +{
858 + if (line < 32) {
859 + if (value)
860 + __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_SET);
861 + else
862 + __raw_writel((1 << line), CNS3XXX_GPIOA_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
863 + } else {
864 + if (value)
865 + __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_SET);
866 + else
867 + __raw_writel((1 << line), CNS3XXX_GPIOB_BASE_VIRT + CNS3XXX_GPIO_CLEAR);
868 + }
869 +}
870 +
871 +static inline int gpio_get_value(unsigned gpio)
872 +{
873 + if (gpio < NR_BUILTIN_GPIO)
874 + {
875 + int value;
876 + gpio_line_get(gpio, &value);
877 + return value;
878 + }
879 + else
880 + return __gpio_get_value(gpio);
881 +}
882 +
883 +static inline void gpio_set_value(unsigned gpio, int value)
884 +{
885 + if (gpio < NR_BUILTIN_GPIO)
886 + gpio_line_set(gpio, value);
887 + else
888 + __gpio_set_value(gpio, value);
889 +}
890 +
891 +#define gpio_cansleep __gpio_cansleep
892 +
893 +extern int gpio_to_irq(int gpio);
894 +extern int irq_to_gpio(int gpio);
895 +
896 +#endif
897 --- a/arch/arm/mach-cns3xxx/Makefile
898 +++ b/arch/arm/mach-cns3xxx/Makefile
899 @@ -1,6 +1,7 @@
900 obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
901 obj-$(CONFIG_PCI) += pcie.o
902 obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
903 +obj-$(CONFIG_MACH_GW2388) += laguna.o
904 obj-$(CONFIG_SMP) += platsmp.o headsmp.o
905 obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
906 obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o