target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/devices.c

   1 /*
   2  * arch/m68k/coldfire/m547x/devices.c
   3  *
   4  * Coldfire M547x/M548x Platform Device Configuration
   5  *
   6  * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * Kurt Mahan <kmahan@freescale.com>
   9  */
  10 #include <linux/module.h>
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/fsl_devices.h>
  15 #include <linux/spi/spi.h>
  16 #include <linux/i2c.h>
  17
  18 #include <asm/coldfire.h>
  19 #include <asm/mcfsim.h>
  20
  21 #ifdef CONFIG_SPI
  22
  23 #include <asm/mcfqspi.h>
  24 /*
  25  *
  26  * DSPI
  27  *
  28  */
  29
  30 /* number of supported SPI selects */
  31 #define SPI_NUM_CHIPSELECTS     8
  32
  33 void coldfire_spi_cs_control(u8 cs, u8 command)
  34 {
  35         /* nothing special required */
  36 }
  37
  38 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  39 static struct coldfire_spi_chip spidev_chip_info = {
  40         .bits_per_word = 8,
  41 };
  42 #endif
  43
  44 static struct spi_board_info spi_board_info[] = {
  45 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
  46         {
  47                 .modalias = "spidev",
  48                 .max_speed_hz = 16000000,       /* max clk (SCK) speed in HZ */
  49                 .bus_num = 1,
  50                 .chip_select = 0,               /* CS0 */
  51                 .controller_data = &spidev_chip_info,
  52         }
  53 #endif
  54 };
  55
  56 static int spi_irq_list[] = {
  57         /* IRQ,              ICR Offset,        ICR Val,Mask */
  58         64 + ISC_DSPI_OVRFW, ISC_DSPI_OVRFW,    0x18,   0,
  59         64 + ISC_DSPI_RFOF,  ISC_DSPI_RFOF,     0x18,   0,
  60         64 + ISC_DSPI_RFDF,  ISC_DSPI_RFDF,     0x18,   0,
  61         64 + ISC_DSPI_TFUF,  ISC_DSPI_TFUF,     0x18,   0,
  62         64 + ISC_DSPI_TCF,   ISC_DSPI_TCF,      0x18,   0,
  63         64 + ISC_DSPI_TFFF,  ISC_DSPI_TFFF,     0x18,   0,
  64         64 + ISC_DSPI_EOQF,  ISC_DSPI_EOQF,     0x18,   0,
  65         0,0,0,0,
  66 };
  67
  68 static struct coldfire_spi_master coldfire_master_info = {
  69         .bus_num = 1,
  70         .num_chipselect = SPI_NUM_CHIPSELECTS,
  71         .irq_list = spi_irq_list,
  72         .irq_source = 0,        /* not used */
  73         .irq_vector = 0,        /* not used */
  74         .irq_mask = 0,          /* not used */
  75         .irq_lp = 0,            /* not used */
  76         .par_val = 0,           /* not used */
  77         .cs_control = coldfire_spi_cs_control,
  78 };
  79
  80 static struct resource coldfire_spi_resources[] = {
  81         [0] = {
  82                 .name = "spi-par",
  83                 .start = MCF_MBAR + 0x00000a50, /* PAR_DSPI */
  84                 .end = MCF_MBAR + 0x00000a50,   /* PAR_DSPI */
  85                 .flags = IORESOURCE_MEM
  86         },
  87
  88         [1] = {
  89                 .name = "spi-module",
  90                 .start = MCF_MBAR + 0x00008a00, /* DSPI MCR Base */
  91                 .end = MCF_MBAR + 0x00008ab8,   /* DSPI mem map end */
  92                 .flags = IORESOURCE_MEM
  93         },
  94
  95         [2] = {
  96                 .name = "spi-int-level",
  97                 .start = MCF_MBAR + 0x740,               /* ICR start */
  98                 .end = MCF_MBAR + 0x740 + ISC_DSPI_EOQF, /* ICR end */
  99                 .flags = IORESOURCE_MEM
 100         },
 101
 102         [3] = {
 103                 .name = "spi-int-mask",
 104                 .start = MCF_MBAR + 0x70c,      /* IMRL */
 105                 .end = MCF_MBAR + 0x70c,        /* IMRL */
 106                 .flags = IORESOURCE_MEM
 107         }
 108 };
 109
 110 static struct platform_device coldfire_spi = {
 111         .name = "spi_coldfire",
 112         .id = -1,
 113         .resource = coldfire_spi_resources,
 114         .num_resources = ARRAY_SIZE(coldfire_spi_resources),
 115         .dev = {
 116                 .platform_data = &coldfire_master_info,
 117         }
 118 };
 119
 120 /**
 121  * m547x_8x_spi_init - Initialize SPI
 122  */
 123 static int __init m547x_8x_spi_init(void)
 124 {
 125         int retval;
 126
 127         /* initialize the DSPI PAR */
 128         MCF_GPIO_PAR_DSPI = (MCF_GPIO_PAR_DSPI_PAR_CS5 |
 129                              MCF_GPIO_PAR_DSPI_PAR_CS3_DSPICS |
 130                              MCF_GPIO_PAR_DSPI_PAR_CS2_DSPICS |
 131                              MCF_GPIO_PAR_DSPI_PAR_CS0_DSPICS |
 132                              MCF_GPIO_PAR_DSPI_PAR_SCK_SCK |
 133                              MCF_GPIO_PAR_DSPI_PAR_SIN_SIN |
 134                              MCF_GPIO_PAR_DSPI_PAR_SOUT_SOUT);
 135
 136         /* register device */
 137         retval = platform_device_register(&coldfire_spi);
 138         if (retval < 0) {
 139                 goto out;
 140         }
 141
 142         /* register board info */
 143         if (ARRAY_SIZE(spi_board_info))
 144                 retval = spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
 145
 146 out:
 147         return retval;
 148 }
 149 #endif
 150
 151 #ifdef CONFIG_I2C_BOARDINFO
 152 static struct i2c_board_info mcf_i2c_devices[] = {
 153         {
 154                 I2C_BOARD_INFO("rv5c387a", 0x32),
 155         },
 156 };
 157 #endif
 158
 159 /**
 160  * m547x_8x_init_devices - Initialize M547X_8X devices
 161  *
 162  * Returns 0 on success.
 163  */
 164 static int __init m547x_8x_init_devices(void)
 165 {
 166 #ifdef CONFIG_SPI
 167         m547x_8x_spi_init();
 168 #endif
 169 #ifdef CONFIG_I2C_BOARDINFO
 170         i2c_register_board_info(0, mcf_i2c_devices,
 171                                 ARRAY_SIZE(mcf_i2c_devices));
 172 #endif
 173
 174         return 0;
 175 }
 176 arch_initcall(m547x_8x_init_devices);