target/linux/etrax-2.6/image/e100boot/src/cbl/src/e100boot.h

   1 /* $Id: e100boot.h,v 1.9 2003/12/16 09:04:07 magnusmn Exp $ */
   2
   3 #include "compiler.h"
   4
   5 #define DMA_DESCR__out_priority__BITNR  5
   6 #define DMA_DESCR__out_priority__WIDTH  1
   7 #define DMA_DESCR__out_priority__normal 0
   8 #define DMA_DESCR__out_priority__high   1
   9
  10 #define DMA_DESCR__ecp_cmd__BITNR  4
  11 #define DMA_DESCR__ecp_cmd__WIDTH  1
  12 #define DMA_DESCR__ecp_cmd__normal 0
  13 #define DMA_DESCR__ecp_cmd__high   1
  14
  15 #define DMA_DESCR__tx_err__BITNR 4
  16 #define DMA_DESCR__tx_err__WIDTH 1
  17 #define DMA_DESCR__tx_err__enable 1
  18 #define DMA_DESCR__tx_err__disable 0
  19
  20 #define DMA_DESCR__intr__BITNR  3
  21 #define DMA_DESCR__intr__WIDTH  1
  22 #define DMA_DESCR__intr__enable 1
  23 #define DMA_DESCR__intr__disable 0
  24
  25 #define DMA_DESCR__wait__BITNR 2
  26 #define DMA_DESCR__wait__WIDTH 1
  27 #define DMA_DESCR__wait__enable 1
  28 #define DMA_DESCR__wait__disable 0
  29
  30 #define DMA_DESCR__eop__BITNR 1
  31 #define DMA_DESCR__eop__WIDTH 1
  32 #define DMA_DESCR__eop__enable 1
  33 #define DMA_DESCR__eop__disable 0
  34
  35 #define DMA_DESCR__eol__BITNR 0
  36 #define DMA_DESCR__eol__WIDTH 1
  37 #define DMA_DESCR__eol__enable 1
  38 #define DMA_DESCR__eol__disable 0
  39
  40 #define DMA_DESCR__sw_len__BITNR 0
  41 #define DMA_DESCR__sw_len__WIDTH 16
  42
  43 #define DMA_DESCR__next__BITNR 0
  44 #define DMA_DESCR__next__WIDTH 32
  45
  46 #define DMA_DESCR__buf__BITNR 0
  47 #define DMA_DESCR__buf__WIDTH 32
  48
  49 #define DMA_DESCR__fifo_len__BITNR 8
  50 #define DMA_DESCR__fifo_len__WIDTH 7
  51
  52 #define DMA_DESCR__crc_err__BITNR 7
  53 #define DMA_DESCR__crc_err__WIDTH 1
  54 #define DMA_DESCR__crc_err__enable 1
  55 #define DMA_DESCR__crc_err__disable 0
  56
  57 #define DMA_DESCR__align_err__BITNR 6
  58 #define DMA_DESCR__align_err__WIDTH 1
  59 #define DMA_DESCR__align_err__enable 1
  60 #define DMA_DESCR__align_err__disable 0
  61
  62 #define DMA_DESCR__in_priority__BITNR 5
  63 #define DMA_DESCR__in_priority__WIDTH 1
  64 #define DMA_DESCR__in_priority__high 1
  65 #define DMA_DESCR__in_priority__normal 0
  66
  67 #define DMA_DESCR__stop__BITNR 4
  68 #define DMA_DESCR__stop__WIDTH 1
  69
  70 #define DMA_DESCR__rd_eop__BITNR 1
  71 #define DMA_DESCR__rd_eop__WIDTH 1
  72
  73 #define DMA_DESCR__hw_len__BITNR 0
  74 #define DMA_DESCR__hw_len__WIDTH 16
  75
  76 #define SET_ETHER_ADDR(a0_0,a0_1,a0_2,a0_3,a0_4,a0_5,a1_0,a1_1,a1_2,a1_3,a1_4,a1_5) \
  77   *R_NETWORK_SA_0 = a0_0 | (a0_1 << 8) | (a0_2 << 16) | (a0_3 << 24); \
  78   *R_NETWORK_SA_1 = a0_4 | (a0_5 << 8) | (a1_0 << 16) | (a1_1 << 24); \
  79   *R_NETWORK_SA_2 = a1_2 | (a1_3 << 8) | (a1_4 << 16) | (a1_5 << 24);
  80
  81 #define DWORD_ALIGN(x) ((x) & 0xfffffffc)
  82
  83 #define CRC_LEN 4
  84
  85 #define TRUE  1
  86 #define FALSE 0
  87
  88 #define NL 1
  89 #define NO_NL 0
  90
  91 #define SERIAL   0
  92 #define NETWORK  1
  93 #define PARALLEL 2
  94
  95 #define STRING      0
  96 #define INT         1
  97 #define ACK         2
  98 #define BOOT_PACKET 3
  99 #define BOOT_CMDS   4
 100 #define NET_INT     5
 101 #define NET_INT_NL  6
 102
 103 #define JUMP           1
 104 #define MEM_TEST       2
 105 #define PACKET_INFO    3
 106 #define SET_REGISTER   4
 107 #define GET_REGISTER   5
 108 #define MEM_DUMP       6
 109 #define MEM_CLEAR      7
 110 #define MEM_VERIFY     8
 111 #define FLASH          9
 112 #define PAUSE_LOOP     10
 113 #define LOOP           11
 114 #define BAUDRATE       12
 115
 116 #define ERR_FLASH_OK        0
 117 #define ERR_FLASH_NONE      1
 118 #define ERR_FLASH_TOO_SMALL 2
 119 #define ERR_FLASH_VERIFY    3
 120 #define ERR_FLASH_ERASE     4
 121
 122 #define TIMEOUT_LIMIT ( ((6250 * 1000) / 0xffff) / 2)
 123
 124 #define TX_CTRL_EOP \
 125 (IO_STATE(DMA_DESCR, intr, disable) |\
 126  IO_STATE(DMA_DESCR, wait, enable)  |\
 127  IO_STATE(DMA_DESCR, eop,  enable)  |\
 128  IO_STATE(DMA_DESCR, eol,  enable))
 129
 130 #define TX_CTRL \
 131      (IO_STATE(DMA_DESCR, intr, disable) |\
 132       IO_STATE(DMA_DESCR, wait, disable) |\
 133       IO_STATE(DMA_DESCR, eop,  disable) |\
 134       IO_STATE(DMA_DESCR, eol,  disable))
 135
 136 #define LOAD_ADDRESS 0x38001000
 137 #define SIZEOF_BOOT_LEVEL_1 2048
 138
 139 /* This is where the commands are transfered to. */
 140 #define IO_BUF_START    0x38001f00
 141 #define IO_BUF_END      0x380020f0 /* bootcode start + cache size */
 142
 143 /* This should only be used in the cbl, but if we compile the sbl for
 144  * elinux then __CRIS__ will be defined, and these are already defined
 145  * in uC-libc. Check that __linux__ is not defined as well!
 146  */
 147
 148 #if defined(__CRIS__) && !defined(__linux__)
 149 #define NULL ((void*)0)
 150
 151 static inline udword
 152 htonl(udword x)
 153 {
 154   __asm__ ("swapwb %0" : "=r" (x) : "0" (x));
 155
 156   return(x);
 157 }
 158 #ifndef ntohl
 159 #define ntohl(x) htonl(x)
 160 #endif
 161
 162 static inline uword
 163 htons(uword x)
 164 {
 165   __asm__ ("swapb %0" : "=r" (x) : "0" (x));
 166
 167   return(x);
 168 }
 169 #ifndef ntohs
 170 #define ntohs(x) htons(x)
 171 #endif
 172 #endif
 173
 174 /*#define ntohs(x) \*/
 175 /*((unsigned short)((((unsigned short)(x) & 0x00ffU) << 8) | \*/
 176 /*                   (((unsigned short)(x) & 0xff00U) >>  8)))*/
 177 /*     */
 178
 179 /*#define ntohl(x) \*/
 180 /*((unsigned long int)((((unsigned long int)(x) & 0x000000ffU) << 24) | \*/
 181 /*                   (((unsigned long int)(x) & 0x0000ff00U) <<  8) | \*/
 182 /*                   (((unsigned long int)(x) & 0x00ff0000U) >>  8) | \*/
 183 /*                   (((unsigned long int)(x) & 0xff000000U) >> 24)))*/
 184
 185 struct packet_header_T  /* Size = 38 */
 186 {
 187   byte      dest[6];
 188   byte      src[6];
 189   uword     length;
 190   udword    snap1;
 191   udword    snap2;
 192   udword    tag;
 193   udword    seq;
 194   udword    type;
 195   udword    id;
 196 } __attribute__ ((packed));
 197
 198 typedef struct dma_descr_T {
 199   uword  sw_len;                /* 0-1 */
 200   uword  ctrl;                  /* 2-3 */
 201   udword next;                  /* 4-7 */
 202   udword buf;                   /* 8-11 */
 203   uword  hw_len;                /* 12-13 */
 204   uword  status;                /* 14-15 */
 205 } dma_descr_T;
 206
 207 typedef struct packet_info_T {
 208   udword addr;
 209   udword size;
 210 } packet_info_T;
 211
 212 typedef struct set_register_T {
 213   udword addr;
 214   udword val;
 215 } set_register_T;
 216
 217 typedef struct get_register_T {
 218   udword addr;
 219 } get_register_T;
 220
 221 typedef struct pause_loop_T {
 222   udword pause;
 223 } pause_loop_T;
 224
 225 typedef struct mem_verify_T {
 226   udword addr;
 227   udword val;
 228 } mem_verify_T;
 229
 230 typedef struct mem_test_T {
 231   udword from;
 232   udword to;
 233 } mem_test_T;
 234
 235 typedef struct mem_dump_T {
 236   udword from_addr;
 237   udword to_addr;
 238 } mem_dump_T;
 239
 240 typedef struct mem_clear_T {
 241   udword from_addr;
 242   udword to_addr;
 243 } mem_clear_T;
 244
 245 typedef struct flash_T {
 246   unsigned char *source;
 247   udword offset;
 248   udword size;
 249 } flash_T;
 250
 251 typedef struct jump_T {
 252   udword addr;
 253 } jump_T;
 254
 255 typedef struct bne_T {
 256   udword addr;
 257   udword target;
 258 } bne_T;
 259
 260 typedef struct br_T {
 261   udword baudrate;
 262 } br_T;
 263
 264 typedef struct command_T {
 265   udword type;
 266   union {
 267     packet_info_T  packet_info;
 268     set_register_T set_register;
 269     get_register_T get_register;
 270     pause_loop_T   pause_loop;
 271     mem_verify_T   mem_verify;
 272     mem_test_T     mem_test;
 273     mem_dump_T     mem_dump;
 274     mem_clear_T    mem_clear;
 275     flash_T        flash;
 276     jump_T         jump;
 277     bne_T          bne;
 278     br_T           br;
 279   } args;
 280 } command_T;
 281
 282 #define NETWORK_HEADER_LENGTH sizeof(struct packet_header_T)
 283
 284 void crt1(void);
 285 void start(void);
 286 void level2_boot(void);
 287 int  read_data(void);
 288 int  handle_network_read(void);
 289 int  flash_write(const unsigned char *source, unsigned int offset, unsigned int size);
 290
 291 void init_interface(void);
 292 int handle_read(void);
 293 void send_ack(void);
 294 void send_string(char *str);
 295 void send_hex(udword v, byte nl);
 296
 297 extern char e100boot_version[];
 298
 299 extern volatile udword bytes_to_read;
 300 extern volatile udword target_address;
 301
 302 extern udword  nbr_read;
 303 extern byte    interface;
 304 extern byte    set_dest;
 305 extern udword  last_timeout;
 306 extern byte   *io_buf_next;
 307 extern byte   *io_buf_cur;
 308
 309 extern struct packet_header_T tx_header;
 310 extern dma_descr_T tx_descr;
 311 extern dma_descr_T tx_descr2;
 312
 313 extern struct packet_header_T rx_header;
 314 extern dma_descr_T rx_descr;
 315 extern dma_descr_T rx_descr2;
 316
 317 extern uword timeout_limit;
 318 extern udword seq;
 319 extern byte serial_up;
 320
 321 enum {                    /* Available in:  */
 322   d_eol      = (1 << 0),  /* flags          */
 323   d_eop      = (1 << 1),  /* flags & status */
 324   d_wait     = (1 << 2),  /* flags          */
 325   d_int      = (1 << 3),  /* flags          */
 326   d_txerr    = (1 << 4),  /* flags          */
 327   d_stop     = (1 << 4),  /*         status */
 328   d_ecp      = (1 << 4),  /* flags & status */
 329   d_pri      = (1 << 5),  /* flags & status */
 330   d_alignerr = (1 << 6),  /*         status */
 331   d_crcerr   = (1 << 7)   /*         status */
 332 };