[8.09] [kernel] generic-2.6: rename "files" directory to "files-2.6.24" to be consistent
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files-2.6.24 / drivers / net / phy / mvswitch.h
1 /*
2 * Marvell 88E6060 switch driver
3 * Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License v2 as published by the
7 * Free Software Foundation
8 */
9 #ifndef __MVSWITCH_H
10 #define __MVSWITCH_H
11
12 #define MV_HEADER_SIZE 2
13 #define MV_HEADER_PORTS_M 0x001f
14 #define MV_HEADER_PORTS_S 0
15 #define MV_HEADER_VLAN_M 0xf000
16 #define MV_HEADER_VLAN_S 12
17
18 #define MV_TRAILER_SIZE 4
19 #define MV_TRAILER_PORTS_M 0x1f
20 #define MV_TRAILER_PORTS_S 16
21 #define MV_TRAILER_FLAGS_S 24
22 #define MV_TRAILER_OVERRIDE 0x80
23
24
25 #define MV_PORTS 5
26 #define MV_WANPORT 4
27 #define MV_CPUPORT 5
28
29 #define MV_BASE 0x10
30
31 #define MV_PHYPORT_BASE (MV_BASE + 0x0)
32 #define MV_PHYPORT(_n) (MV_PHYPORT_BASE + (_n))
33 #define MV_SWITCHPORT_BASE (MV_BASE + 0x8)
34 #define MV_SWITCHPORT(_n) (MV_SWITCHPORT_BASE + (_n))
35 #define MV_SWITCHREGS (MV_BASE + 0xf)
36
37 enum {
38 MV_PHY_CONTROL = 0x00,
39 MV_PHY_STATUS = 0x01,
40 MV_PHY_IDENT0 = 0x02,
41 MV_PHY_IDENT1 = 0x03,
42 MV_PHY_ANEG = 0x04,
43 MV_PHY_LINK_ABILITY = 0x05,
44 MV_PHY_ANEG_EXPAND = 0x06,
45 MV_PHY_XMIT_NEXTP = 0x07,
46 MV_PHY_LINK_NEXTP = 0x08,
47 MV_PHY_CONTROL1 = 0x10,
48 MV_PHY_STATUS1 = 0x11,
49 MV_PHY_INTR_EN = 0x12,
50 MV_PHY_INTR_STATUS = 0x13,
51 MV_PHY_INTR_PORT = 0x14,
52 MV_PHY_RECV_COUNTER = 0x16,
53 MV_PHY_LED_PARALLEL = 0x16,
54 MV_PHY_LED_STREAM = 0x17,
55 MV_PHY_LED_CTRL = 0x18,
56 MV_PHY_LED_OVERRIDE = 0x19,
57 MV_PHY_VCT_CTRL = 0x1a,
58 MV_PHY_VCT_STATUS = 0x1b,
59 MV_PHY_CONTROL2 = 0x1e
60 };
61 #define MV_PHYREG(_type, _port) MV_PHYPORT(_port), MV_PHY_##_type
62
63 enum {
64 MV_PORT_STATUS = 0x00,
65 MV_PORT_IDENT = 0x03,
66 MV_PORT_CONTROL = 0x04,
67 MV_PORT_VLANMAP = 0x06,
68 MV_PORT_ASSOC = 0x0b,
69 MV_PORT_RXCOUNT = 0x10,
70 MV_PORT_TXCOUNT = 0x11,
71 };
72 #define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type
73
74 enum {
75 MV_PORTCTRL_BLOCK = (1 << 0),
76 MV_PORTCTRL_LEARN = (2 << 0),
77 MV_PORTCTRL_ENABLED = (3 << 0),
78 MV_PORTCTRL_VLANTUN = (1 << 7), /* Enforce VLANs on packets */
79 MV_PORTCTRL_RXTR = (1 << 8), /* Enable Marvell packet trailer for ingress */
80 MV_PORTCTRL_HEADER = (1 << 11), /* Enable Marvell packet header mode for port */
81 MV_PORTCTRL_TXTR = (1 << 14), /* Enable Marvell packet trailer for egress */
82 MV_PORTCTRL_FORCEFL = (1 << 15), /* force flow control */
83 };
84
85 #define MV_PORTVLAN_ID(_n) (((_n) & 0xf) << 12)
86 #define MV_PORTVLAN_PORTS(_n) ((_n) & 0x3f)
87
88 #define MV_PORTASSOC_PORTS(_n) ((_n) & 0x1f)
89 #define MV_PORTASSOC_MONITOR (1 << 15)
90
91 enum {
92 MV_SWITCH_MAC0 = 0x01,
93 MV_SWITCH_MAC1 = 0x02,
94 MV_SWITCH_MAC2 = 0x03,
95 MV_SWITCH_CTRL = 0x04,
96 MV_SWITCH_ATU_CTRL = 0x0a,
97 MV_SWITCH_ATU_OP = 0x0b,
98 MV_SWITCH_ATU_DATA = 0x0c,
99 MV_SWITCH_ATU_MAC0 = 0x0d,
100 MV_SWITCH_ATU_MAC1 = 0x0e,
101 MV_SWITCH_ATU_MAC2 = 0x0f,
102 };
103 #define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type
104
105 enum {
106 MV_SWITCHCTL_EEIE = (1 << 0), /* EEPROM interrupt enable */
107 MV_SWITCHCTL_PHYIE = (1 << 1), /* PHY interrupt enable */
108 MV_SWITCHCTL_ATUDONE= (1 << 2), /* ATU done interrupt enable */
109 MV_SWITCHCTL_ATUIE = (1 << 3), /* ATU interrupt enable */
110 MV_SWITCHCTL_CTRMODE= (1 << 8), /* statistics for rx and tx errors */
111 MV_SWITCHCTL_RELOAD = (1 << 9), /* reload registers from eeprom */
112 MV_SWITCHCTL_MSIZE = (1 << 10), /* increase maximum frame size */
113 MV_SWITCHCTL_DROP = (1 << 13), /* discard frames with excessive collisions */
114 };
115
116 enum {
117 #define MV_ATUCTL_AGETIME_MIN 16
118 #define MV_ATUCTL_AGETIME_MAX 4080
119 #define MV_ATUCTL_AGETIME(_n) ((((_n) / 16) & 0xff) << 4)
120 MV_ATUCTL_ATU_256 = (0 << 12),
121 MV_ATUCTL_ATU_512 = (1 << 12),
122 MV_ATUCTL_ATU_1K = (2 << 12),
123 MV_ATUCTL_ATUMASK = (3 << 12),
124 MV_ATUCTL_NO_LEARN = (1 << 14),
125 MV_ATUCTL_RESET = (1 << 15),
126 };
127
128 enum {
129 #define MV_ATUOP_DBNUM(_n) ((_n) & 0x0f)
130
131 MV_ATUOP_NOOP = (0 << 12),
132 MV_ATUOP_FLUSH_ALL = (1 << 12),
133 MV_ATUOP_FLUSH_U = (2 << 12),
134 MV_ATUOP_LOAD_DB = (3 << 12),
135 MV_ATUOP_GET_NEXT = (4 << 12),
136 MV_ATUOP_FLUSH_DB = (5 << 12),
137 MV_ATUOP_FLUSH_DB_UU= (6 << 12),
138
139 MV_ATUOP_INPROGRESS = (1 << 15),
140 };
141
142 #define MV_IDENT_MASK 0xfff0
143 #define MV_IDENT_VALUE 0x0600
144
145 #endif