kernel: add driver for the RTL8366RB switch
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/phy.h>
20 #include <linux/rtl8366rb.h>
21
22 #include "rtl8366_smi.h"
23
24 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
25 #include <linux/debugfs.h>
26 #endif
27
28 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
29 #define RTL8366S_DRIVER_VER "0.2.0"
30
31 #define RTL8366S_PHY_NO_MAX 4
32 #define RTL8366S_PHY_PAGE_MAX 7
33 #define RTL8366S_PHY_ADDR_MAX 31
34
35 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
36 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
37 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
38
39 #define RTL8366_RESET_CTRL_REG 0x0100
40 #define RTL8366_CHIP_CTRL_RESET_HW 1
41 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
42
43 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
44 #define RTL8366S_CHIP_VERSION_MASK 0xf
45 #define RTL8366S_CHIP_ID_REG 0x0509
46 #define RTL8366S_CHIP_ID_8366 0x5937
47
48 /* PHY registers control */
49 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
50 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
51
52 #define RTL8366S_PHY_CTRL_READ 1
53 #define RTL8366S_PHY_CTRL_WRITE 0
54
55 #define RTL8366S_PHY_REG_MASK 0x1f
56 #define RTL8366S_PHY_PAGE_OFFSET 5
57 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
58 #define RTL8366S_PHY_NO_OFFSET 9
59 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
60
61 /* LED control registers */
62 #define RTL8366_LED_BLINKRATE_REG 0x0430
63 #define RTL8366_LED_BLINKRATE_BIT 0
64 #define RTL8366_LED_BLINKRATE_MASK 0x0007
65
66 #define RTL8366_LED_CTRL_REG 0x0431
67 #define RTL8366_LED_0_1_CTRL_REG 0x0432
68 #define RTL8366_LED_2_3_CTRL_REG 0x0433
69
70 #define RTL8366S_MIB_COUNT 33
71 #define RTL8366S_GLOBAL_MIB_COUNT 1
72 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
73 #define RTL8366S_MIB_COUNTER_BASE 0x1000
74 #define RTL8366S_MIB_CTRL_REG 0x13F0
75 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
76 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
77 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
78
79 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
80 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
81 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
82
83
84 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
85 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
86 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
87 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
88 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
89
90
91 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
92 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
93
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
125
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_5 | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_5)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
147
148 struct rtl8366rb {
149 struct device *parent;
150 struct rtl8366_smi smi;
151 struct mii_bus *mii_bus;
152 int mii_irq[PHY_MAX_ADDR];
153 struct switch_dev dev;
154 char buf[4096];
155 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
156 struct dentry *debugfs_root;
157 #endif
158 };
159
160 struct rtl8366rb_vlanconfig {
161 u16 reserved2:1;
162 u16 priority:3;
163 u16 vid:12;
164 u16 untag:8;
165 u16 member:8;
166 u16 stag_mbr:8;
167 u16 stag_idx:3;
168 u16 reserved1:2;
169 u16 fid:3;
170 };
171
172 struct rtl8366rb_vlan4kentry {
173 u16 reserved1:4;
174 u16 vid:12;
175 u16 untag:8;
176 u16 member:8;
177 u16 reserved2:13;
178 u16 fid:3;
179 };
180
181
182 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
183 u16 gl_dbg_reg;
184 #endif
185
186 struct mib_counter {
187 unsigned offset;
188 unsigned length;
189 const char *name;
190 };
191
192 static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = {
193 { 0, 4, "IfInOctets " },
194 { 4, 4, "EtherStatsOctets " },
195 { 8, 2, "EtherStatsUnderSizePkts " },
196 { 10, 2, "EtherFregament " },
197 { 12, 2, "EtherStatsPkts64Octets " },
198 { 14, 2, "EtherStatsPkts65to127Octets " },
199 { 16, 2, "EtherStatsPkts128to255Octets " },
200 { 18, 2, "EtherStatsPkts256to511Octets " },
201 { 20, 2, "EtherStatsPkts512to1023Octets " },
202 { 22, 2, "EtherStatsPkts1024to1518Octets " },
203 { 24, 2, "EtherOversizeStats " },
204 { 26, 2, "EtherStatsJabbers " },
205 { 28, 2, "IfInUcastPkts " },
206 { 30, 2, "EtherStatsMulticastPkts " },
207 { 32, 2, "EtherStatsBroadcastPkts " },
208 { 34, 2, "EtherStatsDropEvents " },
209 { 36, 2, "Dot3StatsFCSErrors " },
210 { 38, 2, "Dot3StatsSymbolErrors " },
211 { 40, 2, "Dot3InPauseFrames " },
212 { 42, 2, "Dot3ControlInUnknownOpcodes " },
213 { 44, 2, "IfOutOctets " },
214 { 46, 2, "Dot3StatsSingleCollisionFrames " },
215 { 48, 2, "Dot3StatMultipleCollisionFrames " },
216 { 50, 2, "Dot3sDeferredTransmissions " },
217 { 52, 2, "Dot3StatsLateCollisions " },
218 { 54, 2, "EtherStatsCollisions " },
219 { 56, 2, "Dot3StatsExcessiveCollisions " },
220 { 58, 2, "Dot3OutPauseFrames " },
221 { 60, 2, "Dot1dBasePortDelayExceededDiscards" },
222 { 62, 2, "Dot1dTpPortInDiscards " },
223 { 64, 2, "IfOutUcastPkts " },
224 { 66, 2, "IfOutMulticastPkts " },
225 { 68, 2, "IfOutBroadcastPkts " },
226 };
227
228 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
229 {
230 return container_of(sw, struct rtl8366rb, dev);
231 }
232
233 static int rtl8366rb_reset_chip(struct rtl8366rb *rtl)
234 {
235 struct rtl8366_smi *smi = &rtl->smi;
236 int timeout = 10;
237 u32 data;
238
239 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
240 RTL8366_CHIP_CTRL_RESET_HW);
241 do {
242 msleep(1);
243 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
244 return -EIO;
245
246 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
247 break;
248 } while (--timeout);
249
250 if (!timeout) {
251 printk("Timeout waiting for the switch to reset\n");
252 return -EIO;
253 }
254
255 return 0;
256 }
257
258 static int rtl8366rb_read_phy_reg(struct rtl8366rb *rtl,
259 u32 phy_no, u32 page, u32 addr, u32 *data)
260 {
261 struct rtl8366_smi *smi = &rtl->smi;
262 u32 reg;
263 int ret;
264
265 if (phy_no > RTL8366S_PHY_NO_MAX)
266 return -EINVAL;
267
268 if (page > RTL8366S_PHY_PAGE_MAX)
269 return -EINVAL;
270
271 if (addr > RTL8366S_PHY_ADDR_MAX)
272 return -EINVAL;
273
274 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
275 RTL8366S_PHY_CTRL_READ);
276 if (ret)
277 return ret;
278
279 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
280 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
281 (addr & RTL8366S_PHY_REG_MASK);
282
283 ret = rtl8366_smi_write_reg(smi, reg, 0);
284 if (ret)
285 return ret;
286
287 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
288 if (ret)
289 return ret;
290
291 return 0;
292 }
293
294 static int rtl8366rb_write_phy_reg(struct rtl8366rb *rtl,
295 u32 phy_no, u32 page, u32 addr, u32 data)
296 {
297 struct rtl8366_smi *smi = &rtl->smi;
298 u32 reg;
299 int ret;
300
301 if (phy_no > RTL8366S_PHY_NO_MAX)
302 return -EINVAL;
303
304 if (page > RTL8366S_PHY_PAGE_MAX)
305 return -EINVAL;
306
307 if (addr > RTL8366S_PHY_ADDR_MAX)
308 return -EINVAL;
309
310 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
311 RTL8366S_PHY_CTRL_WRITE);
312 if (ret)
313 return ret;
314
315 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
316 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
317 (addr & RTL8366S_PHY_REG_MASK);
318
319 ret = rtl8366_smi_write_reg(smi, reg, data);
320 if (ret)
321 return ret;
322
323 return 0;
324 }
325
326 static int rtl8366_get_mib_counter(struct rtl8366rb *rtl, int counter,
327 int port, unsigned long long *val)
328 {
329 struct rtl8366_smi *smi = &rtl->smi;
330 int i;
331 int err;
332 u32 addr, data;
333 u64 mibvalue;
334
335 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
336 return -EINVAL;
337
338 addr = RTL8366S_MIB_COUNTER_BASE +
339 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
340 rtl8366rb_mib_counters[counter].offset;
341
342 /*
343 * Writing access counter address first
344 * then ASIC will prepare 64bits counter wait for being retrived
345 */
346 data = 0; /* writing data will be discard by ASIC */
347 err = rtl8366_smi_write_reg(smi, addr, data);
348 if (err)
349 return err;
350
351 /* read MIB control register */
352 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
353 if (err)
354 return err;
355
356 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
357 return -EBUSY;
358
359 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
360 return -EIO;
361
362 mibvalue = 0;
363 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
364 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
365 if (err)
366 return err;
367
368 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
369 }
370
371 *val = mibvalue;
372 return 0;
373 }
374
375 static int rtl8366rb_get_vlan_4k_entry(struct rtl8366rb *rtl, u32 vid,
376 struct rtl8366rb_vlan4kentry *vlan4k)
377 {
378 struct rtl8366_smi *smi = &rtl->smi;
379 int err;
380 u32 data;
381 u16 *tableaddr;
382
383 memset(vlan4k, '\0', sizeof(struct rtl8366rb_vlan4kentry));
384 vlan4k->vid = vid;
385
386 if (vid >= RTL8366_NUM_VIDS)
387 return -EINVAL;
388
389 tableaddr = (u16 *)vlan4k;
390
391 /* write VID */
392 data = *tableaddr;
393 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
394 if (err)
395 return err;
396
397 /* write table access control word */
398 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
399 RTL8366S_TABLE_VLAN_READ_CTRL);
400 if (err)
401 return err;
402
403 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
404 if (err)
405 return err;
406
407 *tableaddr = data;
408 tableaddr++;
409
410 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
411 &data);
412 if (err)
413 return err;
414
415 *tableaddr = data;
416 tableaddr++;
417
418 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2,
419 &data);
420 if (err)
421 return err;
422 *tableaddr = data;
423 vlan4k->vid = vid;
424
425 return 0;
426 }
427
428 static int rtl8366rb_set_vlan_4k_entry(struct rtl8366rb *rtl,
429 const struct rtl8366rb_vlan4kentry *vlan4k)
430 {
431 struct rtl8366_smi *smi = &rtl->smi;
432 int err;
433 u32 data;
434 u16 *tableaddr;
435
436 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
437 vlan4k->member > RTL8366_PORT_ALL ||
438 vlan4k->untag > RTL8366_PORT_ALL ||
439 vlan4k->fid > RTL8366S_FIDMAX)
440 return -EINVAL;
441
442 tableaddr = (u16 *)vlan4k;
443
444 data = *tableaddr;
445
446 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
447 if (err)
448 return err;
449
450 tableaddr++;
451
452 data = *tableaddr;
453
454 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
455 data);
456 if (err)
457 return err;
458
459 tableaddr++;
460
461 data = *tableaddr;
462
463 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2,
464 data);
465 if (err)
466 return err;
467
468 /* write table access control word */
469 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
470 RTL8366S_TABLE_VLAN_WRITE_CTRL);
471
472 return err;
473 }
474
475 static int rtl8366rb_get_vlan_member_config(struct rtl8366rb *rtl, u32 index,
476 struct rtl8366rb_vlanconfig *vlanmc)
477 {
478 struct rtl8366_smi *smi = &rtl->smi;
479 int err;
480 u32 addr;
481 u32 data;
482 u16 *tableaddr;
483
484 memset(vlanmc, '\0', sizeof(struct rtl8366rb_vlanconfig));
485
486 if (index >= RTL8366_NUM_VLANS)
487 return -EINVAL;
488
489 tableaddr = (u16 *)vlanmc;
490
491 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
492 err = rtl8366_smi_read_reg(smi, addr, &data);
493 if (err)
494 return err;
495
496 *tableaddr = data;
497 tableaddr++;
498
499 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
500 err = rtl8366_smi_read_reg(smi, addr, &data);
501 if (err)
502 return err;
503
504 *tableaddr = data;
505 tableaddr++;
506
507 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
508 err = rtl8366_smi_read_reg(smi, addr, &data);
509 if (err)
510 return err;
511
512 *tableaddr = data;
513
514 return 0;
515 }
516
517 static int rtl8366rb_set_vlan_member_config(struct rtl8366rb *rtl, u32 index,
518 const struct rtl8366rb_vlanconfig
519 *vlanmc)
520 {
521 struct rtl8366_smi *smi = &rtl->smi;
522 int err;
523 u32 addr;
524 u32 data;
525 u16 *tableaddr;
526
527 if (index >= RTL8366_NUM_VLANS ||
528 vlanmc->vid >= RTL8366_NUM_VIDS ||
529 vlanmc->priority > RTL8366S_PRIORITYMAX ||
530 vlanmc->member > RTL8366_PORT_ALL ||
531 vlanmc->untag > RTL8366_PORT_ALL ||
532 vlanmc->fid > RTL8366S_FIDMAX)
533 return -EINVAL;
534
535 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
536
537 tableaddr = (u16 *)vlanmc;
538 data = *tableaddr;
539
540 err = rtl8366_smi_write_reg(smi, addr, data);
541 if (err)
542 return err;
543
544 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
545
546 tableaddr++;
547 data = *tableaddr;
548
549 err = rtl8366_smi_write_reg(smi, addr, data);
550 if (err)
551 return err;
552
553 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
554
555 tableaddr++;
556 data = *tableaddr;
557
558 err = rtl8366_smi_write_reg(smi, addr, data);
559 if (err)
560 return err;
561 return 0;
562 }
563
564 static int rtl8366rb_get_port_vlan_index(struct rtl8366rb *rtl, int port,
565 int *val)
566 {
567 struct rtl8366_smi *smi = &rtl->smi;
568 u32 data;
569 int err;
570
571 if (port >= RTL8366_NUM_PORTS)
572 return -EINVAL;
573
574 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
575 &data);
576 if (err)
577 return err;
578
579 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
580 RTL8366S_PORT_VLAN_CTRL_MASK;
581
582 return 0;
583
584 }
585
586 static int rtl8366rb_get_vlan_port_pvid(struct rtl8366rb *rtl, int port,
587 int *val)
588 {
589 struct rtl8366rb_vlanconfig vlanmc;
590 int err;
591 int index;
592
593 err = rtl8366rb_get_port_vlan_index(rtl, port, &index);
594 if (err)
595 return err;
596
597 err = rtl8366rb_get_vlan_member_config(rtl, index, &vlanmc);
598 if (err)
599 return err;
600
601 *val = vlanmc.vid;
602 return 0;
603 }
604
605 static int rtl8366rb_set_port_vlan_index(struct rtl8366rb *rtl, int port,
606 int index)
607 {
608 struct rtl8366_smi *smi = &rtl->smi;
609 u32 data;
610 int err;
611
612 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
613 return -EINVAL;
614
615 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
616 &data);
617 if (err)
618 return err;
619
620 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
621 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
622 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
623 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
624
625 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
626 data);
627 return err;
628 }
629
630 static int rtl8366rb_set_vlan_port_pvid(struct rtl8366rb *rtl, int port, int val)
631 {
632 int i;
633 struct rtl8366rb_vlanconfig vlanmc;
634 struct rtl8366rb_vlan4kentry vlan4k;
635
636 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
637 return -EINVAL;
638
639 /* Updating the 4K entry; lookup it and change the port member set */
640 rtl8366rb_get_vlan_4k_entry(rtl, val, &vlan4k);
641 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
642 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
643 rtl8366rb_set_vlan_4k_entry(rtl, &vlan4k);
644
645 /*
646 * For the 16 entries more work needs to be done. First see if such
647 * VID is already there and change it
648 */
649 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
650 rtl8366rb_get_vlan_member_config(rtl, i, &vlanmc);
651
652 /* Try to find an existing vid and update port member set */
653 if (val == vlanmc.vid) {
654 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
655 rtl8366rb_set_vlan_member_config(rtl, i, &vlanmc);
656
657 /* Now update PVID register settings */
658 rtl8366rb_set_port_vlan_index(rtl, port, i);
659
660 return 0;
661 }
662 }
663
664 /*
665 * PVID could not be found from vlan table. Replace unused (one that
666 * has no member ports) with new one
667 */
668 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
669 rtl8366rb_get_vlan_member_config(rtl, i, &vlanmc);
670
671 /*
672 * See if this vlan member configuration is unused. It is
673 * unused if member set contains no ports or CPU port only
674 */
675 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
676 vlanmc.vid = val;
677 vlanmc.priority = 0;
678 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
679 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
680 vlanmc.fid = 0;
681
682 rtl8366rb_set_vlan_member_config(rtl, i, &vlanmc);
683
684 /* Now update PVID register settings */
685 rtl8366rb_set_port_vlan_index(rtl, port, i);
686
687 return 0;
688 }
689 }
690
691 dev_err(rtl->parent,
692 "All 16 vlan member configurations are in use\n");
693
694 return -EINVAL;
695 }
696
697
698 static int rtl8366rb_vlan_set_vlan(struct rtl8366rb *rtl, int enable)
699 {
700 struct rtl8366_smi *smi = &rtl->smi;
701 u32 data = 0;
702
703 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
704
705 if (enable)
706 data |= RTL8366_CHIP_CTRL_VLAN;
707 else
708 data &= ~RTL8366_CHIP_CTRL_VLAN;
709
710 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
711 }
712
713 static int rtl8366rb_vlan_set_4ktable(struct rtl8366rb *rtl, int enable)
714 {
715 struct rtl8366_smi *smi = &rtl->smi;
716 u32 data = 0;
717
718 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
719
720 if (enable)
721 data |= RTL8366_CHIP_CTRL_VLAN_4KTB;
722 else
723 data &= ~RTL8366_CHIP_CTRL_VLAN_4KTB;
724
725 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
726 }
727
728 static int rtl8366rb_reset_vlan(struct rtl8366rb *rtl)
729 {
730 struct rtl8366rb_vlan4kentry vlan4k;
731 struct rtl8366rb_vlanconfig vlanmc;
732 int err;
733 int i;
734
735 /* clear 16 VLAN member configuration */
736 vlanmc.vid = 0;
737 vlanmc.priority = 0;
738 vlanmc.member = 0;
739 vlanmc.untag = 0;
740 vlanmc.fid = 0;
741 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
742 err = rtl8366rb_set_vlan_member_config(rtl, i, &vlanmc);
743 if (err)
744 return err;
745 }
746
747 /* Set a default VLAN with vid 1 to 4K table for all ports */
748 vlan4k.vid = 1;
749 vlan4k.member = RTL8366_PORT_ALL;
750 vlan4k.untag = RTL8366_PORT_ALL;
751 vlan4k.fid = 0;
752 err = rtl8366rb_set_vlan_4k_entry(rtl, &vlan4k);
753 if (err)
754 return err;
755
756 /* Set all ports PVID to default VLAN */
757 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
758 err = rtl8366rb_set_vlan_port_pvid(rtl, i, 0);
759 if (err)
760 return err;
761 }
762
763 return 0;
764 }
765
766 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
767 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
768 {
769 file->private_data = inode->i_private;
770 return 0;
771 }
772
773 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
774 char __user *user_buf,
775 size_t count, loff_t *ppos)
776 {
777 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
778 int i, j, len = 0;
779 char *buf = rtl->buf;
780
781 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
782 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
783 " "
784 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
785 "Port 4\n");
786
787 for (i = 0; i < 33; ++i) {
788 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
789 i, rtl8366rb_mib_counters[i].name);
790 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
791 unsigned long long counter = 0;
792
793 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
794 len += snprintf(buf + len,
795 sizeof(rtl->buf) - len,
796 "[%llu]", counter);
797 else
798 len += snprintf(buf + len,
799 sizeof(rtl->buf) - len,
800 "[error]");
801
802 if (j != RTL8366_NUM_PORTS - 1) {
803 if (counter < 100000)
804 len += snprintf(buf + len,
805 sizeof(rtl->buf) - len,
806 "\t");
807
808 len += snprintf(buf + len,
809 sizeof(rtl->buf) - len,
810 "\t");
811 }
812 }
813 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
814 }
815
816 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
817
818 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
819 }
820
821 static ssize_t rtl8366rb_read_debugfs_vlan(struct file *file,
822 char __user *user_buf,
823 size_t count, loff_t *ppos)
824 {
825 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
826 int i, j, len = 0;
827 char *buf = rtl->buf;
828
829 len += snprintf(buf + len, sizeof(rtl->buf) - len,
830 "VLAN Member Config:\n");
831 len += snprintf(buf + len, sizeof(rtl->buf) - len,
832 "\t id \t vid \t prio \t member \t untag \t fid "
833 "\tports\n");
834
835 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
836 struct rtl8366rb_vlanconfig vlanmc;
837
838 rtl8366rb_get_vlan_member_config(rtl, i, &vlanmc);
839
840 len += snprintf(buf + len, sizeof(rtl->buf) - len,
841 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
842 "\t", i, vlanmc.vid, vlanmc.priority,
843 vlanmc.member, vlanmc.untag, vlanmc.fid);
844
845 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
846 int index = 0;
847 if (!rtl8366rb_get_port_vlan_index(rtl, j, &index)) {
848 if (index == i)
849 len += snprintf(buf + len,
850 sizeof(rtl->buf) - len,
851 "%d", j);
852 }
853 }
854 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
855 }
856
857 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
858 }
859
860 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
861 char __user *user_buf,
862 size_t count, loff_t *ppos)
863 {
864 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
865 struct rtl8366_smi *smi = &rtl->smi;
866 u32 t, reg = gl_dbg_reg;
867 int err, len = 0;
868 char *buf = rtl->buf;
869
870 memset(buf, '\0', sizeof(rtl->buf));
871
872 err = rtl8366_smi_read_reg(smi, reg, &t);
873 if (err) {
874 len += snprintf(buf, sizeof(rtl->buf),
875 "Read failed (reg: 0x%04x)\n", reg);
876 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
877 }
878
879 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
880 reg, t);
881
882 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
883 }
884
885 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
886 const char __user *user_buf,
887 size_t count, loff_t *ppos)
888 {
889 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
890 struct rtl8366_smi *smi = &rtl->smi;
891 unsigned long data;
892 u32 reg = gl_dbg_reg;
893 int err;
894 size_t len;
895 char *buf = rtl->buf;
896
897 len = min(count, sizeof(rtl->buf) - 1);
898 if (copy_from_user(buf, user_buf, len)) {
899 dev_err(rtl->parent, "copy from user failed\n");
900 return -EFAULT;
901 }
902
903 buf[len] = '\0';
904 if (len > 0 && buf[len - 1] == '\n')
905 buf[len - 1] = '\0';
906
907
908 if (strict_strtoul(buf, 16, &data)) {
909 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
910 } else {
911 err = rtl8366_smi_write_reg(smi, reg, data);
912 if (err) {
913 dev_err(rtl->parent,
914 "writing reg 0x%04x val 0x%04lx failed\n",
915 reg, data);
916 }
917 }
918
919 return count;
920 }
921
922 static const struct file_operations fops_rtl8366rb_regs = {
923 .read = rtl8366rb_read_debugfs_reg,
924 .write = rtl8366rb_write_debugfs_reg,
925 .open = rtl8366rb_debugfs_open,
926 .owner = THIS_MODULE
927 };
928
929 static const struct file_operations fops_rtl8366rb_vlan = {
930 .read = rtl8366rb_read_debugfs_vlan,
931 .open = rtl8366rb_debugfs_open,
932 .owner = THIS_MODULE
933 };
934
935 static const struct file_operations fops_rtl8366rb_mibs = {
936 .read = rtl8366rb_read_debugfs_mibs,
937 .open = rtl8366rb_debugfs_open,
938 .owner = THIS_MODULE
939 };
940
941 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
942 {
943 struct dentry *node;
944 struct dentry *root;
945
946 if (!rtl->debugfs_root)
947 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
948
949 if (!rtl->debugfs_root) {
950 dev_err(rtl->parent, "Unable to create debugfs dir\n");
951 return;
952 }
953 root = rtl->debugfs_root;
954
955 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
956 if (!node) {
957 dev_err(rtl->parent, "Creating debugfs file reg failed\n");
958 return;
959 }
960
961 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
962 &fops_rtl8366rb_regs);
963 if (!node) {
964 dev_err(rtl->parent, "Creating debugfs file val failed\n");
965 return;
966 }
967
968 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
969 &fops_rtl8366rb_vlan);
970 if (!node) {
971 dev_err(rtl->parent,
972 "Creating debugfs file vlan failed\n");
973 return;
974 }
975
976 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
977 &fops_rtl8366rb_mibs);
978 if (!node) {
979 dev_err(rtl->parent,
980 "Creating debugfs file mibs failed\n");
981 return;
982 }
983 }
984
985 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
986 {
987 if (rtl->debugfs_root) {
988 debugfs_remove_recursive(rtl->debugfs_root);
989 rtl->debugfs_root = NULL;
990 }
991 }
992
993 #else
994 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
995 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
996 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
997
998 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
999 const struct switch_attr *attr,
1000 struct switch_val *val)
1001 {
1002 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1003 struct rtl8366_smi *smi = &rtl->smi;
1004 u32 data = 0;
1005
1006 if (val->value.i == 1) {
1007 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1008 data |= (1 << 2);
1009 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1010 }
1011
1012 return 0;
1013 }
1014
1015 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
1016 const struct switch_attr *attr,
1017 struct switch_val *val)
1018 {
1019 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1020 struct rtl8366_smi *smi = &rtl->smi;
1021 u32 data;
1022
1023 if (attr->ofs == 1) {
1024 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1025
1026 if (data & RTL8366_CHIP_CTRL_VLAN)
1027 val->value.i = 1;
1028 else
1029 val->value.i = 0;
1030 } else if (attr->ofs == 2) {
1031 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1032
1033 if (data & RTL8366_CHIP_CTRL_VLAN_4KTB)
1034 val->value.i = 1;
1035 else
1036 val->value.i = 0;
1037 }
1038
1039 return 0;
1040 }
1041
1042 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
1043 const struct switch_attr *attr,
1044 struct switch_val *val)
1045 {
1046 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1047 struct rtl8366_smi *smi = &rtl->smi;
1048 u32 data;
1049
1050 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1051
1052 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1053
1054 return 0;
1055 }
1056
1057 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
1058 const struct switch_attr *attr,
1059 struct switch_val *val)
1060 {
1061 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1062 struct rtl8366_smi *smi = &rtl->smi;
1063 u32 data;
1064
1065 if (val->value.i >= 6)
1066 return -EINVAL;
1067
1068 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1069
1070 data &= ~RTL8366_LED_BLINKRATE_MASK;
1071 data |= val->value.i;
1072
1073 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1074
1075 return 0;
1076 }
1077
1078 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
1079 const struct switch_attr *attr,
1080 struct switch_val *val)
1081 {
1082 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1083
1084 if (attr->ofs == 1)
1085 return rtl8366rb_vlan_set_vlan(rtl, val->value.i);
1086 else
1087 return rtl8366rb_vlan_set_4ktable(rtl, val->value.i);
1088 }
1089
1090 static const char *rtl8366rb_speed_str(unsigned speed)
1091 {
1092 switch (speed) {
1093 case 0:
1094 return "10baseT";
1095 case 1:
1096 return "100baseT";
1097 case 2:
1098 return "1000baseT";
1099 }
1100
1101 return "unknown";
1102 }
1103
1104 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
1105 const struct switch_attr *attr,
1106 struct switch_val *val)
1107 {
1108 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1109 struct rtl8366_smi *smi = &rtl->smi;
1110 u32 len = 0, data = 0;
1111
1112 if (val->port_vlan >= RTL8366_NUM_PORTS)
1113 return -EINVAL;
1114
1115 memset(rtl->buf, '\0', sizeof(rtl->buf));
1116 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1117 (val->port_vlan / 2), &data);
1118
1119 if (val->port_vlan % 2)
1120 data = data >> 8;
1121
1122 len = snprintf(rtl->buf, sizeof(rtl->buf),
1123 "port:%d link:%s speed:%s %s-duplex %s%s%s",
1124 val->port_vlan,
1125 (data & RTL8366S_PORT_STATUS_LINK_MASK) ? "up" : "down",
1126 rtl8366rb_speed_str(data &
1127 RTL8366S_PORT_STATUS_SPEED_MASK),
1128 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1129 "full" : "half",
1130 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1131 "tx-pause ": "",
1132 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1133 "rx-pause " : "",
1134 (data & RTL8366S_PORT_STATUS_AN_MASK) ? "nway ": "");
1135
1136 val->value.s = rtl->buf;
1137 val->len = len;
1138
1139 return 0;
1140 }
1141
1142 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1143 const struct switch_attr *attr,
1144 struct switch_val *val)
1145 {
1146 int i;
1147 u32 len = 0;
1148 struct rtl8366rb_vlanconfig vlanmc;
1149 struct rtl8366rb_vlan4kentry vlan4k;
1150 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1151 char *buf = rtl->buf;
1152
1153 if (val->port_vlan >= RTL8366_NUM_VLANS)
1154 return -EINVAL;
1155
1156 memset(buf, '\0', sizeof(rtl->buf));
1157
1158 rtl8366rb_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1159 rtl8366rb_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1160
1161 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1162 val->port_vlan);
1163
1164 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1165 int index = 0;
1166 if (!rtl8366rb_get_port_vlan_index(rtl, i, &index) &&
1167 index == val->port_vlan)
1168 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1169 "%d", i);
1170 }
1171 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1172
1173 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1174 "\t\t vid \t prio \t member \t untag \t fid\n");
1175 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1176 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1177 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1178 vlanmc.vid, vlanmc.priority, vlanmc.member,
1179 vlanmc.untag, vlanmc.fid);
1180 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1181 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1182 "%d \t \t 0x%04x \t 0x%04x \t %d",
1183 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1184
1185 val->value.s = buf;
1186 val->len = len;
1187
1188 return 0;
1189 }
1190
1191 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1192 const struct switch_attr *attr,
1193 struct switch_val *val)
1194 {
1195 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1196 struct rtl8366_smi *smi = &rtl->smi;
1197 u32 data = 0;
1198
1199 if (val->port_vlan >= RTL8366_NUM_PORTS)
1200 return -EINVAL;
1201
1202 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1203 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1204 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1205 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1206 } else {
1207 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1208 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1209 (val->value.i << (val->port_vlan * 4));
1210 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1211 }
1212
1213 return 0;
1214 }
1215
1216 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1217 const struct switch_attr *attr,
1218 struct switch_val *val)
1219 {
1220 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1221 struct rtl8366_smi *smi = &rtl->smi;
1222 u32 data = 0;
1223
1224 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1225 return -EINVAL;
1226
1227 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1228 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1229
1230 return 0;
1231 }
1232
1233 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1234 const struct switch_attr *attr,
1235 struct switch_val *val)
1236 {
1237 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1238 struct rtl8366_smi *smi = &rtl->smi;
1239 u32 data = 0;
1240
1241 if (val->port_vlan >= RTL8366_NUM_PORTS)
1242 return -EINVAL;
1243
1244 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1245 data |= (1 << (val->port_vlan + 3));
1246 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1247
1248 return 0;
1249 }
1250
1251 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1252 const struct switch_attr *attr,
1253 struct switch_val *val)
1254 {
1255 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1256 int i, len = 0;
1257 unsigned long long counter = 0;
1258 char *buf = rtl->buf;
1259
1260 if (val->port_vlan >= RTL8366_NUM_PORTS)
1261 return -EINVAL;
1262
1263 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1264 "Port %d MIB counters\n",
1265 val->port_vlan);
1266
1267 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1268 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1269 "%d:%s\t", i, rtl8366rb_mib_counters[i].name);
1270 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1271 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1272 "[%llu]\n", counter);
1273 else
1274 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1275 "[error]\n");
1276 }
1277
1278 val->value.s = buf;
1279 val->len = len;
1280 return 0;
1281 }
1282
1283 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1284 struct switch_val *val)
1285 {
1286 struct rtl8366rb_vlanconfig vlanmc;
1287 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1288 struct switch_port *port;
1289 int i;
1290
1291 if (val->port_vlan >= RTL8366_NUM_VLANS)
1292 return -EINVAL;
1293
1294 rtl8366rb_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1295
1296 port = &val->value.ports[0];
1297 val->len = 0;
1298 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1299 if (!(vlanmc.member & BIT(i)))
1300 continue;
1301
1302 port->id = i;
1303 port->flags = (vlanmc.untag & BIT(i)) ?
1304 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1305 val->len++;
1306 port++;
1307 }
1308 return 0;
1309 }
1310
1311 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1312 struct switch_val *val)
1313 {
1314 struct rtl8366rb_vlanconfig vlanmc;
1315 struct rtl8366rb_vlan4kentry vlan4k;
1316 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1317 struct switch_port *port;
1318 int i;
1319
1320 if (val->port_vlan >= RTL8366_NUM_VLANS)
1321 return -EINVAL;
1322
1323 rtl8366rb_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1324 rtl8366rb_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1325
1326 vlanmc.untag = 0;
1327 vlanmc.member = 0;
1328
1329 port = &val->value.ports[0];
1330 for (i = 0; i < val->len; i++, port++) {
1331 vlanmc.member |= BIT(port->id);
1332
1333 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1334 vlanmc.untag |= BIT(port->id);
1335 }
1336
1337 vlan4k.member = vlanmc.member;
1338 vlan4k.untag = vlanmc.untag;
1339
1340 rtl8366rb_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1341 rtl8366rb_set_vlan_4k_entry(rtl, &vlan4k);
1342 return 0;
1343 }
1344
1345 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1346 {
1347 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1348 return rtl8366rb_get_vlan_port_pvid(rtl, port, val);
1349 }
1350
1351 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1352 {
1353 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1354 return rtl8366rb_set_vlan_port_pvid(rtl, port, val);
1355 }
1356
1357 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1358 {
1359 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1360 int err;
1361
1362 err = rtl8366rb_reset_chip(rtl);
1363 if (err)
1364 return err;
1365
1366 return rtl8366rb_reset_vlan(rtl);
1367 }
1368
1369 static struct switch_attr rtl8366rb_globals[] = {
1370 {
1371 .type = SWITCH_TYPE_INT,
1372 .name = "enable_vlan",
1373 .description = "Enable VLAN mode",
1374 .set = rtl8366rb_sw_set_vlan_enable,
1375 .get = rtl8366rb_sw_get_vlan_enable,
1376 .max = 1,
1377 .ofs = 1
1378 }, {
1379 .type = SWITCH_TYPE_INT,
1380 .name = "enable_vlan4k",
1381 .description = "Enable VLAN 4K mode",
1382 .set = rtl8366rb_sw_set_vlan_enable,
1383 .get = rtl8366rb_sw_get_vlan_enable,
1384 .max = 1,
1385 .ofs = 2
1386 }, {
1387 .type = SWITCH_TYPE_INT,
1388 .name = "reset_mibs",
1389 .description = "Reset all MIB counters",
1390 .set = rtl8366rb_sw_reset_mibs,
1391 .get = NULL,
1392 .max = 1
1393 }, {
1394 .type = SWITCH_TYPE_INT,
1395 .name = "blinkrate",
1396 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1397 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1398 .set = rtl8366rb_sw_set_blinkrate,
1399 .get = rtl8366rb_sw_get_blinkrate,
1400 .max = 5
1401 },
1402 };
1403
1404 static struct switch_attr rtl8366rb_port[] = {
1405 {
1406 .type = SWITCH_TYPE_STRING,
1407 .name = "link",
1408 .description = "Get port link information",
1409 .max = 1,
1410 .set = NULL,
1411 .get = rtl8366rb_sw_get_port_link,
1412 }, {
1413 .type = SWITCH_TYPE_INT,
1414 .name = "reset_mib",
1415 .description = "Reset single port MIB counters",
1416 .max = 1,
1417 .set = rtl8366rb_sw_reset_port_mibs,
1418 .get = NULL,
1419 }, {
1420 .type = SWITCH_TYPE_STRING,
1421 .name = "mib",
1422 .description = "Get MIB counters for port",
1423 .max = 33,
1424 .set = NULL,
1425 .get = rtl8366rb_sw_get_port_mib,
1426 }, {
1427 .type = SWITCH_TYPE_INT,
1428 .name = "led",
1429 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1430 .max = 15,
1431 .set = rtl8366rb_sw_set_port_led,
1432 .get = rtl8366rb_sw_get_port_led,
1433 },
1434 };
1435
1436 static struct switch_attr rtl8366rb_vlan[] = {
1437 {
1438 .type = SWITCH_TYPE_STRING,
1439 .name = "info",
1440 .description = "Get vlan information",
1441 .max = 1,
1442 .set = NULL,
1443 .get = rtl8366rb_sw_get_vlan_info,
1444 },
1445 };
1446
1447 /* template */
1448 static struct switch_dev rtl8366_switch_dev = {
1449 .name = "RTL8366S",
1450 .cpu_port = RTL8366_PORT_NUM_CPU,
1451 .ports = RTL8366_NUM_PORTS,
1452 .vlans = RTL8366_NUM_VLANS,
1453 .attr_global = {
1454 .attr = rtl8366rb_globals,
1455 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1456 },
1457 .attr_port = {
1458 .attr = rtl8366rb_port,
1459 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1460 },
1461 .attr_vlan = {
1462 .attr = rtl8366rb_vlan,
1463 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1464 },
1465
1466 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1467 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1468 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1469 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1470 .reset_switch = rtl8366rb_sw_reset_switch,
1471 };
1472
1473 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1474 {
1475 struct switch_dev *dev = &rtl->dev;
1476 int err;
1477
1478 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1479 dev->priv = rtl;
1480 dev->devname = dev_name(rtl->parent);
1481
1482 err = register_switch(dev, NULL);
1483 if (err)
1484 dev_err(rtl->parent, "switch registration failed\n");
1485
1486 return err;
1487 }
1488
1489 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1490 {
1491 unregister_switch(&rtl->dev);
1492 }
1493
1494 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1495 {
1496 struct rtl8366rb *rtl = bus->priv;
1497 u32 val = 0;
1498 int err;
1499
1500 err = rtl8366rb_read_phy_reg(rtl, addr, 0, reg, &val);
1501 if (err)
1502 return 0xffff;
1503
1504 return val;
1505 }
1506
1507 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1508 {
1509 struct rtl8366rb *rtl = bus->priv;
1510 u32 t;
1511 int err;
1512
1513 err = rtl8366rb_write_phy_reg(rtl, addr, 0, reg, val);
1514 /* flush write */
1515 (void) rtl8366rb_read_phy_reg(rtl, addr, 0, reg, &t);
1516
1517 return err;
1518 }
1519
1520 static int rtl8366rb_mii_init(struct rtl8366rb *rtl)
1521 {
1522 int ret;
1523 int i;
1524
1525 rtl->mii_bus = mdiobus_alloc();
1526 if (rtl->mii_bus == NULL) {
1527 ret = -ENOMEM;
1528 goto err;
1529 }
1530
1531 rtl->mii_bus->priv = (void *) rtl;
1532 rtl->mii_bus->name = "rtl8366-rtl";
1533 rtl->mii_bus->read = rtl8366rb_mii_read;
1534 rtl->mii_bus->write = rtl8366rb_mii_write;
1535 snprintf(rtl->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1536 dev_name(rtl->parent));
1537 rtl->mii_bus->parent = rtl->parent;
1538 rtl->mii_bus->phy_mask = ~(0x1f);
1539 rtl->mii_bus->irq = rtl->mii_irq;
1540 for (i = 0; i < PHY_MAX_ADDR; i++)
1541 rtl->mii_irq[i] = PHY_POLL;
1542
1543 ret = mdiobus_register(rtl->mii_bus);
1544 if (ret)
1545 goto err_free;
1546
1547 return 0;
1548
1549 err_free:
1550 mdiobus_free(rtl->mii_bus);
1551 err:
1552 return ret;
1553 }
1554
1555 static void rtl8366rb_mii_cleanup(struct rtl8366rb *rtl)
1556 {
1557 mdiobus_unregister(rtl->mii_bus);
1558 mdiobus_free(rtl->mii_bus);
1559 }
1560
1561 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1562 {
1563 return (bus->read == rtl8366rb_mii_read &&
1564 bus->write == rtl8366rb_mii_write);
1565 }
1566
1567 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1568 {
1569 struct rtl8366_smi *smi = &rtl->smi;
1570 u32 chip_id = 0;
1571 u32 chip_ver = 0;
1572 int ret;
1573
1574 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1575 if (ret) {
1576 dev_err(rtl->parent, "unable to read chip id\n");
1577 return ret;
1578 }
1579
1580 switch (chip_id) {
1581 case RTL8366S_CHIP_ID_8366:
1582 break;
1583 default:
1584 dev_err(rtl->parent, "unknown chip id (%04x)\n", chip_id);
1585 return -ENODEV;
1586 }
1587
1588 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1589 &chip_ver);
1590 if (ret) {
1591 dev_err(rtl->parent, "unable to read chip version\n");
1592 return ret;
1593 }
1594
1595 dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
1596 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1597
1598 ret = rtl8366rb_reset_chip(rtl);
1599 if (ret)
1600 return ret;
1601
1602 rtl8366rb_debugfs_init(rtl);
1603 return 0;
1604 }
1605
1606 static int __init rtl8366rb_probe(struct platform_device *pdev)
1607 {
1608 static int rtl8366_smi_version_printed;
1609 struct rtl8366rb_platform_data *pdata;
1610 struct rtl8366rb *rtl;
1611 struct rtl8366_smi *smi;
1612 int err;
1613
1614 if (!rtl8366_smi_version_printed++)
1615 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1616 " version " RTL8366S_DRIVER_VER"\n");
1617
1618 pdata = pdev->dev.platform_data;
1619 if (!pdata) {
1620 dev_err(&pdev->dev, "no platform data specified\n");
1621 err = -EINVAL;
1622 goto err_out;
1623 }
1624
1625 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1626 if (!rtl) {
1627 dev_err(&pdev->dev, "no memory for private data\n");
1628 err = -ENOMEM;
1629 goto err_out;
1630 }
1631
1632 rtl->parent = &pdev->dev;
1633
1634 smi = &rtl->smi;
1635 smi->parent = &pdev->dev;
1636 smi->gpio_sda = pdata->gpio_sda;
1637 smi->gpio_sck = pdata->gpio_sck;
1638
1639 err = rtl8366_smi_init(smi);
1640 if (err)
1641 goto err_free_rtl;
1642
1643 platform_set_drvdata(pdev, rtl);
1644
1645 err = rtl8366rb_setup(rtl);
1646 if (err)
1647 goto err_clear_drvdata;
1648
1649 err = rtl8366rb_mii_init(rtl);
1650 if (err)
1651 goto err_clear_drvdata;
1652
1653 err = rtl8366rb_switch_init(rtl);
1654 if (err)
1655 goto err_mii_cleanup;
1656
1657 return 0;
1658
1659 err_mii_cleanup:
1660 rtl8366rb_mii_cleanup(rtl);
1661 err_clear_drvdata:
1662 platform_set_drvdata(pdev, NULL);
1663 rtl8366_smi_cleanup(smi);
1664 err_free_rtl:
1665 kfree(rtl);
1666 err_out:
1667 return err;
1668 }
1669
1670 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1671 {
1672 if (!rtl8366rb_mii_bus_match(phydev->bus))
1673 return -EINVAL;
1674
1675 return 0;
1676 }
1677
1678 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1679 {
1680 return 0;
1681 }
1682
1683 static struct phy_driver rtl8366rb_phy_driver = {
1684 .phy_id = 0x001cc960,
1685 .name = "Realtek RTL8366RB",
1686 .phy_id_mask = 0x1ffffff0,
1687 .features = PHY_GBIT_FEATURES,
1688 .config_aneg = rtl8366rb_phy_config_aneg,
1689 .config_init = rtl8366rb_phy_config_init,
1690 .read_status = genphy_read_status,
1691 .driver = {
1692 .owner = THIS_MODULE,
1693 },
1694 };
1695
1696 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1697 {
1698 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1699
1700 if (rtl) {
1701 rtl8366rb_switch_cleanup(rtl);
1702 rtl8366rb_debugfs_remove(rtl);
1703 rtl8366rb_mii_cleanup(rtl);
1704 platform_set_drvdata(pdev, NULL);
1705 rtl8366_smi_cleanup(&rtl->smi);
1706 kfree(rtl);
1707 }
1708
1709 return 0;
1710 }
1711
1712 static struct platform_driver rtl8366rb_driver = {
1713 .driver = {
1714 .name = RTL8366RB_DRIVER_NAME,
1715 .owner = THIS_MODULE,
1716 },
1717 .probe = rtl8366rb_probe,
1718 .remove = __devexit_p(rtl8366rb_remove),
1719 };
1720
1721 static int __init rtl8366rb_module_init(void)
1722 {
1723 int ret;
1724 ret = platform_driver_register(&rtl8366rb_driver);
1725 if (ret)
1726 return ret;
1727
1728 ret = phy_driver_register(&rtl8366rb_phy_driver);
1729 if (ret)
1730 goto err_platform_unregister;
1731
1732 return 0;
1733
1734 err_platform_unregister:
1735 platform_driver_unregister(&rtl8366rb_driver);
1736 return ret;
1737 }
1738 module_init(rtl8366rb_module_init);
1739
1740 static void __exit rtl8366rb_module_exit(void)
1741 {
1742 phy_driver_unregister(&rtl8366rb_phy_driver);
1743 platform_driver_unregister(&rtl8366rb_driver);
1744 }
1745 module_exit(rtl8366rb_module_exit);
1746
1747 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1748 MODULE_VERSION(RTL8366S_DRIVER_VER);
1749 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1750 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1751 MODULE_LICENSE("GPL v2");
1752 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);