987947226ea18ac6114d0483d3d5404a0ea743d5
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366rb.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366rb.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366RB ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36 #define RTL8366_CHIP_CTRL_VLAN_4KTB (1 << 14)
37
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
41
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x050A
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0509
45 #define RTL8366S_CHIP_ID_8366 0x5937
46
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8000
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8002
50
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
53
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0xf << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
59
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0430
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
64
65 #define RTL8366_LED_CTRL_REG 0x0431
66 #define RTL8366_LED_0_1_CTRL_REG 0x0432
67 #define RTL8366_LED_2_3_CTRL_REG 0x0433
68
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0050
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x13F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x0FFC
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0001
77
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
81
82
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0063
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
88
89
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018C
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
97
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0020
99
100
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0014
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
108
109
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
117
118
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123 #define RTL8366_PORT_5 (1 << 4) /* In userspace port 4 */
124
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
126
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
128 RTL8366_PORT_2 | \
129 RTL8366_PORT_3 | \
130 RTL8366_PORT_4 | \
131 RTL8366_PORT_5 | \
132 RTL8366_PORT_CPU)
133
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
135 RTL8366_PORT_2 | \
136 RTL8366_PORT_3 | \
137 RTL8366_PORT_4 | \
138 RTL8366_PORT_5)
139
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
141 RTL8366_PORT_2 | \
142 RTL8366_PORT_3 | \
143 RTL8366_PORT_4)
144
145 #define RTL8366_PORT_ALL_INTERNAL RTL8366_PORT_CPU
146
147 struct rtl8366rb {
148 struct device *parent;
149 struct rtl8366_smi smi;
150 struct switch_dev dev;
151 char buf[4096];
152 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
153 struct dentry *debugfs_root;
154 #endif
155 };
156
157 struct rtl8366rb_vlan_mc {
158 u16 reserved2:1;
159 u16 priority:3;
160 u16 vid:12;
161 u16 untag:8;
162 u16 member:8;
163 u16 stag_mbr:8;
164 u16 stag_idx:3;
165 u16 reserved1:2;
166 u16 fid:3;
167 };
168
169 struct rtl8366rb_vlan_4k {
170 u16 reserved1:4;
171 u16 vid:12;
172 u16 untag:8;
173 u16 member:8;
174 u16 reserved2:13;
175 u16 fid:3;
176 };
177
178 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
179 u16 gl_dbg_reg;
180 #endif
181
182 struct mib_counter {
183 unsigned offset;
184 unsigned length;
185 const char *name;
186 };
187
188 static struct mib_counter rtl8366rb_mib_counters[RTL8366S_MIB_COUNT] = {
189 { 0, 4, "IfInOctets " },
190 { 4, 4, "EtherStatsOctets " },
191 { 8, 2, "EtherStatsUnderSizePkts " },
192 { 10, 2, "EtherFregament " },
193 { 12, 2, "EtherStatsPkts64Octets " },
194 { 14, 2, "EtherStatsPkts65to127Octets " },
195 { 16, 2, "EtherStatsPkts128to255Octets " },
196 { 18, 2, "EtherStatsPkts256to511Octets " },
197 { 20, 2, "EtherStatsPkts512to1023Octets " },
198 { 22, 2, "EtherStatsPkts1024to1518Octets " },
199 { 24, 2, "EtherOversizeStats " },
200 { 26, 2, "EtherStatsJabbers " },
201 { 28, 2, "IfInUcastPkts " },
202 { 30, 2, "EtherStatsMulticastPkts " },
203 { 32, 2, "EtherStatsBroadcastPkts " },
204 { 34, 2, "EtherStatsDropEvents " },
205 { 36, 2, "Dot3StatsFCSErrors " },
206 { 38, 2, "Dot3StatsSymbolErrors " },
207 { 40, 2, "Dot3InPauseFrames " },
208 { 42, 2, "Dot3ControlInUnknownOpcodes " },
209 { 44, 4, "IfOutOctets " },
210 { 48, 2, "Dot3StatsSingleCollisionFrames " },
211 { 50, 2, "Dot3StatMultipleCollisionFrames " },
212 { 52, 2, "Dot3sDeferredTransmissions " },
213 { 54, 2, "Dot3StatsLateCollisions " },
214 { 56, 2, "EtherStatsCollisions " },
215 { 58, 2, "Dot3StatsExcessiveCollisions " },
216 { 60, 2, "Dot3OutPauseFrames " },
217 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
218 { 64, 2, "Dot1dTpPortInDiscards " },
219 { 66, 2, "IfOutUcastPkts " },
220 { 68, 2, "IfOutMulticastPkts " },
221 { 70, 2, "IfOutBroadcastPkts " },
222 };
223
224 static inline struct rtl8366rb *smi_to_rtl8366rb(struct rtl8366_smi *smi)
225 {
226 return container_of(smi, struct rtl8366rb, smi);
227 }
228
229 static inline struct rtl8366rb *sw_to_rtl8366rb(struct switch_dev *sw)
230 {
231 return container_of(sw, struct rtl8366rb, dev);
232 }
233
234 static int rtl8366rb_reset_chip(struct rtl8366rb *rtl)
235 {
236 struct rtl8366_smi *smi = &rtl->smi;
237 int timeout = 10;
238 u32 data;
239
240 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
241 RTL8366_CHIP_CTRL_RESET_HW);
242 do {
243 msleep(1);
244 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
245 return -EIO;
246
247 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
248 break;
249 } while (--timeout);
250
251 if (!timeout) {
252 printk("Timeout waiting for the switch to reset\n");
253 return -EIO;
254 }
255
256 return 0;
257 }
258
259 static int rtl8366rb_read_phy_reg(struct rtl8366_smi *smi,
260 u32 phy_no, u32 page, u32 addr, u32 *data)
261 {
262 u32 reg;
263 int ret;
264
265 if (phy_no > RTL8366S_PHY_NO_MAX)
266 return -EINVAL;
267
268 if (page > RTL8366S_PHY_PAGE_MAX)
269 return -EINVAL;
270
271 if (addr > RTL8366S_PHY_ADDR_MAX)
272 return -EINVAL;
273
274 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
275 RTL8366S_PHY_CTRL_READ);
276 if (ret)
277 return ret;
278
279 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
280 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
281 (addr & RTL8366S_PHY_REG_MASK);
282
283 ret = rtl8366_smi_write_reg(smi, reg, 0);
284 if (ret)
285 return ret;
286
287 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
288 if (ret)
289 return ret;
290
291 return 0;
292 }
293
294 static int rtl8366rb_write_phy_reg(struct rtl8366_smi *smi,
295 u32 phy_no, u32 page, u32 addr, u32 data)
296 {
297 u32 reg;
298 int ret;
299
300 if (phy_no > RTL8366S_PHY_NO_MAX)
301 return -EINVAL;
302
303 if (page > RTL8366S_PHY_PAGE_MAX)
304 return -EINVAL;
305
306 if (addr > RTL8366S_PHY_ADDR_MAX)
307 return -EINVAL;
308
309 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
310 RTL8366S_PHY_CTRL_WRITE);
311 if (ret)
312 return ret;
313
314 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
315 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
316 (addr & RTL8366S_PHY_REG_MASK);
317
318 ret = rtl8366_smi_write_reg(smi, reg, data);
319 if (ret)
320 return ret;
321
322 return 0;
323 }
324
325 static int rtl8366_get_mib_counter(struct rtl8366rb *rtl, int counter,
326 int port, unsigned long long *val)
327 {
328 struct rtl8366_smi *smi = &rtl->smi;
329 int i;
330 int err;
331 u32 addr, data;
332 u64 mibvalue;
333
334 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
335 return -EINVAL;
336
337 addr = RTL8366S_MIB_COUNTER_BASE +
338 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
339 rtl8366rb_mib_counters[counter].offset;
340
341 /*
342 * Writing access counter address first
343 * then ASIC will prepare 64bits counter wait for being retrived
344 */
345 data = 0; /* writing data will be discard by ASIC */
346 err = rtl8366_smi_write_reg(smi, addr, data);
347 if (err)
348 return err;
349
350 /* read MIB control register */
351 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
352 if (err)
353 return err;
354
355 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
356 return -EBUSY;
357
358 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
359 return -EIO;
360
361 mibvalue = 0;
362 for (i = rtl8366rb_mib_counters[counter].length; i > 0; i--) {
363 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
364 if (err)
365 return err;
366
367 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
368 }
369
370 *val = mibvalue;
371 return 0;
372 }
373
374 static int rtl8366rb_get_vlan_4k(struct rtl8366rb *rtl, u32 vid,
375 struct rtl8366_vlan_4k *vlan4k)
376 {
377 struct rtl8366_smi *smi = &rtl->smi;
378 struct rtl8366rb_vlan_4k vlan4k_priv;
379 int err;
380 u32 data;
381 u16 *tableaddr;
382
383 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
384 vlan4k_priv.vid = vid;
385
386 if (vid >= RTL8366_NUM_VIDS)
387 return -EINVAL;
388
389 tableaddr = (u16 *)&vlan4k_priv;
390
391 /* write VID */
392 data = *tableaddr;
393 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
394 if (err)
395 return err;
396
397 /* write table access control word */
398 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
399 RTL8366S_TABLE_VLAN_READ_CTRL);
400 if (err)
401 return err;
402
403 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
404 if (err)
405 return err;
406
407 *tableaddr = data;
408 tableaddr++;
409
410 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
411 &data);
412 if (err)
413 return err;
414
415 *tableaddr = data;
416 tableaddr++;
417
418 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 2,
419 &data);
420 if (err)
421 return err;
422 *tableaddr = data;
423
424 vlan4k->vid = vid;
425 vlan4k->untag = vlan4k_priv.untag;
426 vlan4k->member = vlan4k_priv.member;
427 vlan4k->fid = vlan4k_priv.fid;
428
429 return 0;
430 }
431
432 static int rtl8366rb_set_vlan_4k(struct rtl8366rb *rtl,
433 const struct rtl8366_vlan_4k *vlan4k)
434 {
435 struct rtl8366_smi *smi = &rtl->smi;
436 struct rtl8366rb_vlan_4k vlan4k_priv;
437 int err;
438 u32 data;
439 u16 *tableaddr;
440
441 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
442 vlan4k->member > RTL8366_PORT_ALL ||
443 vlan4k->untag > RTL8366_PORT_ALL ||
444 vlan4k->fid > RTL8366S_FIDMAX)
445 return -EINVAL;
446
447 vlan4k_priv.vid = vlan4k->vid;
448 vlan4k_priv.untag = vlan4k->untag;
449 vlan4k_priv.member = vlan4k->member;
450 vlan4k_priv.fid = vlan4k->fid;
451
452 tableaddr = (u16 *)&vlan4k_priv;
453
454 data = *tableaddr;
455
456 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
457 if (err)
458 return err;
459
460 tableaddr++;
461
462 data = *tableaddr;
463
464 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
465 data);
466 if (err)
467 return err;
468
469 tableaddr++;
470
471 data = *tableaddr;
472
473 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 2,
474 data);
475 if (err)
476 return err;
477
478 /* write table access control word */
479 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
480 RTL8366S_TABLE_VLAN_WRITE_CTRL);
481
482 return err;
483 }
484
485 static int rtl8366rb_get_vlan_mc(struct rtl8366rb *rtl, u32 index,
486 struct rtl8366_vlan_mc *vlanmc)
487 {
488 struct rtl8366_smi *smi = &rtl->smi;
489 struct rtl8366rb_vlan_mc vlanmc_priv;
490 int err;
491 u32 addr;
492 u32 data;
493 u16 *tableaddr;
494
495 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
496
497 if (index >= RTL8366_NUM_VLANS)
498 return -EINVAL;
499
500 tableaddr = (u16 *)&vlanmc_priv;
501
502 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
503 err = rtl8366_smi_read_reg(smi, addr, &data);
504 if (err)
505 return err;
506
507 *tableaddr = data;
508 tableaddr++;
509
510 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
511 err = rtl8366_smi_read_reg(smi, addr, &data);
512 if (err)
513 return err;
514
515 *tableaddr = data;
516 tableaddr++;
517
518 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
519 err = rtl8366_smi_read_reg(smi, addr, &data);
520 if (err)
521 return err;
522
523 *tableaddr = data;
524
525 vlanmc->vid = vlanmc_priv.vid;
526 vlanmc->priority = vlanmc_priv.priority;
527 vlanmc->untag = vlanmc_priv.untag;
528 vlanmc->member = vlanmc_priv.member;
529 vlanmc->fid = vlanmc_priv.fid;
530
531 return 0;
532 }
533
534 static int rtl8366rb_set_vlan_mc(struct rtl8366rb *rtl, u32 index,
535 const struct rtl8366_vlan_mc *vlanmc)
536 {
537 struct rtl8366_smi *smi = &rtl->smi;
538 struct rtl8366rb_vlan_mc vlanmc_priv;
539 int err;
540 u32 addr;
541 u32 data;
542 u16 *tableaddr;
543
544 if (index >= RTL8366_NUM_VLANS ||
545 vlanmc->vid >= RTL8366_NUM_VIDS ||
546 vlanmc->priority > RTL8366S_PRIORITYMAX ||
547 vlanmc->member > RTL8366_PORT_ALL ||
548 vlanmc->untag > RTL8366_PORT_ALL ||
549 vlanmc->fid > RTL8366S_FIDMAX)
550 return -EINVAL;
551
552 vlanmc_priv.vid = vlanmc->vid;
553 vlanmc_priv.priority = vlanmc->priority;
554 vlanmc_priv.untag = vlanmc->untag;
555 vlanmc_priv.member = vlanmc->member;
556 vlanmc_priv.stag_mbr = 0;
557 vlanmc_priv.stag_idx = 0;
558 vlanmc_priv.fid = vlanmc->fid;
559
560 addr = RTL8366S_VLAN_MEMCONF_BASE + (index * 3);
561
562 tableaddr = (u16 *)&vlanmc_priv;
563 data = *tableaddr;
564
565 err = rtl8366_smi_write_reg(smi, addr, data);
566 if (err)
567 return err;
568
569 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index * 3);
570
571 tableaddr++;
572 data = *tableaddr;
573
574 err = rtl8366_smi_write_reg(smi, addr, data);
575 if (err)
576 return err;
577
578 addr = RTL8366S_VLAN_MEMCONF_BASE + 2 + (index * 3);
579
580 tableaddr++;
581 data = *tableaddr;
582
583 err = rtl8366_smi_write_reg(smi, addr, data);
584 if (err)
585 return err;
586 return 0;
587 }
588
589 static int rtl8366rb_get_port_vlan_index(struct rtl8366rb *rtl, int port,
590 int *val)
591 {
592 struct rtl8366_smi *smi = &rtl->smi;
593 u32 data;
594 int err;
595
596 if (port >= RTL8366_NUM_PORTS)
597 return -EINVAL;
598
599 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
600 &data);
601 if (err)
602 return err;
603
604 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
605 RTL8366S_PORT_VLAN_CTRL_MASK;
606
607 return 0;
608
609 }
610
611 static int rtl8366rb_get_vlan_port_pvid(struct rtl8366rb *rtl, int port,
612 int *val)
613 {
614 struct rtl8366_vlan_mc vlanmc;
615 int err;
616 int index;
617
618 err = rtl8366rb_get_port_vlan_index(rtl, port, &index);
619 if (err)
620 return err;
621
622 err = rtl8366rb_get_vlan_mc(rtl, index, &vlanmc);
623 if (err)
624 return err;
625
626 *val = vlanmc.vid;
627 return 0;
628 }
629
630 static int rtl8366rb_set_port_vlan_index(struct rtl8366rb *rtl, int port,
631 int index)
632 {
633 struct rtl8366_smi *smi = &rtl->smi;
634 u32 data;
635 int err;
636
637 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
638 return -EINVAL;
639
640 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
641 &data);
642 if (err)
643 return err;
644
645 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
646 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
647 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
648 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
649
650 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
651 data);
652 return err;
653 }
654
655 static int rtl8366rb_set_vlan_port_pvid(struct rtl8366rb *rtl, int port, int val)
656 {
657 int i;
658 struct rtl8366_vlan_mc vlanmc;
659 struct rtl8366_vlan_4k vlan4k;
660
661 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
662 return -EINVAL;
663
664 /* Updating the 4K entry; lookup it and change the port member set */
665 rtl8366rb_get_vlan_4k(rtl, val, &vlan4k);
666 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
667 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
668 rtl8366rb_set_vlan_4k(rtl, &vlan4k);
669
670 /*
671 * For the 16 entries more work needs to be done. First see if such
672 * VID is already there and change it
673 */
674 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
675 rtl8366rb_get_vlan_mc(rtl, i, &vlanmc);
676
677 /* Try to find an existing vid and update port member set */
678 if (val == vlanmc.vid) {
679 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
680 rtl8366rb_set_vlan_mc(rtl, i, &vlanmc);
681
682 /* Now update PVID register settings */
683 rtl8366rb_set_port_vlan_index(rtl, port, i);
684
685 return 0;
686 }
687 }
688
689 /*
690 * PVID could not be found from vlan table. Replace unused (one that
691 * has no member ports) with new one
692 */
693 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
694 rtl8366rb_get_vlan_mc(rtl, i, &vlanmc);
695
696 /*
697 * See if this vlan member configuration is unused. It is
698 * unused if member set contains no ports or CPU port only
699 */
700 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
701 vlanmc.vid = val;
702 vlanmc.priority = 0;
703 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
704 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
705 vlanmc.fid = 0;
706
707 rtl8366rb_set_vlan_mc(rtl, i, &vlanmc);
708
709 /* Now update PVID register settings */
710 rtl8366rb_set_port_vlan_index(rtl, port, i);
711
712 return 0;
713 }
714 }
715
716 dev_err(rtl->parent,
717 "All 16 vlan member configurations are in use\n");
718
719 return -EINVAL;
720 }
721
722
723 static int rtl8366rb_vlan_set_vlan(struct rtl8366rb *rtl, int enable)
724 {
725 struct rtl8366_smi *smi = &rtl->smi;
726 u32 data = 0;
727
728 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
729
730 if (enable)
731 data |= RTL8366_CHIP_CTRL_VLAN;
732 else
733 data &= ~RTL8366_CHIP_CTRL_VLAN;
734
735 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
736 }
737
738 static int rtl8366rb_vlan_set_4ktable(struct rtl8366rb *rtl, int enable)
739 {
740 struct rtl8366_smi *smi = &rtl->smi;
741 u32 data = 0;
742
743 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
744
745 if (enable)
746 data |= RTL8366_CHIP_CTRL_VLAN_4KTB;
747 else
748 data &= ~RTL8366_CHIP_CTRL_VLAN_4KTB;
749
750 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
751 }
752
753 static int rtl8366rb_reset_vlan(struct rtl8366rb *rtl)
754 {
755 struct rtl8366_vlan_4k vlan4k;
756 struct rtl8366_vlan_mc vlanmc;
757 int err;
758 int i;
759
760 /* clear 16 VLAN member configuration */
761 vlanmc.vid = 0;
762 vlanmc.priority = 0;
763 vlanmc.member = 0;
764 vlanmc.untag = 0;
765 vlanmc.fid = 0;
766 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
767 err = rtl8366rb_set_vlan_mc(rtl, i, &vlanmc);
768 if (err)
769 return err;
770 }
771
772 /* Set a default VLAN with vid 1 to 4K table for all ports */
773 vlan4k.vid = 1;
774 vlan4k.member = RTL8366_PORT_ALL;
775 vlan4k.untag = RTL8366_PORT_ALL;
776 vlan4k.fid = 0;
777 err = rtl8366rb_set_vlan_4k(rtl, &vlan4k);
778 if (err)
779 return err;
780
781 /* Set all ports PVID to default VLAN */
782 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
783 err = rtl8366rb_set_vlan_port_pvid(rtl, i, 0);
784 if (err)
785 return err;
786 }
787
788 return 0;
789 }
790
791 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
792 static int rtl8366rb_debugfs_open(struct inode *inode, struct file *file)
793 {
794 file->private_data = inode->i_private;
795 return 0;
796 }
797
798 static ssize_t rtl8366rb_read_debugfs_mibs(struct file *file,
799 char __user *user_buf,
800 size_t count, loff_t *ppos)
801 {
802 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
803 int i, j, len = 0;
804 char *buf = rtl->buf;
805
806 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
807 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
808 " "
809 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
810 "Port 4\n");
811
812 for (i = 0; i < 33; ++i) {
813 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
814 i, rtl8366rb_mib_counters[i].name);
815 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
816 unsigned long long counter = 0;
817
818 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
819 len += snprintf(buf + len,
820 sizeof(rtl->buf) - len,
821 "[%llu]", counter);
822 else
823 len += snprintf(buf + len,
824 sizeof(rtl->buf) - len,
825 "[error]");
826
827 if (j != RTL8366_NUM_PORTS - 1) {
828 if (counter < 100000)
829 len += snprintf(buf + len,
830 sizeof(rtl->buf) - len,
831 "\t");
832
833 len += snprintf(buf + len,
834 sizeof(rtl->buf) - len,
835 "\t");
836 }
837 }
838 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
839 }
840
841 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
842
843 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
844 }
845
846 static ssize_t rtl8366rb_read_debugfs_vlan(struct file *file,
847 char __user *user_buf,
848 size_t count, loff_t *ppos)
849 {
850 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
851 int i, j, len = 0;
852 char *buf = rtl->buf;
853
854 len += snprintf(buf + len, sizeof(rtl->buf) - len,
855 "VLAN Member Config:\n");
856 len += snprintf(buf + len, sizeof(rtl->buf) - len,
857 "\t id \t vid \t prio \t member \t untag \t fid "
858 "\tports\n");
859
860 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
861 struct rtl8366_vlan_mc vlanmc;
862
863 rtl8366rb_get_vlan_mc(rtl, i, &vlanmc);
864
865 len += snprintf(buf + len, sizeof(rtl->buf) - len,
866 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
867 "\t", i, vlanmc.vid, vlanmc.priority,
868 vlanmc.member, vlanmc.untag, vlanmc.fid);
869
870 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
871 int index = 0;
872 if (!rtl8366rb_get_port_vlan_index(rtl, j, &index)) {
873 if (index == i)
874 len += snprintf(buf + len,
875 sizeof(rtl->buf) - len,
876 "%d", j);
877 }
878 }
879 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
880 }
881
882 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
883 }
884
885 static ssize_t rtl8366rb_read_debugfs_reg(struct file *file,
886 char __user *user_buf,
887 size_t count, loff_t *ppos)
888 {
889 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
890 struct rtl8366_smi *smi = &rtl->smi;
891 u32 t, reg = gl_dbg_reg;
892 int err, len = 0;
893 char *buf = rtl->buf;
894
895 memset(buf, '\0', sizeof(rtl->buf));
896
897 err = rtl8366_smi_read_reg(smi, reg, &t);
898 if (err) {
899 len += snprintf(buf, sizeof(rtl->buf),
900 "Read failed (reg: 0x%04x)\n", reg);
901 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
902 }
903
904 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
905 reg, t);
906
907 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
908 }
909
910 static ssize_t rtl8366rb_write_debugfs_reg(struct file *file,
911 const char __user *user_buf,
912 size_t count, loff_t *ppos)
913 {
914 struct rtl8366rb *rtl = (struct rtl8366rb *)file->private_data;
915 struct rtl8366_smi *smi = &rtl->smi;
916 unsigned long data;
917 u32 reg = gl_dbg_reg;
918 int err;
919 size_t len;
920 char *buf = rtl->buf;
921
922 len = min(count, sizeof(rtl->buf) - 1);
923 if (copy_from_user(buf, user_buf, len)) {
924 dev_err(rtl->parent, "copy from user failed\n");
925 return -EFAULT;
926 }
927
928 buf[len] = '\0';
929 if (len > 0 && buf[len - 1] == '\n')
930 buf[len - 1] = '\0';
931
932
933 if (strict_strtoul(buf, 16, &data)) {
934 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
935 } else {
936 err = rtl8366_smi_write_reg(smi, reg, data);
937 if (err) {
938 dev_err(rtl->parent,
939 "writing reg 0x%04x val 0x%04lx failed\n",
940 reg, data);
941 }
942 }
943
944 return count;
945 }
946
947 static const struct file_operations fops_rtl8366rb_regs = {
948 .read = rtl8366rb_read_debugfs_reg,
949 .write = rtl8366rb_write_debugfs_reg,
950 .open = rtl8366rb_debugfs_open,
951 .owner = THIS_MODULE
952 };
953
954 static const struct file_operations fops_rtl8366rb_vlan = {
955 .read = rtl8366rb_read_debugfs_vlan,
956 .open = rtl8366rb_debugfs_open,
957 .owner = THIS_MODULE
958 };
959
960 static const struct file_operations fops_rtl8366rb_mibs = {
961 .read = rtl8366rb_read_debugfs_mibs,
962 .open = rtl8366rb_debugfs_open,
963 .owner = THIS_MODULE
964 };
965
966 static void rtl8366rb_debugfs_init(struct rtl8366rb *rtl)
967 {
968 struct dentry *node;
969 struct dentry *root;
970
971 if (!rtl->debugfs_root)
972 rtl->debugfs_root = debugfs_create_dir("rtl8366rb", NULL);
973
974 if (!rtl->debugfs_root) {
975 dev_err(rtl->parent, "Unable to create debugfs dir\n");
976 return;
977 }
978 root = rtl->debugfs_root;
979
980 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &gl_dbg_reg);
981 if (!node) {
982 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
983 "reg");
984 return;
985 }
986
987 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
988 &fops_rtl8366rb_regs);
989 if (!node) {
990 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
991 "val");
992 return;
993 }
994
995 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
996 &fops_rtl8366rb_vlan);
997 if (!node) {
998 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
999 "vlan");
1000 return;
1001 }
1002
1003 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
1004 &fops_rtl8366rb_mibs);
1005 if (!node) {
1006 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1007 "mibs");
1008 return;
1009 }
1010 }
1011
1012 static void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl)
1013 {
1014 if (rtl->debugfs_root) {
1015 debugfs_remove_recursive(rtl->debugfs_root);
1016 rtl->debugfs_root = NULL;
1017 }
1018 }
1019
1020 #else
1021 static inline void rtl8366rb_debugfs_init(struct rtl8366rb *rtl) {}
1022 static inline void rtl8366rb_debugfs_remove(struct rtl8366rb *rtl) {}
1023 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1024
1025 static int rtl8366rb_sw_reset_mibs(struct switch_dev *dev,
1026 const struct switch_attr *attr,
1027 struct switch_val *val)
1028 {
1029 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1030 struct rtl8366_smi *smi = &rtl->smi;
1031 u32 data = 0;
1032
1033 if (val->value.i == 1) {
1034 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1035 data |= (1 << 2);
1036 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1037 }
1038
1039 return 0;
1040 }
1041
1042 static int rtl8366rb_sw_get_vlan_enable(struct switch_dev *dev,
1043 const struct switch_attr *attr,
1044 struct switch_val *val)
1045 {
1046 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1047 struct rtl8366_smi *smi = &rtl->smi;
1048 u32 data;
1049
1050 if (attr->ofs == 1) {
1051 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1052
1053 if (data & RTL8366_CHIP_CTRL_VLAN)
1054 val->value.i = 1;
1055 else
1056 val->value.i = 0;
1057 } else if (attr->ofs == 2) {
1058 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1059
1060 if (data & RTL8366_CHIP_CTRL_VLAN_4KTB)
1061 val->value.i = 1;
1062 else
1063 val->value.i = 0;
1064 }
1065
1066 return 0;
1067 }
1068
1069 static int rtl8366rb_sw_get_blinkrate(struct switch_dev *dev,
1070 const struct switch_attr *attr,
1071 struct switch_val *val)
1072 {
1073 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1074 struct rtl8366_smi *smi = &rtl->smi;
1075 u32 data;
1076
1077 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1078
1079 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1080
1081 return 0;
1082 }
1083
1084 static int rtl8366rb_sw_set_blinkrate(struct switch_dev *dev,
1085 const struct switch_attr *attr,
1086 struct switch_val *val)
1087 {
1088 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1089 struct rtl8366_smi *smi = &rtl->smi;
1090 u32 data;
1091
1092 if (val->value.i >= 6)
1093 return -EINVAL;
1094
1095 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1096
1097 data &= ~RTL8366_LED_BLINKRATE_MASK;
1098 data |= val->value.i;
1099
1100 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1101
1102 return 0;
1103 }
1104
1105 static int rtl8366rb_sw_set_vlan_enable(struct switch_dev *dev,
1106 const struct switch_attr *attr,
1107 struct switch_val *val)
1108 {
1109 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1110
1111 if (attr->ofs == 1)
1112 return rtl8366rb_vlan_set_vlan(rtl, val->value.i);
1113 else
1114 return rtl8366rb_vlan_set_4ktable(rtl, val->value.i);
1115 }
1116
1117 static const char *rtl8366rb_speed_str(unsigned speed)
1118 {
1119 switch (speed) {
1120 case 0:
1121 return "10baseT";
1122 case 1:
1123 return "100baseT";
1124 case 2:
1125 return "1000baseT";
1126 }
1127
1128 return "unknown";
1129 }
1130
1131 static int rtl8366rb_sw_get_port_link(struct switch_dev *dev,
1132 const struct switch_attr *attr,
1133 struct switch_val *val)
1134 {
1135 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1136 struct rtl8366_smi *smi = &rtl->smi;
1137 u32 len = 0, data = 0;
1138
1139 if (val->port_vlan >= RTL8366_NUM_PORTS)
1140 return -EINVAL;
1141
1142 memset(rtl->buf, '\0', sizeof(rtl->buf));
1143 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1144 (val->port_vlan / 2), &data);
1145
1146 if (val->port_vlan % 2)
1147 data = data >> 8;
1148
1149 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1150 len = snprintf(rtl->buf, sizeof(rtl->buf),
1151 "port:%d link:up speed:%s %s-duplex %s%s%s",
1152 val->port_vlan,
1153 rtl8366rb_speed_str(data &
1154 RTL8366S_PORT_STATUS_SPEED_MASK),
1155 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1156 "full" : "half",
1157 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1158 "tx-pause ": "",
1159 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1160 "rx-pause " : "",
1161 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1162 "nway ": "");
1163 } else {
1164 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1165 val->port_vlan);
1166 }
1167
1168 val->value.s = rtl->buf;
1169 val->len = len;
1170
1171 return 0;
1172 }
1173
1174 static int rtl8366rb_sw_get_vlan_info(struct switch_dev *dev,
1175 const struct switch_attr *attr,
1176 struct switch_val *val)
1177 {
1178 int i;
1179 u32 len = 0;
1180 struct rtl8366_vlan_mc vlanmc;
1181 struct rtl8366_vlan_4k vlan4k;
1182 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1183 char *buf = rtl->buf;
1184
1185 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1186 return -EINVAL;
1187
1188 memset(buf, '\0', sizeof(rtl->buf));
1189
1190 rtl8366rb_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1191 rtl8366rb_get_vlan_4k(rtl, vlanmc.vid, &vlan4k);
1192
1193 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1194 val->port_vlan);
1195
1196 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1197 int index = 0;
1198 if (!rtl8366rb_get_port_vlan_index(rtl, i, &index) &&
1199 index == val->port_vlan)
1200 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1201 "%d", i);
1202 }
1203 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1204
1205 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1206 "\t\t vid \t prio \t member \t untag \t fid\n");
1207 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1208 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1209 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1210 vlanmc.vid, vlanmc.priority, vlanmc.member,
1211 vlanmc.untag, vlanmc.fid);
1212 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1213 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1214 "%d \t \t 0x%04x \t 0x%04x \t %d",
1215 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1216
1217 val->value.s = buf;
1218 val->len = len;
1219
1220 return 0;
1221 }
1222
1223 static int rtl8366rb_sw_set_port_led(struct switch_dev *dev,
1224 const struct switch_attr *attr,
1225 struct switch_val *val)
1226 {
1227 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1228 struct rtl8366_smi *smi = &rtl->smi;
1229 u32 data = 0;
1230
1231 if (val->port_vlan >= RTL8366_NUM_PORTS)
1232 return -EINVAL;
1233
1234 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1235 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1236 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1237 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1238 } else {
1239 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1240 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1241 (val->value.i << (val->port_vlan * 4));
1242 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1243 }
1244
1245 return 0;
1246 }
1247
1248 static int rtl8366rb_sw_get_port_led(struct switch_dev *dev,
1249 const struct switch_attr *attr,
1250 struct switch_val *val)
1251 {
1252 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1253 struct rtl8366_smi *smi = &rtl->smi;
1254 u32 data = 0;
1255
1256 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1257 return -EINVAL;
1258
1259 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1260 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1261
1262 return 0;
1263 }
1264
1265 static int rtl8366rb_sw_reset_port_mibs(struct switch_dev *dev,
1266 const struct switch_attr *attr,
1267 struct switch_val *val)
1268 {
1269 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1270 struct rtl8366_smi *smi = &rtl->smi;
1271 u32 data = 0;
1272
1273 if (val->port_vlan >= RTL8366_NUM_PORTS)
1274 return -EINVAL;
1275
1276 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1277 data |= (1 << (val->port_vlan + 3));
1278 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1279
1280 return 0;
1281 }
1282
1283 static int rtl8366rb_sw_get_port_mib(struct switch_dev *dev,
1284 const struct switch_attr *attr,
1285 struct switch_val *val)
1286 {
1287 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1288 int i, len = 0;
1289 unsigned long long counter = 0;
1290 char *buf = rtl->buf;
1291
1292 if (val->port_vlan >= RTL8366_NUM_PORTS)
1293 return -EINVAL;
1294
1295 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1296 "Port %d MIB counters\n",
1297 val->port_vlan);
1298
1299 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1300 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1301 "%d:%s\t", i, rtl8366rb_mib_counters[i].name);
1302 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1303 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1304 "[%llu]\n", counter);
1305 else
1306 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1307 "[error]\n");
1308 }
1309
1310 val->value.s = buf;
1311 val->len = len;
1312 return 0;
1313 }
1314
1315 static int rtl8366rb_sw_get_vlan_ports(struct switch_dev *dev,
1316 struct switch_val *val)
1317 {
1318 struct rtl8366_vlan_mc vlanmc;
1319 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1320 struct switch_port *port;
1321 int i;
1322
1323 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1324 return -EINVAL;
1325
1326 rtl8366rb_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1327
1328 port = &val->value.ports[0];
1329 val->len = 0;
1330 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1331 if (!(vlanmc.member & BIT(i)))
1332 continue;
1333
1334 port->id = i;
1335 port->flags = (vlanmc.untag & BIT(i)) ?
1336 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1337 val->len++;
1338 port++;
1339 }
1340 return 0;
1341 }
1342
1343 static int rtl8366rb_sw_set_vlan_ports(struct switch_dev *dev,
1344 struct switch_val *val)
1345 {
1346 struct rtl8366_vlan_mc vlanmc;
1347 struct rtl8366_vlan_4k vlan4k;
1348 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1349 struct switch_port *port;
1350 int i;
1351
1352 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1353 return -EINVAL;
1354
1355 rtl8366rb_get_vlan_mc(rtl, val->port_vlan, &vlanmc);
1356 rtl8366rb_get_vlan_4k(rtl, vlanmc.vid, &vlan4k);
1357
1358 vlanmc.untag = 0;
1359 vlanmc.member = 0;
1360
1361 port = &val->value.ports[0];
1362 for (i = 0; i < val->len; i++, port++) {
1363 vlanmc.member |= BIT(port->id);
1364
1365 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1366 vlanmc.untag |= BIT(port->id);
1367 }
1368
1369 vlan4k.member = vlanmc.member;
1370 vlan4k.untag = vlanmc.untag;
1371
1372 rtl8366rb_set_vlan_mc(rtl, val->port_vlan, &vlanmc);
1373 rtl8366rb_set_vlan_4k(rtl, &vlan4k);
1374 return 0;
1375 }
1376
1377 static int rtl8366rb_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1378 {
1379 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1380 return rtl8366rb_get_vlan_port_pvid(rtl, port, val);
1381 }
1382
1383 static int rtl8366rb_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1384 {
1385 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1386 return rtl8366rb_set_vlan_port_pvid(rtl, port, val);
1387 }
1388
1389 static int rtl8366rb_sw_reset_switch(struct switch_dev *dev)
1390 {
1391 struct rtl8366rb *rtl = sw_to_rtl8366rb(dev);
1392 int err;
1393
1394 err = rtl8366rb_reset_chip(rtl);
1395 if (err)
1396 return err;
1397
1398 return rtl8366rb_reset_vlan(rtl);
1399 }
1400
1401 static struct switch_attr rtl8366rb_globals[] = {
1402 {
1403 .type = SWITCH_TYPE_INT,
1404 .name = "enable_vlan",
1405 .description = "Enable VLAN mode",
1406 .set = rtl8366rb_sw_set_vlan_enable,
1407 .get = rtl8366rb_sw_get_vlan_enable,
1408 .max = 1,
1409 .ofs = 1
1410 }, {
1411 .type = SWITCH_TYPE_INT,
1412 .name = "enable_vlan4k",
1413 .description = "Enable VLAN 4K mode",
1414 .set = rtl8366rb_sw_set_vlan_enable,
1415 .get = rtl8366rb_sw_get_vlan_enable,
1416 .max = 1,
1417 .ofs = 2
1418 }, {
1419 .type = SWITCH_TYPE_INT,
1420 .name = "reset_mibs",
1421 .description = "Reset all MIB counters",
1422 .set = rtl8366rb_sw_reset_mibs,
1423 .get = NULL,
1424 .max = 1
1425 }, {
1426 .type = SWITCH_TYPE_INT,
1427 .name = "blinkrate",
1428 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1429 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1430 .set = rtl8366rb_sw_set_blinkrate,
1431 .get = rtl8366rb_sw_get_blinkrate,
1432 .max = 5
1433 },
1434 };
1435
1436 static struct switch_attr rtl8366rb_port[] = {
1437 {
1438 .type = SWITCH_TYPE_STRING,
1439 .name = "link",
1440 .description = "Get port link information",
1441 .max = 1,
1442 .set = NULL,
1443 .get = rtl8366rb_sw_get_port_link,
1444 }, {
1445 .type = SWITCH_TYPE_INT,
1446 .name = "reset_mib",
1447 .description = "Reset single port MIB counters",
1448 .max = 1,
1449 .set = rtl8366rb_sw_reset_port_mibs,
1450 .get = NULL,
1451 }, {
1452 .type = SWITCH_TYPE_STRING,
1453 .name = "mib",
1454 .description = "Get MIB counters for port",
1455 .max = 33,
1456 .set = NULL,
1457 .get = rtl8366rb_sw_get_port_mib,
1458 }, {
1459 .type = SWITCH_TYPE_INT,
1460 .name = "led",
1461 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1462 .max = 15,
1463 .set = rtl8366rb_sw_set_port_led,
1464 .get = rtl8366rb_sw_get_port_led,
1465 },
1466 };
1467
1468 static struct switch_attr rtl8366rb_vlan[] = {
1469 {
1470 .type = SWITCH_TYPE_STRING,
1471 .name = "info",
1472 .description = "Get vlan information",
1473 .max = 1,
1474 .set = NULL,
1475 .get = rtl8366rb_sw_get_vlan_info,
1476 },
1477 };
1478
1479 /* template */
1480 static struct switch_dev rtl8366_switch_dev = {
1481 .name = "RTL8366S",
1482 .cpu_port = RTL8366_PORT_NUM_CPU,
1483 .ports = RTL8366_NUM_PORTS,
1484 .vlans = RTL8366_NUM_VLANS,
1485 .attr_global = {
1486 .attr = rtl8366rb_globals,
1487 .n_attr = ARRAY_SIZE(rtl8366rb_globals),
1488 },
1489 .attr_port = {
1490 .attr = rtl8366rb_port,
1491 .n_attr = ARRAY_SIZE(rtl8366rb_port),
1492 },
1493 .attr_vlan = {
1494 .attr = rtl8366rb_vlan,
1495 .n_attr = ARRAY_SIZE(rtl8366rb_vlan),
1496 },
1497
1498 .get_vlan_ports = rtl8366rb_sw_get_vlan_ports,
1499 .set_vlan_ports = rtl8366rb_sw_set_vlan_ports,
1500 .get_port_pvid = rtl8366rb_sw_get_port_pvid,
1501 .set_port_pvid = rtl8366rb_sw_set_port_pvid,
1502 .reset_switch = rtl8366rb_sw_reset_switch,
1503 };
1504
1505 static int rtl8366rb_switch_init(struct rtl8366rb *rtl)
1506 {
1507 struct switch_dev *dev = &rtl->dev;
1508 int err;
1509
1510 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1511 dev->priv = rtl;
1512 dev->devname = dev_name(rtl->parent);
1513
1514 err = register_switch(dev, NULL);
1515 if (err)
1516 dev_err(rtl->parent, "switch registration failed\n");
1517
1518 return err;
1519 }
1520
1521 static void rtl8366rb_switch_cleanup(struct rtl8366rb *rtl)
1522 {
1523 unregister_switch(&rtl->dev);
1524 }
1525
1526 static int rtl8366rb_mii_read(struct mii_bus *bus, int addr, int reg)
1527 {
1528 struct rtl8366_smi *smi = bus->priv;
1529 u32 val = 0;
1530 int err;
1531
1532 err = rtl8366rb_read_phy_reg(smi, addr, 0, reg, &val);
1533 if (err)
1534 return 0xffff;
1535
1536 return val;
1537 }
1538
1539 static int rtl8366rb_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1540 {
1541 struct rtl8366_smi *smi = bus->priv;
1542 u32 t;
1543 int err;
1544
1545 err = rtl8366rb_write_phy_reg(smi, addr, 0, reg, val);
1546 /* flush write */
1547 (void) rtl8366rb_read_phy_reg(smi, addr, 0, reg, &t);
1548
1549 return err;
1550 }
1551
1552 static int rtl8366rb_mii_bus_match(struct mii_bus *bus)
1553 {
1554 return (bus->read == rtl8366rb_mii_read &&
1555 bus->write == rtl8366rb_mii_write);
1556 }
1557
1558 static int rtl8366rb_setup(struct rtl8366rb *rtl)
1559 {
1560 int ret;
1561
1562 ret = rtl8366rb_reset_chip(rtl);
1563 if (ret)
1564 return ret;
1565
1566 rtl8366rb_debugfs_init(rtl);
1567 return 0;
1568 }
1569
1570 static int rtl8366rb_detect(struct rtl8366_smi *smi)
1571 {
1572 u32 chip_id = 0;
1573 u32 chip_ver = 0;
1574 int ret;
1575
1576 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1577 if (ret) {
1578 dev_err(smi->parent, "unable to read chip id\n");
1579 return ret;
1580 }
1581
1582 switch (chip_id) {
1583 case RTL8366S_CHIP_ID_8366:
1584 break;
1585 default:
1586 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1587 return -ENODEV;
1588 }
1589
1590 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1591 &chip_ver);
1592 if (ret) {
1593 dev_err(smi->parent, "unable to read chip version\n");
1594 return ret;
1595 }
1596
1597 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1598 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1599
1600 return 0;
1601 }
1602
1603 static struct rtl8366_smi_ops rtl8366rb_smi_ops = {
1604 .detect = rtl8366rb_detect,
1605 .mii_read = rtl8366rb_mii_read,
1606 .mii_write = rtl8366rb_mii_write,
1607 };
1608
1609 static int __init rtl8366rb_probe(struct platform_device *pdev)
1610 {
1611 static int rtl8366_smi_version_printed;
1612 struct rtl8366rb_platform_data *pdata;
1613 struct rtl8366rb *rtl;
1614 struct rtl8366_smi *smi;
1615 int err;
1616
1617 if (!rtl8366_smi_version_printed++)
1618 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1619 " version " RTL8366S_DRIVER_VER"\n");
1620
1621 pdata = pdev->dev.platform_data;
1622 if (!pdata) {
1623 dev_err(&pdev->dev, "no platform data specified\n");
1624 err = -EINVAL;
1625 goto err_out;
1626 }
1627
1628 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1629 if (!rtl) {
1630 dev_err(&pdev->dev, "no memory for private data\n");
1631 err = -ENOMEM;
1632 goto err_out;
1633 }
1634
1635 rtl->parent = &pdev->dev;
1636
1637 smi = &rtl->smi;
1638 smi->parent = &pdev->dev;
1639 smi->gpio_sda = pdata->gpio_sda;
1640 smi->gpio_sck = pdata->gpio_sck;
1641 smi->ops = &rtl8366rb_smi_ops;
1642
1643 err = rtl8366_smi_init(smi);
1644 if (err)
1645 goto err_free_rtl;
1646
1647 platform_set_drvdata(pdev, rtl);
1648
1649 err = rtl8366rb_setup(rtl);
1650 if (err)
1651 goto err_clear_drvdata;
1652
1653 err = rtl8366rb_switch_init(rtl);
1654 if (err)
1655 goto err_clear_drvdata;
1656
1657 return 0;
1658
1659 err_clear_drvdata:
1660 platform_set_drvdata(pdev, NULL);
1661 rtl8366_smi_cleanup(smi);
1662 err_free_rtl:
1663 kfree(rtl);
1664 err_out:
1665 return err;
1666 }
1667
1668 static int rtl8366rb_phy_config_init(struct phy_device *phydev)
1669 {
1670 if (!rtl8366rb_mii_bus_match(phydev->bus))
1671 return -EINVAL;
1672
1673 return 0;
1674 }
1675
1676 static int rtl8366rb_phy_config_aneg(struct phy_device *phydev)
1677 {
1678 return 0;
1679 }
1680
1681 static struct phy_driver rtl8366rb_phy_driver = {
1682 .phy_id = 0x001cc960,
1683 .name = "Realtek RTL8366RB",
1684 .phy_id_mask = 0x1ffffff0,
1685 .features = PHY_GBIT_FEATURES,
1686 .config_aneg = rtl8366rb_phy_config_aneg,
1687 .config_init = rtl8366rb_phy_config_init,
1688 .read_status = genphy_read_status,
1689 .driver = {
1690 .owner = THIS_MODULE,
1691 },
1692 };
1693
1694 static int __devexit rtl8366rb_remove(struct platform_device *pdev)
1695 {
1696 struct rtl8366rb *rtl = platform_get_drvdata(pdev);
1697
1698 if (rtl) {
1699 rtl8366rb_switch_cleanup(rtl);
1700 rtl8366rb_debugfs_remove(rtl);
1701 platform_set_drvdata(pdev, NULL);
1702 rtl8366_smi_cleanup(&rtl->smi);
1703 kfree(rtl);
1704 }
1705
1706 return 0;
1707 }
1708
1709 static struct platform_driver rtl8366rb_driver = {
1710 .driver = {
1711 .name = RTL8366RB_DRIVER_NAME,
1712 .owner = THIS_MODULE,
1713 },
1714 .probe = rtl8366rb_probe,
1715 .remove = __devexit_p(rtl8366rb_remove),
1716 };
1717
1718 static int __init rtl8366rb_module_init(void)
1719 {
1720 int ret;
1721 ret = platform_driver_register(&rtl8366rb_driver);
1722 if (ret)
1723 return ret;
1724
1725 ret = phy_driver_register(&rtl8366rb_phy_driver);
1726 if (ret)
1727 goto err_platform_unregister;
1728
1729 return 0;
1730
1731 err_platform_unregister:
1732 platform_driver_unregister(&rtl8366rb_driver);
1733 return ret;
1734 }
1735 module_init(rtl8366rb_module_init);
1736
1737 static void __exit rtl8366rb_module_exit(void)
1738 {
1739 phy_driver_unregister(&rtl8366rb_phy_driver);
1740 platform_driver_unregister(&rtl8366rb_driver);
1741 }
1742 module_exit(rtl8366rb_module_exit);
1743
1744 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1745 MODULE_VERSION(RTL8366S_DRIVER_VER);
1746 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1747 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1748 MODULE_LICENSE("GPL v2");
1749 MODULE_ALIAS("platform:" RTL8366RB_DRIVER_NAME);