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5120f89110e8adf0040a38c44cc1ad594905274f
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36
37 #define RTL8366_RESET_CTRL_REG 0x0100
38 #define RTL8366_CHIP_CTRL_RESET_HW 1
39 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
40
41 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
42 #define RTL8366S_CHIP_VERSION_MASK 0xf
43 #define RTL8366S_CHIP_ID_REG 0x0105
44 #define RTL8366S_CHIP_ID_8366 0x8366
45
46 /* PHY registers control */
47 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
48 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
49
50 #define RTL8366S_PHY_CTRL_READ 1
51 #define RTL8366S_PHY_CTRL_WRITE 0
52
53 #define RTL8366S_PHY_REG_MASK 0x1f
54 #define RTL8366S_PHY_PAGE_OFFSET 5
55 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
56 #define RTL8366S_PHY_NO_OFFSET 9
57 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
58
59 /* LED control registers */
60 #define RTL8366_LED_BLINKRATE_REG 0x0420
61 #define RTL8366_LED_BLINKRATE_BIT 0
62 #define RTL8366_LED_BLINKRATE_MASK 0x0007
63
64 #define RTL8366_LED_CTRL_REG 0x0421
65 #define RTL8366_LED_0_1_CTRL_REG 0x0422
66 #define RTL8366_LED_2_3_CTRL_REG 0x0423
67
68 #define RTL8366S_MIB_COUNT 33
69 #define RTL8366S_GLOBAL_MIB_COUNT 1
70 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
71 #define RTL8366S_MIB_COUNTER_BASE 0x1000
72 #define RTL8366S_MIB_CTRL_REG 0x11F0
73 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
74 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
75 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
76
77 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
78 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
79 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
80
81
82 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
83 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
84 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
85 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
86 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
87
88
89 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
90 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
91
92 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
93
94 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
95 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
96 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
97
98 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
99
100
101 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
102 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
103 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
104 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
105 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
106 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
107 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
108
109
110 #define RTL8366_PORT_NUM_CPU 5
111 #define RTL8366_NUM_PORTS 6
112 #define RTL8366_NUM_VLANS 16
113 #define RTL8366_NUM_LEDGROUPS 4
114 #define RTL8366_NUM_VIDS 4096
115 #define RTL8366S_PRIORITYMAX 7
116 #define RTL8366S_FIDMAX 7
117
118
119 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
120 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
121 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
122 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
123
124 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
125 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
126
127 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
128 RTL8366_PORT_2 | \
129 RTL8366_PORT_3 | \
130 RTL8366_PORT_4 | \
131 RTL8366_PORT_UNKNOWN | \
132 RTL8366_PORT_CPU)
133
134 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
135 RTL8366_PORT_2 | \
136 RTL8366_PORT_3 | \
137 RTL8366_PORT_4 | \
138 RTL8366_PORT_UNKNOWN)
139
140 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
141 RTL8366_PORT_2 | \
142 RTL8366_PORT_3 | \
143 RTL8366_PORT_4)
144
145 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
146 RTL8366_PORT_CPU)
147
148 struct rtl8366s {
149 struct device *parent;
150 struct rtl8366_smi smi;
151 struct switch_dev dev;
152 char buf[4096];
153 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
154 struct dentry *debugfs_root;
155 #endif
156 };
157
158 struct rtl8366s_vlan_mc {
159 u16 reserved2:1;
160 u16 priority:3;
161 u16 vid:12;
162
163 u16 reserved1:1;
164 u16 fid:3;
165 u16 untag:6;
166 u16 member:6;
167 };
168
169 struct rtl8366s_vlan_4k {
170 u16 reserved1:4;
171 u16 vid:12;
172
173 u16 reserved2:1;
174 u16 fid:3;
175 u16 untag:6;
176 u16 member:6;
177 };
178
179 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
180 u16 g_dbg_reg;
181 #endif
182
183 struct mib_counter {
184 unsigned offset;
185 unsigned length;
186 const char *name;
187 };
188
189 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
190 { 0, 4, "IfInOctets " },
191 { 4, 4, "EtherStatsOctets " },
192 { 8, 2, "EtherStatsUnderSizePkts " },
193 { 10, 2, "EtherFregament " },
194 { 12, 2, "EtherStatsPkts64Octets " },
195 { 14, 2, "EtherStatsPkts65to127Octets " },
196 { 16, 2, "EtherStatsPkts128to255Octets " },
197 { 18, 2, "EtherStatsPkts256to511Octets " },
198 { 20, 2, "EtherStatsPkts512to1023Octets " },
199 { 22, 2, "EtherStatsPkts1024to1518Octets " },
200 { 24, 2, "EtherOversizeStats " },
201 { 26, 2, "EtherStatsJabbers " },
202 { 28, 2, "IfInUcastPkts " },
203 { 30, 2, "EtherStatsMulticastPkts " },
204 { 32, 2, "EtherStatsBroadcastPkts " },
205 { 34, 2, "EtherStatsDropEvents " },
206 { 36, 2, "Dot3StatsFCSErrors " },
207 { 38, 2, "Dot3StatsSymbolErrors " },
208 { 40, 2, "Dot3InPauseFrames " },
209 { 42, 2, "Dot3ControlInUnknownOpcodes " },
210 { 44, 4, "IfOutOctets " },
211 { 48, 2, "Dot3StatsSingleCollisionFrames " },
212 { 50, 2, "Dot3StatMultipleCollisionFrames " },
213 { 52, 2, "Dot3sDeferredTransmissions " },
214 { 54, 2, "Dot3StatsLateCollisions " },
215 { 56, 2, "EtherStatsCollisions " },
216 { 58, 2, "Dot3StatsExcessiveCollisions " },
217 { 60, 2, "Dot3OutPauseFrames " },
218 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
219 { 64, 2, "Dot1dTpPortInDiscards " },
220 { 66, 2, "IfOutUcastPkts " },
221 { 68, 2, "IfOutMulticastPkts " },
222 { 70, 2, "IfOutBroadcastPkts " },
223 };
224
225 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
226 {
227 return container_of(smi, struct rtl8366s, smi);
228 }
229
230 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
231 {
232 return container_of(sw, struct rtl8366s, dev);
233 }
234
235 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
236 {
237 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
238 return &rtl->smi;
239 }
240
241 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
242 {
243 int timeout = 10;
244 u32 data;
245
246 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
247 RTL8366_CHIP_CTRL_RESET_HW);
248 do {
249 msleep(1);
250 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
251 return -EIO;
252
253 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
254 break;
255 } while (--timeout);
256
257 if (!timeout) {
258 printk("Timeout waiting for the switch to reset\n");
259 return -EIO;
260 }
261
262 return 0;
263 }
264
265 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
266 u32 phy_no, u32 page, u32 addr, u32 *data)
267 {
268 u32 reg;
269 int ret;
270
271 if (phy_no > RTL8366S_PHY_NO_MAX)
272 return -EINVAL;
273
274 if (page > RTL8366S_PHY_PAGE_MAX)
275 return -EINVAL;
276
277 if (addr > RTL8366S_PHY_ADDR_MAX)
278 return -EINVAL;
279
280 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
281 RTL8366S_PHY_CTRL_READ);
282 if (ret)
283 return ret;
284
285 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
286 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
287 (addr & RTL8366S_PHY_REG_MASK);
288
289 ret = rtl8366_smi_write_reg(smi, reg, 0);
290 if (ret)
291 return ret;
292
293 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
294 if (ret)
295 return ret;
296
297 return 0;
298 }
299
300 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
301 u32 phy_no, u32 page, u32 addr, u32 data)
302 {
303 u32 reg;
304 int ret;
305
306 if (phy_no > RTL8366S_PHY_NO_MAX)
307 return -EINVAL;
308
309 if (page > RTL8366S_PHY_PAGE_MAX)
310 return -EINVAL;
311
312 if (addr > RTL8366S_PHY_ADDR_MAX)
313 return -EINVAL;
314
315 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
316 RTL8366S_PHY_CTRL_WRITE);
317 if (ret)
318 return ret;
319
320 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
321 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
322 (addr & RTL8366S_PHY_REG_MASK);
323
324 ret = rtl8366_smi_write_reg(smi, reg, data);
325 if (ret)
326 return ret;
327
328 return 0;
329 }
330
331 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
332 int port, unsigned long long *val)
333 {
334 int i;
335 int err;
336 u32 addr, data;
337 u64 mibvalue;
338
339 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
340 return -EINVAL;
341
342 addr = RTL8366S_MIB_COUNTER_BASE +
343 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
344 rtl8366s_mib_counters[counter].offset;
345
346 /*
347 * Writing access counter address first
348 * then ASIC will prepare 64bits counter wait for being retrived
349 */
350 data = 0; /* writing data will be discard by ASIC */
351 err = rtl8366_smi_write_reg(smi, addr, data);
352 if (err)
353 return err;
354
355 /* read MIB control register */
356 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
357 if (err)
358 return err;
359
360 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
361 return -EBUSY;
362
363 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
364 return -EIO;
365
366 mibvalue = 0;
367 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
368 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
369 if (err)
370 return err;
371
372 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
373 }
374
375 *val = mibvalue;
376 return 0;
377 }
378
379 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
380 struct rtl8366_vlan_4k *vlan4k)
381 {
382 struct rtl8366s_vlan_4k vlan4k_priv;
383 int err;
384 u32 data;
385 u16 *tableaddr;
386
387 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
388 vlan4k_priv.vid = vid;
389
390 if (vid >= RTL8366_NUM_VIDS)
391 return -EINVAL;
392
393 tableaddr = (u16 *)&vlan4k_priv;
394
395 /* write VID */
396 data = *tableaddr;
397 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
398 if (err)
399 return err;
400
401 /* write table access control word */
402 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
403 RTL8366S_TABLE_VLAN_READ_CTRL);
404 if (err)
405 return err;
406
407 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
408 if (err)
409 return err;
410
411 *tableaddr = data;
412 tableaddr++;
413
414 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
415 &data);
416 if (err)
417 return err;
418
419 *tableaddr = data;
420
421 vlan4k->vid = vid;
422 vlan4k->untag = vlan4k_priv.untag;
423 vlan4k->member = vlan4k_priv.member;
424 vlan4k->fid = vlan4k_priv.fid;
425
426 return 0;
427 }
428
429 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
430 const struct rtl8366_vlan_4k *vlan4k)
431 {
432 struct rtl8366s_vlan_4k vlan4k_priv;
433 int err;
434 u32 data;
435 u16 *tableaddr;
436
437 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
438 vlan4k->member > RTL8366_PORT_ALL ||
439 vlan4k->untag > RTL8366_PORT_ALL ||
440 vlan4k->fid > RTL8366S_FIDMAX)
441 return -EINVAL;
442
443 vlan4k_priv.vid = vlan4k->vid;
444 vlan4k_priv.untag = vlan4k->untag;
445 vlan4k_priv.member = vlan4k->member;
446 vlan4k_priv.fid = vlan4k->fid;
447
448 tableaddr = (u16 *)&vlan4k_priv;
449
450 data = *tableaddr;
451
452 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
453 if (err)
454 return err;
455
456 tableaddr++;
457
458 data = *tableaddr;
459
460 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
461 data);
462 if (err)
463 return err;
464
465 /* write table access control word */
466 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
467 RTL8366S_TABLE_VLAN_WRITE_CTRL);
468
469 return err;
470 }
471
472 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
473 struct rtl8366_vlan_mc *vlanmc)
474 {
475 struct rtl8366s_vlan_mc vlanmc_priv;
476 int err;
477 u32 addr;
478 u32 data;
479 u16 *tableaddr;
480
481 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
482
483 if (index >= RTL8366_NUM_VLANS)
484 return -EINVAL;
485
486 tableaddr = (u16 *)&vlanmc_priv;
487
488 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
489 err = rtl8366_smi_read_reg(smi, addr, &data);
490 if (err)
491 return err;
492
493 *tableaddr = data;
494 tableaddr++;
495
496 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
497 err = rtl8366_smi_read_reg(smi, addr, &data);
498 if (err)
499 return err;
500
501 *tableaddr = data;
502
503 vlanmc->vid = vlanmc_priv.vid;
504 vlanmc->priority = vlanmc_priv.priority;
505 vlanmc->untag = vlanmc_priv.untag;
506 vlanmc->member = vlanmc_priv.member;
507 vlanmc->fid = vlanmc_priv.fid;
508
509 return 0;
510 }
511
512 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
513 const struct rtl8366_vlan_mc *vlanmc)
514 {
515 struct rtl8366s_vlan_mc vlanmc_priv;
516 int err;
517 u32 addr;
518 u32 data;
519 u16 *tableaddr;
520
521 if (index >= RTL8366_NUM_VLANS ||
522 vlanmc->vid >= RTL8366_NUM_VIDS ||
523 vlanmc->priority > RTL8366S_PRIORITYMAX ||
524 vlanmc->member > RTL8366_PORT_ALL ||
525 vlanmc->untag > RTL8366_PORT_ALL ||
526 vlanmc->fid > RTL8366S_FIDMAX)
527 return -EINVAL;
528
529 vlanmc_priv.vid = vlanmc->vid;
530 vlanmc_priv.priority = vlanmc->priority;
531 vlanmc_priv.untag = vlanmc->untag;
532 vlanmc_priv.member = vlanmc->member;
533 vlanmc_priv.fid = vlanmc->fid;
534
535 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
536
537 tableaddr = (u16 *)&vlanmc_priv;
538 data = *tableaddr;
539
540 err = rtl8366_smi_write_reg(smi, addr, data);
541 if (err)
542 return err;
543
544 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
545
546 tableaddr++;
547 data = *tableaddr;
548
549 err = rtl8366_smi_write_reg(smi, addr, data);
550 if (err)
551 return err;
552
553 return 0;
554 }
555
556 static int rtl8366s_get_port_vlan_index(struct rtl8366_smi *smi, int port,
557 int *val)
558 {
559 u32 data;
560 int err;
561
562 if (port >= RTL8366_NUM_PORTS)
563 return -EINVAL;
564
565 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
566 &data);
567 if (err)
568 return err;
569
570 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
571 RTL8366S_PORT_VLAN_CTRL_MASK;
572
573 return 0;
574
575 }
576
577 static int rtl8366s_get_vlan_port_pvid(struct rtl8366_smi *smi, int port,
578 int *val)
579 {
580 struct rtl8366_vlan_mc vlanmc;
581 int err;
582 int index;
583
584 err = rtl8366s_get_port_vlan_index(smi, port, &index);
585 if (err)
586 return err;
587
588 err = rtl8366s_get_vlan_mc(smi, index, &vlanmc);
589 if (err)
590 return err;
591
592 *val = vlanmc.vid;
593 return 0;
594 }
595
596 static int rtl8366s_set_port_vlan_index(struct rtl8366_smi *smi, int port,
597 int index)
598 {
599 u32 data;
600 int err;
601
602 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
603 return -EINVAL;
604
605 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
606 &data);
607 if (err)
608 return err;
609
610 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
611 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
612 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
613 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
614
615 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
616 data);
617 return err;
618 }
619
620 static int rtl8366s_set_vlan_port_pvid(struct rtl8366_smi *smi, int port, int val)
621 {
622 int i;
623 struct rtl8366_vlan_mc vlanmc;
624 struct rtl8366_vlan_4k vlan4k;
625
626 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
627 return -EINVAL;
628
629 /* Updating the 4K entry; lookup it and change the port member set */
630 rtl8366s_get_vlan_4k(smi, val, &vlan4k);
631 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
632 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
633 rtl8366s_set_vlan_4k(smi, &vlan4k);
634
635 /*
636 * For the 16 entries more work needs to be done. First see if such
637 * VID is already there and change it
638 */
639 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
640 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
641
642 /* Try to find an existing vid and update port member set */
643 if (val == vlanmc.vid) {
644 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
645 rtl8366s_set_vlan_mc(smi, i, &vlanmc);
646
647 /* Now update PVID register settings */
648 rtl8366s_set_port_vlan_index(smi, port, i);
649
650 return 0;
651 }
652 }
653
654 /*
655 * PVID could not be found from vlan table. Replace unused (one that
656 * has no member ports) with new one
657 */
658 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
659 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
660
661 /*
662 * See if this vlan member configuration is unused. It is
663 * unused if member set contains no ports or CPU port only
664 */
665 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
666 vlanmc.vid = val;
667 vlanmc.priority = 0;
668 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
669 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
670 vlanmc.fid = 0;
671
672 rtl8366s_set_vlan_mc(smi, i, &vlanmc);
673
674 /* Now update PVID register settings */
675 rtl8366s_set_port_vlan_index(smi, port, i);
676
677 return 0;
678 }
679 }
680
681 dev_err(smi->parent,
682 "All 16 vlan member configurations are in use\n");
683
684 return -EINVAL;
685 }
686
687
688 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
689 {
690 u32 data = 0;
691
692 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
693
694 if (enable)
695 data |= RTL8366_CHIP_CTRL_VLAN;
696 else
697 data &= ~RTL8366_CHIP_CTRL_VLAN;
698
699 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
700 }
701
702 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
703 {
704 u32 data = 0;
705
706 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
707
708 if (enable)
709 data |= 1;
710 else
711 data &= ~1;
712
713 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
714 }
715
716 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
717 {
718 struct rtl8366_vlan_4k vlan4k;
719 struct rtl8366_vlan_mc vlanmc;
720 int err;
721 int i;
722
723 /* clear 16 VLAN member configuration */
724 vlanmc.vid = 0;
725 vlanmc.priority = 0;
726 vlanmc.member = 0;
727 vlanmc.untag = 0;
728 vlanmc.fid = 0;
729 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
730 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
731 if (err)
732 return err;
733 }
734
735 /* Set a default VLAN with vid 1 to 4K table for all ports */
736 vlan4k.vid = 1;
737 vlan4k.member = RTL8366_PORT_ALL;
738 vlan4k.untag = RTL8366_PORT_ALL;
739 vlan4k.fid = 0;
740 err = rtl8366s_set_vlan_4k(smi, &vlan4k);
741 if (err)
742 return err;
743
744 /* Set all ports PVID to default VLAN */
745 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
746 err = rtl8366s_set_vlan_port_pvid(smi, i, 0);
747 if (err)
748 return err;
749 }
750
751 return 0;
752 }
753
754 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
755 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
756 {
757 file->private_data = inode->i_private;
758 return 0;
759 }
760
761 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
762 char __user *user_buf,
763 size_t count, loff_t *ppos)
764 {
765 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
766 struct rtl8366_smi *smi = &rtl->smi;
767 int i, j, len = 0;
768 char *buf = rtl->buf;
769
770 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
771 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
772 " "
773 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
774 "Port 4\n");
775
776 for (i = 0; i < 33; ++i) {
777 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
778 i, rtl8366s_mib_counters[i].name);
779 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
780 unsigned long long counter = 0;
781
782 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
783 len += snprintf(buf + len,
784 sizeof(rtl->buf) - len,
785 "[%llu]", counter);
786 else
787 len += snprintf(buf + len,
788 sizeof(rtl->buf) - len,
789 "[error]");
790
791 if (j != RTL8366_NUM_PORTS - 1) {
792 if (counter < 100000)
793 len += snprintf(buf + len,
794 sizeof(rtl->buf) - len,
795 "\t");
796
797 len += snprintf(buf + len,
798 sizeof(rtl->buf) - len,
799 "\t");
800 }
801 }
802 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
803 }
804
805 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
806
807 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
808 }
809
810 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
811 char __user *user_buf,
812 size_t count, loff_t *ppos)
813 {
814 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
815 struct rtl8366_smi *smi = &rtl->smi;
816 int i, j, len = 0;
817 char *buf = rtl->buf;
818
819 len += snprintf(buf + len, sizeof(rtl->buf) - len,
820 "VLAN Member Config:\n");
821 len += snprintf(buf + len, sizeof(rtl->buf) - len,
822 "\t id \t vid \t prio \t member \t untag \t fid "
823 "\tports\n");
824
825 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
826 struct rtl8366_vlan_mc vlanmc;
827
828 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
829
830 len += snprintf(buf + len, sizeof(rtl->buf) - len,
831 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
832 "\t", i, vlanmc.vid, vlanmc.priority,
833 vlanmc.member, vlanmc.untag, vlanmc.fid);
834
835 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
836 int index = 0;
837 if (!rtl8366s_get_port_vlan_index(smi, j, &index)) {
838 if (index == i)
839 len += snprintf(buf + len,
840 sizeof(rtl->buf) - len,
841 "%d", j);
842 }
843 }
844 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
845 }
846
847 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
848 }
849
850 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
851 char __user *user_buf,
852 size_t count, loff_t *ppos)
853 {
854 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
855 struct rtl8366_smi *smi = &rtl->smi;
856 u32 t, reg = g_dbg_reg;
857 int err, len = 0;
858 char *buf = rtl->buf;
859
860 memset(buf, '\0', sizeof(rtl->buf));
861
862 err = rtl8366_smi_read_reg(smi, reg, &t);
863 if (err) {
864 len += snprintf(buf, sizeof(rtl->buf),
865 "Read failed (reg: 0x%04x)\n", reg);
866 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
867 }
868
869 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
870 reg, t);
871
872 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
873 }
874
875 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
876 const char __user *user_buf,
877 size_t count, loff_t *ppos)
878 {
879 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
880 struct rtl8366_smi *smi = &rtl->smi;
881 unsigned long data;
882 u32 reg = g_dbg_reg;
883 int err;
884 size_t len;
885 char *buf = rtl->buf;
886
887 len = min(count, sizeof(rtl->buf) - 1);
888 if (copy_from_user(buf, user_buf, len)) {
889 dev_err(rtl->parent, "copy from user failed\n");
890 return -EFAULT;
891 }
892
893 buf[len] = '\0';
894 if (len > 0 && buf[len - 1] == '\n')
895 buf[len - 1] = '\0';
896
897
898 if (strict_strtoul(buf, 16, &data)) {
899 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
900 } else {
901 err = rtl8366_smi_write_reg(smi, reg, data);
902 if (err) {
903 dev_err(rtl->parent,
904 "writing reg 0x%04x val 0x%04lx failed\n",
905 reg, data);
906 }
907 }
908
909 return count;
910 }
911
912 static const struct file_operations fops_rtl8366s_regs = {
913 .read = rtl8366s_read_debugfs_reg,
914 .write = rtl8366s_write_debugfs_reg,
915 .open = rtl8366s_debugfs_open,
916 .owner = THIS_MODULE
917 };
918
919 static const struct file_operations fops_rtl8366s_vlan = {
920 .read = rtl8366s_read_debugfs_vlan,
921 .open = rtl8366s_debugfs_open,
922 .owner = THIS_MODULE
923 };
924
925 static const struct file_operations fops_rtl8366s_mibs = {
926 .read = rtl8366s_read_debugfs_mibs,
927 .open = rtl8366s_debugfs_open,
928 .owner = THIS_MODULE
929 };
930
931 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
932 {
933 struct dentry *node;
934 struct dentry *root;
935
936 if (!rtl->debugfs_root)
937 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
938
939 if (!rtl->debugfs_root) {
940 dev_err(rtl->parent, "Unable to create debugfs dir\n");
941 return;
942 }
943 root = rtl->debugfs_root;
944
945 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
946 if (!node) {
947 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
948 "reg");
949 return;
950 }
951
952 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
953 &fops_rtl8366s_regs);
954 if (!node) {
955 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
956 "val");
957 return;
958 }
959
960 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
961 &fops_rtl8366s_vlan);
962 if (!node) {
963 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
964 "vlan");
965 return;
966 }
967
968 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
969 &fops_rtl8366s_mibs);
970 if (!node) {
971 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
972 "mibs");
973 return;
974 }
975 }
976
977 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
978 {
979 if (rtl->debugfs_root) {
980 debugfs_remove_recursive(rtl->debugfs_root);
981 rtl->debugfs_root = NULL;
982 }
983 }
984
985 #else
986 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
987 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
988 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
989
990 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
991 const struct switch_attr *attr,
992 struct switch_val *val)
993 {
994 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
995 u32 data = 0;
996
997 if (val->value.i == 1) {
998 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
999 data |= (1 << 2);
1000 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1001 }
1002
1003 return 0;
1004 }
1005
1006 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
1007 const struct switch_attr *attr,
1008 struct switch_val *val)
1009 {
1010 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1011 u32 data;
1012
1013 if (attr->ofs == 1) {
1014 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1015
1016 if (data & RTL8366_CHIP_CTRL_VLAN)
1017 val->value.i = 1;
1018 else
1019 val->value.i = 0;
1020 } else if (attr->ofs == 2) {
1021 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1022
1023 if (data & 0x0001)
1024 val->value.i = 1;
1025 else
1026 val->value.i = 0;
1027 }
1028
1029 return 0;
1030 }
1031
1032 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1033 const struct switch_attr *attr,
1034 struct switch_val *val)
1035 {
1036 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1037 u32 data;
1038
1039 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1040
1041 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1042
1043 return 0;
1044 }
1045
1046 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1047 const struct switch_attr *attr,
1048 struct switch_val *val)
1049 {
1050 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1051 u32 data;
1052
1053 if (val->value.i >= 6)
1054 return -EINVAL;
1055
1056 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1057
1058 data &= ~RTL8366_LED_BLINKRATE_MASK;
1059 data |= val->value.i;
1060
1061 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1062
1063 return 0;
1064 }
1065
1066 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1067 const struct switch_attr *attr,
1068 struct switch_val *val)
1069 {
1070 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1071
1072 if (attr->ofs == 1)
1073 return rtl8366s_vlan_set_vlan(smi, val->value.i);
1074 else
1075 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
1076 }
1077
1078 static const char *rtl8366s_speed_str(unsigned speed)
1079 {
1080 switch (speed) {
1081 case 0:
1082 return "10baseT";
1083 case 1:
1084 return "100baseT";
1085 case 2:
1086 return "1000baseT";
1087 }
1088
1089 return "unknown";
1090 }
1091
1092 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1093 const struct switch_attr *attr,
1094 struct switch_val *val)
1095 {
1096 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1097 struct rtl8366_smi *smi = &rtl->smi;
1098 u32 len = 0, data = 0;
1099
1100 if (val->port_vlan >= RTL8366_NUM_PORTS)
1101 return -EINVAL;
1102
1103 memset(rtl->buf, '\0', sizeof(rtl->buf));
1104 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1105 (val->port_vlan / 2), &data);
1106
1107 if (val->port_vlan % 2)
1108 data = data >> 8;
1109
1110 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1111 len = snprintf(rtl->buf, sizeof(rtl->buf),
1112 "port:%d link:up speed:%s %s-duplex %s%s%s",
1113 val->port_vlan,
1114 rtl8366s_speed_str(data &
1115 RTL8366S_PORT_STATUS_SPEED_MASK),
1116 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1117 "full" : "half",
1118 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1119 "tx-pause ": "",
1120 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1121 "rx-pause " : "",
1122 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1123 "nway ": "");
1124 } else {
1125 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1126 val->port_vlan);
1127 }
1128
1129 val->value.s = rtl->buf;
1130 val->len = len;
1131
1132 return 0;
1133 }
1134
1135 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1136 const struct switch_attr *attr,
1137 struct switch_val *val)
1138 {
1139 int i;
1140 u32 len = 0;
1141 struct rtl8366_vlan_mc vlanmc;
1142 struct rtl8366_vlan_4k vlan4k;
1143 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1144 struct rtl8366_smi *smi = &rtl->smi;
1145 char *buf = rtl->buf;
1146
1147 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1148 return -EINVAL;
1149
1150 memset(buf, '\0', sizeof(rtl->buf));
1151
1152 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1153 rtl8366s_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1154
1155 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1156 val->port_vlan);
1157
1158 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1159 int index = 0;
1160 if (!rtl8366s_get_port_vlan_index(smi, i, &index) &&
1161 index == val->port_vlan)
1162 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1163 "%d", i);
1164 }
1165 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1166
1167 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1168 "\t\t vid \t prio \t member \t untag \t fid\n");
1169 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1170 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1171 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1172 vlanmc.vid, vlanmc.priority, vlanmc.member,
1173 vlanmc.untag, vlanmc.fid);
1174 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1175 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1176 "%d \t \t 0x%04x \t 0x%04x \t %d",
1177 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1178
1179 val->value.s = buf;
1180 val->len = len;
1181
1182 return 0;
1183 }
1184
1185 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1186 const struct switch_attr *attr,
1187 struct switch_val *val)
1188 {
1189 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1190 u32 data = 0;
1191
1192 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1193 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1194 return -EINVAL;
1195
1196 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1197 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1198 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1199 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1200 } else {
1201 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1202 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1203 (val->value.i << (val->port_vlan * 4));
1204 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1205 }
1206
1207 return 0;
1208 }
1209
1210 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1211 const struct switch_attr *attr,
1212 struct switch_val *val)
1213 {
1214 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1215 u32 data = 0;
1216
1217 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1218 return -EINVAL;
1219
1220 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1221 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1222
1223 return 0;
1224 }
1225
1226 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1227 const struct switch_attr *attr,
1228 struct switch_val *val)
1229 {
1230 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1231 u32 data = 0;
1232
1233 if (val->port_vlan >= RTL8366_NUM_PORTS)
1234 return -EINVAL;
1235
1236 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1237 data |= (1 << (val->port_vlan + 3));
1238 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1239
1240 return 0;
1241 }
1242
1243 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1244 const struct switch_attr *attr,
1245 struct switch_val *val)
1246 {
1247 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1248 struct rtl8366_smi *smi = &rtl->smi;
1249 int i, len = 0;
1250 unsigned long long counter = 0;
1251 char *buf = rtl->buf;
1252
1253 if (val->port_vlan >= RTL8366_NUM_PORTS)
1254 return -EINVAL;
1255
1256 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1257 "Port %d MIB counters\n",
1258 val->port_vlan);
1259
1260 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1261 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1262 "%d:%s\t", i, rtl8366s_mib_counters[i].name);
1263 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1264 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1265 "[%llu]\n", counter);
1266 else
1267 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1268 "[error]\n");
1269 }
1270
1271 val->value.s = buf;
1272 val->len = len;
1273 return 0;
1274 }
1275
1276 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1277 struct switch_val *val)
1278 {
1279 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1280 struct rtl8366_vlan_mc vlanmc;
1281 struct switch_port *port;
1282 int i;
1283
1284 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1285 return -EINVAL;
1286
1287 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1288
1289 port = &val->value.ports[0];
1290 val->len = 0;
1291 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1292 if (!(vlanmc.member & BIT(i)))
1293 continue;
1294
1295 port->id = i;
1296 port->flags = (vlanmc.untag & BIT(i)) ?
1297 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1298 val->len++;
1299 port++;
1300 }
1301 return 0;
1302 }
1303
1304 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1305 struct switch_val *val)
1306 {
1307 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1308 struct rtl8366_vlan_mc vlanmc;
1309 struct rtl8366_vlan_4k vlan4k;
1310 struct switch_port *port;
1311 int i;
1312
1313 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1314 return -EINVAL;
1315
1316 rtl8366s_get_vlan_mc(smi, val->port_vlan, &vlanmc);
1317 rtl8366s_get_vlan_4k(smi, vlanmc.vid, &vlan4k);
1318
1319 vlanmc.untag = 0;
1320 vlanmc.member = 0;
1321
1322 port = &val->value.ports[0];
1323 for (i = 0; i < val->len; i++, port++) {
1324 vlanmc.member |= BIT(port->id);
1325
1326 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1327 vlanmc.untag |= BIT(port->id);
1328 }
1329
1330 vlan4k.member = vlanmc.member;
1331 vlan4k.untag = vlanmc.untag;
1332
1333 rtl8366s_set_vlan_mc(smi, val->port_vlan, &vlanmc);
1334 rtl8366s_set_vlan_4k(smi, &vlan4k);
1335 return 0;
1336 }
1337
1338 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1339 {
1340 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1341 return rtl8366s_get_vlan_port_pvid(smi, port, val);
1342 }
1343
1344 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1345 {
1346 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1347 return rtl8366s_set_vlan_port_pvid(smi, port, val);
1348 }
1349
1350 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1351 {
1352 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1353 int err;
1354
1355 err = rtl8366s_reset_chip(smi);
1356 if (err)
1357 return err;
1358
1359 return rtl8366s_reset_vlan(smi);
1360 }
1361
1362 static struct switch_attr rtl8366s_globals[] = {
1363 {
1364 .type = SWITCH_TYPE_INT,
1365 .name = "enable_vlan",
1366 .description = "Enable VLAN mode",
1367 .set = rtl8366s_sw_set_vlan_enable,
1368 .get = rtl8366s_sw_get_vlan_enable,
1369 .max = 1,
1370 .ofs = 1
1371 }, {
1372 .type = SWITCH_TYPE_INT,
1373 .name = "enable_vlan4k",
1374 .description = "Enable VLAN 4K mode",
1375 .set = rtl8366s_sw_set_vlan_enable,
1376 .get = rtl8366s_sw_get_vlan_enable,
1377 .max = 1,
1378 .ofs = 2
1379 }, {
1380 .type = SWITCH_TYPE_INT,
1381 .name = "reset_mibs",
1382 .description = "Reset all MIB counters",
1383 .set = rtl8366s_sw_reset_mibs,
1384 .get = NULL,
1385 .max = 1
1386 }, {
1387 .type = SWITCH_TYPE_INT,
1388 .name = "blinkrate",
1389 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1390 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1391 .set = rtl8366s_sw_set_blinkrate,
1392 .get = rtl8366s_sw_get_blinkrate,
1393 .max = 5
1394 },
1395 };
1396
1397 static struct switch_attr rtl8366s_port[] = {
1398 {
1399 .type = SWITCH_TYPE_STRING,
1400 .name = "link",
1401 .description = "Get port link information",
1402 .max = 1,
1403 .set = NULL,
1404 .get = rtl8366s_sw_get_port_link,
1405 }, {
1406 .type = SWITCH_TYPE_INT,
1407 .name = "reset_mib",
1408 .description = "Reset single port MIB counters",
1409 .max = 1,
1410 .set = rtl8366s_sw_reset_port_mibs,
1411 .get = NULL,
1412 }, {
1413 .type = SWITCH_TYPE_STRING,
1414 .name = "mib",
1415 .description = "Get MIB counters for port",
1416 .max = 33,
1417 .set = NULL,
1418 .get = rtl8366s_sw_get_port_mib,
1419 }, {
1420 .type = SWITCH_TYPE_INT,
1421 .name = "led",
1422 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1423 .max = 15,
1424 .set = rtl8366s_sw_set_port_led,
1425 .get = rtl8366s_sw_get_port_led,
1426 },
1427 };
1428
1429 static struct switch_attr rtl8366s_vlan[] = {
1430 {
1431 .type = SWITCH_TYPE_STRING,
1432 .name = "info",
1433 .description = "Get vlan information",
1434 .max = 1,
1435 .set = NULL,
1436 .get = rtl8366s_sw_get_vlan_info,
1437 },
1438 };
1439
1440 /* template */
1441 static struct switch_dev rtl8366_switch_dev = {
1442 .name = "RTL8366S",
1443 .cpu_port = RTL8366_PORT_NUM_CPU,
1444 .ports = RTL8366_NUM_PORTS,
1445 .vlans = RTL8366_NUM_VLANS,
1446 .attr_global = {
1447 .attr = rtl8366s_globals,
1448 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1449 },
1450 .attr_port = {
1451 .attr = rtl8366s_port,
1452 .n_attr = ARRAY_SIZE(rtl8366s_port),
1453 },
1454 .attr_vlan = {
1455 .attr = rtl8366s_vlan,
1456 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1457 },
1458
1459 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1460 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1461 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1462 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1463 .reset_switch = rtl8366s_sw_reset_switch,
1464 };
1465
1466 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1467 {
1468 struct switch_dev *dev = &rtl->dev;
1469 int err;
1470
1471 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1472 dev->priv = rtl;
1473 dev->devname = dev_name(rtl->parent);
1474
1475 err = register_switch(dev, NULL);
1476 if (err)
1477 dev_err(rtl->parent, "switch registration failed\n");
1478
1479 return err;
1480 }
1481
1482 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1483 {
1484 unregister_switch(&rtl->dev);
1485 }
1486
1487 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1488 {
1489 struct rtl8366_smi *smi = bus->priv;
1490 u32 val = 0;
1491 int err;
1492
1493 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1494 if (err)
1495 return 0xffff;
1496
1497 return val;
1498 }
1499
1500 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1501 {
1502 struct rtl8366_smi *smi = bus->priv;
1503 u32 t;
1504 int err;
1505
1506 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1507 /* flush write */
1508 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1509
1510 return err;
1511 }
1512
1513 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1514 {
1515 return (bus->read == rtl8366s_mii_read &&
1516 bus->write == rtl8366s_mii_write);
1517 }
1518
1519 static int rtl8366s_setup(struct rtl8366s *rtl)
1520 {
1521 struct rtl8366_smi *smi = &rtl->smi;
1522 int ret;
1523
1524 ret = rtl8366s_reset_chip(smi);
1525 if (ret)
1526 return ret;
1527
1528 rtl8366s_debugfs_init(rtl);
1529 return 0;
1530 }
1531
1532 static int rtl8366s_detect(struct rtl8366_smi *smi)
1533 {
1534 u32 chip_id = 0;
1535 u32 chip_ver = 0;
1536 int ret;
1537
1538 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1539 if (ret) {
1540 dev_err(smi->parent, "unable to read chip id\n");
1541 return ret;
1542 }
1543
1544 switch (chip_id) {
1545 case RTL8366S_CHIP_ID_8366:
1546 break;
1547 default:
1548 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1549 return -ENODEV;
1550 }
1551
1552 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1553 &chip_ver);
1554 if (ret) {
1555 dev_err(smi->parent, "unable to read chip version\n");
1556 return ret;
1557 }
1558
1559 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1560 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1561
1562 return 0;
1563 }
1564
1565 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1566 .detect = rtl8366s_detect,
1567 .mii_read = rtl8366s_mii_read,
1568 .mii_write = rtl8366s_mii_write,
1569 };
1570
1571 static int __init rtl8366s_probe(struct platform_device *pdev)
1572 {
1573 static int rtl8366_smi_version_printed;
1574 struct rtl8366s_platform_data *pdata;
1575 struct rtl8366s *rtl;
1576 struct rtl8366_smi *smi;
1577 int err;
1578
1579 if (!rtl8366_smi_version_printed++)
1580 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1581 " version " RTL8366S_DRIVER_VER"\n");
1582
1583 pdata = pdev->dev.platform_data;
1584 if (!pdata) {
1585 dev_err(&pdev->dev, "no platform data specified\n");
1586 err = -EINVAL;
1587 goto err_out;
1588 }
1589
1590 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1591 if (!rtl) {
1592 dev_err(&pdev->dev, "no memory for private data\n");
1593 err = -ENOMEM;
1594 goto err_out;
1595 }
1596
1597 rtl->parent = &pdev->dev;
1598
1599 smi = &rtl->smi;
1600 smi->parent = &pdev->dev;
1601 smi->gpio_sda = pdata->gpio_sda;
1602 smi->gpio_sck = pdata->gpio_sck;
1603 smi->ops = &rtl8366s_smi_ops;
1604
1605 err = rtl8366_smi_init(smi);
1606 if (err)
1607 goto err_free_rtl;
1608
1609 platform_set_drvdata(pdev, rtl);
1610
1611 err = rtl8366s_setup(rtl);
1612 if (err)
1613 goto err_clear_drvdata;
1614
1615 err = rtl8366s_switch_init(rtl);
1616 if (err)
1617 goto err_clear_drvdata;
1618
1619 return 0;
1620
1621 err_clear_drvdata:
1622 platform_set_drvdata(pdev, NULL);
1623 rtl8366_smi_cleanup(smi);
1624 err_free_rtl:
1625 kfree(rtl);
1626 err_out:
1627 return err;
1628 }
1629
1630 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1631 {
1632 if (!rtl8366s_mii_bus_match(phydev->bus))
1633 return -EINVAL;
1634
1635 return 0;
1636 }
1637
1638 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1639 {
1640 return 0;
1641 }
1642
1643 static struct phy_driver rtl8366s_phy_driver = {
1644 .phy_id = 0x001cc960,
1645 .name = "Realtek RTL8366S",
1646 .phy_id_mask = 0x1ffffff0,
1647 .features = PHY_GBIT_FEATURES,
1648 .config_aneg = rtl8366s_phy_config_aneg,
1649 .config_init = rtl8366s_phy_config_init,
1650 .read_status = genphy_read_status,
1651 .driver = {
1652 .owner = THIS_MODULE,
1653 },
1654 };
1655
1656 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1657 {
1658 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1659
1660 if (rtl) {
1661 rtl8366s_switch_cleanup(rtl);
1662 rtl8366s_debugfs_remove(rtl);
1663 platform_set_drvdata(pdev, NULL);
1664 rtl8366_smi_cleanup(&rtl->smi);
1665 kfree(rtl);
1666 }
1667
1668 return 0;
1669 }
1670
1671 static struct platform_driver rtl8366s_driver = {
1672 .driver = {
1673 .name = RTL8366S_DRIVER_NAME,
1674 .owner = THIS_MODULE,
1675 },
1676 .probe = rtl8366s_probe,
1677 .remove = __devexit_p(rtl8366s_remove),
1678 };
1679
1680 static int __init rtl8366s_module_init(void)
1681 {
1682 int ret;
1683 ret = platform_driver_register(&rtl8366s_driver);
1684 if (ret)
1685 return ret;
1686
1687 ret = phy_driver_register(&rtl8366s_phy_driver);
1688 if (ret)
1689 goto err_platform_unregister;
1690
1691 return 0;
1692
1693 err_platform_unregister:
1694 platform_driver_unregister(&rtl8366s_driver);
1695 return ret;
1696 }
1697 module_init(rtl8366s_module_init);
1698
1699 static void __exit rtl8366s_module_exit(void)
1700 {
1701 phy_driver_unregister(&rtl8366s_phy_driver);
1702 platform_driver_unregister(&rtl8366s_driver);
1703 }
1704 module_exit(rtl8366s_module_exit);
1705
1706 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1707 MODULE_VERSION(RTL8366S_DRIVER_VER);
1708 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1709 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1710 MODULE_LICENSE("GPL v2");
1711 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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