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[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
36
37 /* Switch Global Configuration register */
38 #define RTL8366_SGCR 0x0000
39 #define RTL8366_SGCR_EN_BC_STORM_CTRL BIT(0)
40 #define RTL8366_SGCR_MAX_LENGTH(_x) (_x << 4)
41 #define RTL8366_SGCR_MAX_LENGTH_MASK RTL8366_SGCR_MAX_LENGTH(0x3)
42 #define RTL8366_SGCR_MAX_LENGTH_1522 RTL8366_SGCR_MAX_LENGTH(0x0)
43 #define RTL8366_SGCR_MAX_LENGTH_1536 RTL8366_SGCR_MAX_LENGTH(0x1)
44 #define RTL8366_SGCR_MAX_LENGTH_1552 RTL8366_SGCR_MAX_LENGTH(0x2)
45 #define RTL8366_SGCR_MAX_LENGTH_16000 RTL8366_SGCR_MAX_LENGTH(0x3)
46
47 /* Port Enable Control register */
48 #define RTL8366_PECR 0x0001
49
50 /* Switch Security Control registers */
51 #define RTL8366_SSCR0 0x0002
52 #define RTL8366_SSCR1 0x0003
53 #define RTL8366_SSCR2 0x0004
54 #define RTL8366_SSCR2_DROP_UNKNOWN_DA BIT(0)
55
56 #define RTL8366_RESET_CTRL_REG 0x0100
57 #define RTL8366_CHIP_CTRL_RESET_HW 1
58 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
59
60 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
61 #define RTL8366S_CHIP_VERSION_MASK 0xf
62 #define RTL8366S_CHIP_ID_REG 0x0105
63 #define RTL8366S_CHIP_ID_8366 0x8366
64
65 /* PHY registers control */
66 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
67 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
68
69 #define RTL8366S_PHY_CTRL_READ 1
70 #define RTL8366S_PHY_CTRL_WRITE 0
71
72 #define RTL8366S_PHY_REG_MASK 0x1f
73 #define RTL8366S_PHY_PAGE_OFFSET 5
74 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
75 #define RTL8366S_PHY_NO_OFFSET 9
76 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
77
78 /* LED control registers */
79 #define RTL8366_LED_BLINKRATE_REG 0x0420
80 #define RTL8366_LED_BLINKRATE_BIT 0
81 #define RTL8366_LED_BLINKRATE_MASK 0x0007
82
83 #define RTL8366_LED_CTRL_REG 0x0421
84 #define RTL8366_LED_0_1_CTRL_REG 0x0422
85 #define RTL8366_LED_2_3_CTRL_REG 0x0423
86
87 #define RTL8366S_MIB_COUNT 33
88 #define RTL8366S_GLOBAL_MIB_COUNT 1
89 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
90 #define RTL8366S_MIB_COUNTER_BASE 0x1000
91 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
92 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
93 #define RTL8366S_MIB_CTRL_REG 0x11F0
94 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
95 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
96 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
97
98 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
99 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
100 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
101
102
103 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
104 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
105 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
106 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
107 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
108
109
110 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
111 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
112
113 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
114
115 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
116 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
117 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
118
119 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
120
121
122 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
123 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
124 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
125 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
126 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
127 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
128 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
129
130
131 #define RTL8366_PORT_NUM_CPU 5
132 #define RTL8366_NUM_PORTS 6
133 #define RTL8366_NUM_VLANS 16
134 #define RTL8366_NUM_LEDGROUPS 4
135 #define RTL8366_NUM_VIDS 4096
136 #define RTL8366S_PRIORITYMAX 7
137 #define RTL8366S_FIDMAX 7
138
139
140 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
141 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
142 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
143 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
144
145 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
146 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
147
148 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
149 RTL8366_PORT_2 | \
150 RTL8366_PORT_3 | \
151 RTL8366_PORT_4 | \
152 RTL8366_PORT_UNKNOWN | \
153 RTL8366_PORT_CPU)
154
155 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
156 RTL8366_PORT_2 | \
157 RTL8366_PORT_3 | \
158 RTL8366_PORT_4 | \
159 RTL8366_PORT_UNKNOWN)
160
161 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
162 RTL8366_PORT_2 | \
163 RTL8366_PORT_3 | \
164 RTL8366_PORT_4)
165
166 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
167 RTL8366_PORT_CPU)
168
169 struct rtl8366s {
170 struct device *parent;
171 struct rtl8366_smi smi;
172 struct switch_dev dev;
173 char buf[4096];
174 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
175 struct dentry *debugfs_root;
176 #endif
177 };
178
179 struct rtl8366s_vlan_mc {
180 u16 reserved2:1;
181 u16 priority:3;
182 u16 vid:12;
183
184 u16 reserved1:1;
185 u16 fid:3;
186 u16 untag:6;
187 u16 member:6;
188 };
189
190 struct rtl8366s_vlan_4k {
191 u16 reserved1:4;
192 u16 vid:12;
193
194 u16 reserved2:1;
195 u16 fid:3;
196 u16 untag:6;
197 u16 member:6;
198 };
199
200 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
201 u16 g_dbg_reg;
202 #endif
203
204 struct mib_counter {
205 unsigned base;
206 unsigned offset;
207 unsigned length;
208 const char *name;
209 };
210
211 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
212 { 0, 0, 4, "IfInOctets" },
213 { 0, 4, 4, "EtherStatsOctets" },
214 { 0, 8, 2, "EtherStatsUnderSizePkts" },
215 { 0, 10, 2, "EtherFragments" },
216 { 0, 12, 2, "EtherStatsPkts64Octets" },
217 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
218 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
219 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
220 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
221 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
222 { 0, 24, 2, "EtherOversizeStats" },
223 { 0, 26, 2, "EtherStatsJabbers" },
224 { 0, 28, 2, "IfInUcastPkts" },
225 { 0, 30, 2, "EtherStatsMulticastPkts" },
226 { 0, 32, 2, "EtherStatsBroadcastPkts" },
227 { 0, 34, 2, "EtherStatsDropEvents" },
228 { 0, 36, 2, "Dot3StatsFCSErrors" },
229 { 0, 38, 2, "Dot3StatsSymbolErrors" },
230 { 0, 40, 2, "Dot3InPauseFrames" },
231 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
232 { 0, 44, 4, "IfOutOctets" },
233 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
234 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
235 { 0, 52, 2, "Dot3sDeferredTransmissions" },
236 { 0, 54, 2, "Dot3StatsLateCollisions" },
237 { 0, 56, 2, "EtherStatsCollisions" },
238 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
239 { 0, 60, 2, "Dot3OutPauseFrames" },
240 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
241
242 /*
243 * The following counters are accessible at a different
244 * base address.
245 */
246 { 1, 0, 2, "Dot1dTpPortInDiscards" },
247 { 1, 2, 2, "IfOutUcastPkts" },
248 { 1, 4, 2, "IfOutMulticastPkts" },
249 { 1, 6, 2, "IfOutBroadcastPkts" },
250 };
251
252 #define REG_WR(_smi, _reg, _val) \
253 do { \
254 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
255 if (err) \
256 return err; \
257 } while (0)
258
259 #define REG_RMW(_smi, _reg, _mask, _val) \
260 do { \
261 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
262 if (err) \
263 return err; \
264 } while (0)
265
266 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
267 {
268 return container_of(smi, struct rtl8366s, smi);
269 }
270
271 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
272 {
273 return container_of(sw, struct rtl8366s, dev);
274 }
275
276 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
277 {
278 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
279 return &rtl->smi;
280 }
281
282 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
283 {
284 int timeout = 10;
285 u32 data;
286
287 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
288 RTL8366_CHIP_CTRL_RESET_HW);
289 do {
290 msleep(1);
291 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
292 return -EIO;
293
294 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
295 break;
296 } while (--timeout);
297
298 if (!timeout) {
299 printk("Timeout waiting for the switch to reset\n");
300 return -EIO;
301 }
302
303 return 0;
304 }
305
306 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
307 {
308 int err;
309
310 /* set maximum packet length to 1536 bytes */
311 REG_RMW(smi, RTL8366_SGCR, RTL8366_SGCR_MAX_LENGTH_MASK,
312 RTL8366_SGCR_MAX_LENGTH_1536);
313
314 /* enable all ports */
315 REG_WR(smi, RTL8366_PECR, 0);
316
317 /* disable learning for all ports */
318 REG_WR(smi, RTL8366_SSCR0, RTL8366_PORT_ALL);
319
320 /* disable auto ageing for all ports */
321 REG_WR(smi, RTL8366_SSCR1, RTL8366_PORT_ALL);
322
323 /* don't drop packets whose DA has not been learned */
324 REG_RMW(smi, RTL8366_SSCR2, RTL8366_SSCR2_DROP_UNKNOWN_DA, 0);
325
326 return 0;
327 }
328
329 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
330 u32 phy_no, u32 page, u32 addr, u32 *data)
331 {
332 u32 reg;
333 int ret;
334
335 if (phy_no > RTL8366S_PHY_NO_MAX)
336 return -EINVAL;
337
338 if (page > RTL8366S_PHY_PAGE_MAX)
339 return -EINVAL;
340
341 if (addr > RTL8366S_PHY_ADDR_MAX)
342 return -EINVAL;
343
344 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
345 RTL8366S_PHY_CTRL_READ);
346 if (ret)
347 return ret;
348
349 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
350 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
351 (addr & RTL8366S_PHY_REG_MASK);
352
353 ret = rtl8366_smi_write_reg(smi, reg, 0);
354 if (ret)
355 return ret;
356
357 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
358 if (ret)
359 return ret;
360
361 return 0;
362 }
363
364 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
365 u32 phy_no, u32 page, u32 addr, u32 data)
366 {
367 u32 reg;
368 int ret;
369
370 if (phy_no > RTL8366S_PHY_NO_MAX)
371 return -EINVAL;
372
373 if (page > RTL8366S_PHY_PAGE_MAX)
374 return -EINVAL;
375
376 if (addr > RTL8366S_PHY_ADDR_MAX)
377 return -EINVAL;
378
379 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
380 RTL8366S_PHY_CTRL_WRITE);
381 if (ret)
382 return ret;
383
384 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
385 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
386 (addr & RTL8366S_PHY_REG_MASK);
387
388 ret = rtl8366_smi_write_reg(smi, reg, data);
389 if (ret)
390 return ret;
391
392 return 0;
393 }
394
395 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
396 int port, unsigned long long *val)
397 {
398 int i;
399 int err;
400 u32 addr, data;
401 u64 mibvalue;
402
403 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
404 return -EINVAL;
405
406 switch (rtl8366s_mib_counters[counter].base) {
407 case 0:
408 addr = RTL8366S_MIB_COUNTER_BASE +
409 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
410 break;
411
412 case 1:
413 addr = RTL8366S_MIB_COUNTER_BASE2 +
414 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 addr += rtl8366s_mib_counters[counter].offset;
422
423 /*
424 * Writing access counter address first
425 * then ASIC will prepare 64bits counter wait for being retrived
426 */
427 data = 0; /* writing data will be discard by ASIC */
428 err = rtl8366_smi_write_reg(smi, addr, data);
429 if (err)
430 return err;
431
432 /* read MIB control register */
433 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
434 if (err)
435 return err;
436
437 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
438 return -EBUSY;
439
440 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
441 return -EIO;
442
443 mibvalue = 0;
444 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
445 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
446 if (err)
447 return err;
448
449 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
450 }
451
452 *val = mibvalue;
453 return 0;
454 }
455
456 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
457 struct rtl8366_vlan_4k *vlan4k)
458 {
459 struct rtl8366s_vlan_4k vlan4k_priv;
460 int err;
461 u32 data;
462 u16 *tableaddr;
463
464 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
465 vlan4k_priv.vid = vid;
466
467 if (vid >= RTL8366_NUM_VIDS)
468 return -EINVAL;
469
470 tableaddr = (u16 *)&vlan4k_priv;
471
472 /* write VID */
473 data = *tableaddr;
474 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
475 if (err)
476 return err;
477
478 /* write table access control word */
479 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
480 RTL8366S_TABLE_VLAN_READ_CTRL);
481 if (err)
482 return err;
483
484 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
485 if (err)
486 return err;
487
488 *tableaddr = data;
489 tableaddr++;
490
491 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
492 &data);
493 if (err)
494 return err;
495
496 *tableaddr = data;
497
498 vlan4k->vid = vid;
499 vlan4k->untag = vlan4k_priv.untag;
500 vlan4k->member = vlan4k_priv.member;
501 vlan4k->fid = vlan4k_priv.fid;
502
503 return 0;
504 }
505
506 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
507 const struct rtl8366_vlan_4k *vlan4k)
508 {
509 struct rtl8366s_vlan_4k vlan4k_priv;
510 int err;
511 u32 data;
512 u16 *tableaddr;
513
514 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
515 vlan4k->member > RTL8366_PORT_ALL ||
516 vlan4k->untag > RTL8366_PORT_ALL ||
517 vlan4k->fid > RTL8366S_FIDMAX)
518 return -EINVAL;
519
520 vlan4k_priv.vid = vlan4k->vid;
521 vlan4k_priv.untag = vlan4k->untag;
522 vlan4k_priv.member = vlan4k->member;
523 vlan4k_priv.fid = vlan4k->fid;
524
525 tableaddr = (u16 *)&vlan4k_priv;
526
527 data = *tableaddr;
528
529 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
530 if (err)
531 return err;
532
533 tableaddr++;
534
535 data = *tableaddr;
536
537 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
538 data);
539 if (err)
540 return err;
541
542 /* write table access control word */
543 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
544 RTL8366S_TABLE_VLAN_WRITE_CTRL);
545
546 return err;
547 }
548
549 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
550 struct rtl8366_vlan_mc *vlanmc)
551 {
552 struct rtl8366s_vlan_mc vlanmc_priv;
553 int err;
554 u32 addr;
555 u32 data;
556 u16 *tableaddr;
557
558 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
559
560 if (index >= RTL8366_NUM_VLANS)
561 return -EINVAL;
562
563 tableaddr = (u16 *)&vlanmc_priv;
564
565 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
566 err = rtl8366_smi_read_reg(smi, addr, &data);
567 if (err)
568 return err;
569
570 *tableaddr = data;
571 tableaddr++;
572
573 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
574 err = rtl8366_smi_read_reg(smi, addr, &data);
575 if (err)
576 return err;
577
578 *tableaddr = data;
579
580 vlanmc->vid = vlanmc_priv.vid;
581 vlanmc->priority = vlanmc_priv.priority;
582 vlanmc->untag = vlanmc_priv.untag;
583 vlanmc->member = vlanmc_priv.member;
584 vlanmc->fid = vlanmc_priv.fid;
585
586 return 0;
587 }
588
589 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
590 const struct rtl8366_vlan_mc *vlanmc)
591 {
592 struct rtl8366s_vlan_mc vlanmc_priv;
593 int err;
594 u32 addr;
595 u32 data;
596 u16 *tableaddr;
597
598 if (index >= RTL8366_NUM_VLANS ||
599 vlanmc->vid >= RTL8366_NUM_VIDS ||
600 vlanmc->priority > RTL8366S_PRIORITYMAX ||
601 vlanmc->member > RTL8366_PORT_ALL ||
602 vlanmc->untag > RTL8366_PORT_ALL ||
603 vlanmc->fid > RTL8366S_FIDMAX)
604 return -EINVAL;
605
606 vlanmc_priv.vid = vlanmc->vid;
607 vlanmc_priv.priority = vlanmc->priority;
608 vlanmc_priv.untag = vlanmc->untag;
609 vlanmc_priv.member = vlanmc->member;
610 vlanmc_priv.fid = vlanmc->fid;
611
612 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
613
614 tableaddr = (u16 *)&vlanmc_priv;
615 data = *tableaddr;
616
617 err = rtl8366_smi_write_reg(smi, addr, data);
618 if (err)
619 return err;
620
621 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
622
623 tableaddr++;
624 data = *tableaddr;
625
626 err = rtl8366_smi_write_reg(smi, addr, data);
627 if (err)
628 return err;
629
630 return 0;
631 }
632
633 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
634 {
635 u32 data;
636 int err;
637
638 if (port >= RTL8366_NUM_PORTS)
639 return -EINVAL;
640
641 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
642 &data);
643 if (err)
644 return err;
645
646 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
647 RTL8366S_PORT_VLAN_CTRL_MASK;
648
649 return 0;
650 }
651
652 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
653 {
654 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
655 return -EINVAL;
656
657 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
658 RTL8366S_PORT_VLAN_CTRL_MASK <<
659 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
660 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
661 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
662 }
663
664 static int rtl8366s_set_vlan(struct rtl8366_smi *smi, int vid, u32 member,
665 u32 untag, u32 fid)
666 {
667 struct rtl8366_vlan_4k vlan4k;
668 int err;
669 int i;
670
671 /* Update the 4K table */
672 err = rtl8366s_get_vlan_4k(smi, vid, &vlan4k);
673 if (err)
674 return err;
675
676 vlan4k.member = member;
677 vlan4k.untag = untag;
678 vlan4k.fid = fid;
679 err = rtl8366s_set_vlan_4k(smi, &vlan4k);
680 if (err)
681 return err;
682
683 /* Try to find an existing MC entry for this VID */
684 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
685 struct rtl8366_vlan_mc vlanmc;
686
687 err = rtl8366s_get_vlan_mc(smi, i, &vlanmc);
688 if (err)
689 return err;
690
691 if (vid == vlanmc.vid) {
692 /* update the MC entry */
693 vlanmc.member = member;
694 vlanmc.untag = untag;
695 vlanmc.fid = fid;
696
697 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
698 break;
699 }
700 }
701
702 return err;
703 }
704
705 static int rtl8366s_get_pvid(struct rtl8366_smi *smi, int port, int *val)
706 {
707 struct rtl8366_vlan_mc vlanmc;
708 int err;
709 int index;
710
711 err = rtl8366s_get_mc_index(smi, port, &index);
712 if (err)
713 return err;
714
715 err = rtl8366s_get_vlan_mc(smi, index, &vlanmc);
716 if (err)
717 return err;
718
719 *val = vlanmc.vid;
720 return 0;
721 }
722
723 static int rtl8366s_mc_is_used(struct rtl8366_smi *smi, int mc_index,
724 int *used)
725 {
726 int err;
727 int i;
728
729 *used = 0;
730 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
731 int index = 0;
732
733 err = rtl8366s_get_mc_index(smi, i, &index);
734 if (err)
735 return err;
736
737 if (mc_index == index) {
738 *used = 1;
739 break;
740 }
741 }
742
743 return 0;
744 }
745
746 static int rtl8366s_set_pvid(struct rtl8366_smi *smi, unsigned port,
747 unsigned vid)
748 {
749 struct rtl8366_vlan_mc vlanmc;
750 struct rtl8366_vlan_4k vlan4k;
751 int err;
752 int i;
753
754 /* Try to find an existing MC entry for this VID */
755 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
756 err = rtl8366s_get_vlan_mc(smi, i, &vlanmc);
757 if (err)
758 return err;
759
760 if (vid == vlanmc.vid) {
761 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
762 if (err)
763 return err;
764
765 err = rtl8366s_set_mc_index(smi, port, i);
766 return err;
767 }
768 }
769
770 /* We have no MC entry for this VID, try to find an empty one */
771 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
772 err = rtl8366s_get_vlan_mc(smi, i, &vlanmc);
773 if (err)
774 return err;
775
776 if (vlanmc.vid == 0 && vlanmc.member == 0) {
777 /* Update the entry from the 4K table */
778 err = rtl8366s_get_vlan_4k(smi, vid, &vlan4k);
779 if (err)
780 return err;
781
782 vlanmc.vid = vid;
783 vlanmc.member = vlan4k.member;
784 vlanmc.untag = vlan4k.untag;
785 vlanmc.fid = vlan4k.fid;
786 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
787 if (err)
788 return err;
789
790 err = rtl8366s_set_mc_index(smi, port, i);
791 return err;
792 }
793 }
794
795 /* MC table is full, try to find an unused entry and replace it */
796 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
797 int used;
798
799 err = rtl8366s_mc_is_used(smi, i, &used);
800 if (err)
801 return err;
802
803 if (!used) {
804 /* Update the entry from the 4K table */
805 err = rtl8366s_get_vlan_4k(smi, vid, &vlan4k);
806 if (err)
807 return err;
808
809 vlanmc.vid = vid;
810 vlanmc.member = vlan4k.member;
811 vlanmc.untag = vlan4k.untag;
812 vlanmc.fid = vlan4k.fid;
813 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
814 if (err)
815 return err;
816
817 err = rtl8366s_set_mc_index(smi, port, i);
818 return err;
819 }
820 }
821
822 dev_err(smi->parent,
823 "all VLAN member configurations are in use\n");
824
825 return -ENOSPC;
826 }
827
828 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
829 {
830 return rtl8366_smi_rmwr(smi, RTL8366_CHIP_GLOBAL_CTRL_REG,
831 RTL8366_CHIP_CTRL_VLAN,
832 (enable) ? RTL8366_CHIP_CTRL_VLAN : 0);
833 }
834
835 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
836 {
837 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
838 1, (enable) ? 1 : 0);
839 }
840
841 static int rtl8366s_reset_vlan(struct rtl8366_smi *smi)
842 {
843 struct rtl8366_vlan_mc vlanmc;
844 int err;
845 int i;
846
847 /* clear VLAN member configurations */
848 vlanmc.vid = 0;
849 vlanmc.priority = 0;
850 vlanmc.member = 0;
851 vlanmc.untag = 0;
852 vlanmc.fid = 0;
853 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
854 err = rtl8366s_set_vlan_mc(smi, i, &vlanmc);
855 if (err)
856 return err;
857 }
858
859 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
860 if (i == RTL8366_PORT_CPU)
861 continue;
862
863 err = rtl8366s_set_vlan(smi, (i + 1),
864 (1 << i) | RTL8366_PORT_CPU,
865 (1 << i) | RTL8366_PORT_CPU,
866 0);
867 if (err)
868 return err;
869
870 err = rtl8366s_set_pvid(smi, i, (i + 1));
871 if (err)
872 return err;
873 }
874
875 return 0;
876 }
877
878 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
879 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
880 {
881 file->private_data = inode->i_private;
882 return 0;
883 }
884
885 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
886 char __user *user_buf,
887 size_t count, loff_t *ppos)
888 {
889 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
890 struct rtl8366_smi *smi = &rtl->smi;
891 int i, j, len = 0;
892 char *buf = rtl->buf;
893
894 len += snprintf(buf + len, sizeof(rtl->buf) - len,
895 "%-36s %12s %12s %12s %12s %12s %12s\n",
896 "Counter",
897 "Port 0", "Port 1", "Port 2",
898 "Port 3", "Port 4", "Port 5");
899
900 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
901 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
902 rtl8366s_mib_counters[i].name);
903 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
904 unsigned long long counter = 0;
905
906 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
907 len += snprintf(buf + len,
908 sizeof(rtl->buf) - len,
909 "%12llu ", counter);
910 else
911 len += snprintf(buf + len,
912 sizeof(rtl->buf) - len,
913 "%12s ", "error");
914 }
915 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
916 }
917
918 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
919 }
920
921 static ssize_t rtl8366s_read_debugfs_vlan_mc(struct file *file,
922 char __user *user_buf,
923 size_t count, loff_t *ppos)
924 {
925 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
926 struct rtl8366_smi *smi = &rtl->smi;
927 int i, len = 0;
928 char *buf = rtl->buf;
929
930 len += snprintf(buf + len, sizeof(rtl->buf) - len,
931 "%2s %6s %4s %6s %6s %3s\n",
932 "id", "vid","prio", "member", "untag", "fid");
933
934 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
935 struct rtl8366_vlan_mc vlanmc;
936
937 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
938
939 len += snprintf(buf + len, sizeof(rtl->buf) - len,
940 "%2d %6d %4d 0x%04x 0x%04x %3d\n",
941 i, vlanmc.vid, vlanmc.priority,
942 vlanmc.member, vlanmc.untag, vlanmc.fid);
943 }
944
945 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
946 }
947
948 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
949 char __user *user_buf,
950 size_t count, loff_t *ppos)
951 {
952 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
953 struct rtl8366_smi *smi = &rtl->smi;
954 u32 t, reg = g_dbg_reg;
955 int err, len = 0;
956 char *buf = rtl->buf;
957
958 memset(buf, '\0', sizeof(rtl->buf));
959
960 err = rtl8366_smi_read_reg(smi, reg, &t);
961 if (err) {
962 len += snprintf(buf, sizeof(rtl->buf),
963 "Read failed (reg: 0x%04x)\n", reg);
964 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
965 }
966
967 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
968 reg, t);
969
970 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
971 }
972
973 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
974 const char __user *user_buf,
975 size_t count, loff_t *ppos)
976 {
977 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
978 struct rtl8366_smi *smi = &rtl->smi;
979 unsigned long data;
980 u32 reg = g_dbg_reg;
981 int err;
982 size_t len;
983 char *buf = rtl->buf;
984
985 len = min(count, sizeof(rtl->buf) - 1);
986 if (copy_from_user(buf, user_buf, len)) {
987 dev_err(rtl->parent, "copy from user failed\n");
988 return -EFAULT;
989 }
990
991 buf[len] = '\0';
992 if (len > 0 && buf[len - 1] == '\n')
993 buf[len - 1] = '\0';
994
995
996 if (strict_strtoul(buf, 16, &data)) {
997 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
998 } else {
999 err = rtl8366_smi_write_reg(smi, reg, data);
1000 if (err) {
1001 dev_err(rtl->parent,
1002 "writing reg 0x%04x val 0x%04lx failed\n",
1003 reg, data);
1004 }
1005 }
1006
1007 return count;
1008 }
1009
1010 static const struct file_operations fops_rtl8366s_regs = {
1011 .read = rtl8366s_read_debugfs_reg,
1012 .write = rtl8366s_write_debugfs_reg,
1013 .open = rtl8366s_debugfs_open,
1014 .owner = THIS_MODULE
1015 };
1016
1017 static const struct file_operations fops_rtl8366s_vlan_mc = {
1018 .read = rtl8366s_read_debugfs_vlan_mc,
1019 .open = rtl8366s_debugfs_open,
1020 .owner = THIS_MODULE
1021 };
1022
1023 static const struct file_operations fops_rtl8366s_mibs = {
1024 .read = rtl8366s_read_debugfs_mibs,
1025 .open = rtl8366s_debugfs_open,
1026 .owner = THIS_MODULE
1027 };
1028
1029 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
1030 {
1031 struct dentry *node;
1032 struct dentry *root;
1033
1034 if (!rtl->debugfs_root)
1035 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
1036
1037 if (!rtl->debugfs_root) {
1038 dev_err(rtl->parent, "Unable to create debugfs dir\n");
1039 return;
1040 }
1041 root = rtl->debugfs_root;
1042
1043 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
1044 if (!node) {
1045 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1046 "reg");
1047 return;
1048 }
1049
1050 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
1051 &fops_rtl8366s_regs);
1052 if (!node) {
1053 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1054 "val");
1055 return;
1056 }
1057
1058 node = debugfs_create_file("vlan_mc", S_IRUSR, root, rtl,
1059 &fops_rtl8366s_vlan_mc);
1060 if (!node) {
1061 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1062 "vlan_mc");
1063 return;
1064 }
1065
1066 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
1067 &fops_rtl8366s_mibs);
1068 if (!node) {
1069 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
1070 "mibs");
1071 return;
1072 }
1073 }
1074
1075 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
1076 {
1077 if (rtl->debugfs_root) {
1078 debugfs_remove_recursive(rtl->debugfs_root);
1079 rtl->debugfs_root = NULL;
1080 }
1081 }
1082
1083 #else
1084 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
1085 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
1086 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
1087
1088 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
1089 const struct switch_attr *attr,
1090 struct switch_val *val)
1091 {
1092 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1093 int err = 0;
1094
1095 if (val->value.i == 1)
1096 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
1097
1098 return err;
1099 }
1100
1101 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
1102 const struct switch_attr *attr,
1103 struct switch_val *val)
1104 {
1105 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1106 u32 data;
1107
1108 if (attr->ofs == 1) {
1109 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
1110
1111 if (data & RTL8366_CHIP_CTRL_VLAN)
1112 val->value.i = 1;
1113 else
1114 val->value.i = 0;
1115 } else if (attr->ofs == 2) {
1116 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1117
1118 if (data & 0x0001)
1119 val->value.i = 1;
1120 else
1121 val->value.i = 0;
1122 }
1123
1124 return 0;
1125 }
1126
1127 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1128 const struct switch_attr *attr,
1129 struct switch_val *val)
1130 {
1131 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1132 u32 data;
1133
1134 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1135
1136 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1137
1138 return 0;
1139 }
1140
1141 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1142 const struct switch_attr *attr,
1143 struct switch_val *val)
1144 {
1145 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1146
1147 if (val->value.i >= 6)
1148 return -EINVAL;
1149
1150 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG,
1151 RTL8366_LED_BLINKRATE_MASK,
1152 val->value.i);
1153 }
1154
1155 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1156 const struct switch_attr *attr,
1157 struct switch_val *val)
1158 {
1159 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1160
1161 if (attr->ofs == 1)
1162 return rtl8366s_vlan_set_vlan(smi, val->value.i);
1163 else
1164 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
1165 }
1166
1167 static const char *rtl8366s_speed_str(unsigned speed)
1168 {
1169 switch (speed) {
1170 case 0:
1171 return "10baseT";
1172 case 1:
1173 return "100baseT";
1174 case 2:
1175 return "1000baseT";
1176 }
1177
1178 return "unknown";
1179 }
1180
1181 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1182 const struct switch_attr *attr,
1183 struct switch_val *val)
1184 {
1185 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1186 struct rtl8366_smi *smi = &rtl->smi;
1187 u32 len = 0, data = 0;
1188
1189 if (val->port_vlan >= RTL8366_NUM_PORTS)
1190 return -EINVAL;
1191
1192 memset(rtl->buf, '\0', sizeof(rtl->buf));
1193 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1194 (val->port_vlan / 2), &data);
1195
1196 if (val->port_vlan % 2)
1197 data = data >> 8;
1198
1199 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1200 len = snprintf(rtl->buf, sizeof(rtl->buf),
1201 "port:%d link:up speed:%s %s-duplex %s%s%s",
1202 val->port_vlan,
1203 rtl8366s_speed_str(data &
1204 RTL8366S_PORT_STATUS_SPEED_MASK),
1205 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1206 "full" : "half",
1207 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1208 "tx-pause ": "",
1209 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1210 "rx-pause " : "",
1211 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1212 "nway ": "");
1213 } else {
1214 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1215 val->port_vlan);
1216 }
1217
1218 val->value.s = rtl->buf;
1219 val->len = len;
1220
1221 return 0;
1222 }
1223
1224 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1225 const struct switch_attr *attr,
1226 struct switch_val *val)
1227 {
1228 int i;
1229 u32 len = 0;
1230 struct rtl8366_vlan_4k vlan4k;
1231 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1232 struct rtl8366_smi *smi = &rtl->smi;
1233 char *buf = rtl->buf;
1234 int err;
1235
1236 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1237 return -EINVAL;
1238
1239 memset(buf, '\0', sizeof(rtl->buf));
1240
1241 err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1242 if (err)
1243 return err;
1244
1245 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1246 "VLAN %d: Ports: '", vlan4k.vid);
1247
1248 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1249 if (!(vlan4k.member & (1 << i)))
1250 continue;
1251
1252 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d%s", i,
1253 (vlan4k.untag & (1 << i)) ? "" : "t");
1254 }
1255
1256 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1257 "', members=%04x, untag=%04x, fid=%u",
1258 vlan4k.member, vlan4k.untag, vlan4k.fid);
1259
1260 val->value.s = buf;
1261 val->len = len;
1262
1263 return 0;
1264 }
1265
1266 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1267 const struct switch_attr *attr,
1268 struct switch_val *val)
1269 {
1270 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1271 u32 data;
1272 u32 mask;
1273 u32 reg;
1274
1275 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1276 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1277 return -EINVAL;
1278
1279 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1280 reg = RTL8366_LED_BLINKRATE_REG;
1281 mask = 0xF << 4;
1282 data = val->value.i << 4;
1283 } else {
1284 reg = RTL8366_LED_CTRL_REG;
1285 mask = 0xF << (val->port_vlan * 4),
1286 data = val->value.i << (val->port_vlan * 4);
1287 }
1288
1289 return rtl8366_smi_rmwr(smi, RTL8366_LED_BLINKRATE_REG, mask, data);
1290 }
1291
1292 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1293 const struct switch_attr *attr,
1294 struct switch_val *val)
1295 {
1296 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1297 u32 data = 0;
1298
1299 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1300 return -EINVAL;
1301
1302 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1303 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1304
1305 return 0;
1306 }
1307
1308 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1309 const struct switch_attr *attr,
1310 struct switch_val *val)
1311 {
1312 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1313
1314 if (val->port_vlan >= RTL8366_NUM_PORTS)
1315 return -EINVAL;
1316
1317
1318 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
1319 0, (1 << (val->port_vlan + 3)));
1320 }
1321
1322 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1323 const struct switch_attr *attr,
1324 struct switch_val *val)
1325 {
1326 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1327 struct rtl8366_smi *smi = &rtl->smi;
1328 int i, len = 0;
1329 unsigned long long counter = 0;
1330 char *buf = rtl->buf;
1331
1332 if (val->port_vlan >= RTL8366_NUM_PORTS)
1333 return -EINVAL;
1334
1335 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1336 "Port %d MIB counters\n",
1337 val->port_vlan);
1338
1339 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
1340 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1341 "%-36s: ", rtl8366s_mib_counters[i].name);
1342 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1343 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1344 "%llu\n", counter);
1345 else
1346 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1347 "%s\n", "error");
1348 }
1349
1350 val->value.s = buf;
1351 val->len = len;
1352 return 0;
1353 }
1354
1355 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1356 struct switch_val *val)
1357 {
1358 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1359 struct switch_port *port;
1360 struct rtl8366_vlan_4k vlan4k;
1361 int i;
1362
1363 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1364 return -EINVAL;
1365
1366 rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1367
1368 port = &val->value.ports[0];
1369 val->len = 0;
1370 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1371 if (!(vlan4k.member & BIT(i)))
1372 continue;
1373
1374 port->id = i;
1375 port->flags = (vlan4k.untag & BIT(i)) ?
1376 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1377 val->len++;
1378 port++;
1379 }
1380 return 0;
1381 }
1382
1383 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1384 struct switch_val *val)
1385 {
1386 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1387 struct switch_port *port;
1388 u32 member = 0;
1389 u32 untag = 0;
1390 int i;
1391
1392 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1393 return -EINVAL;
1394
1395 port = &val->value.ports[0];
1396 for (i = 0; i < val->len; i++, port++) {
1397 member |= BIT(port->id);
1398
1399 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1400 untag |= BIT(port->id);
1401 }
1402
1403 return rtl8366s_set_vlan(smi, val->port_vlan, member, untag, 0);
1404 }
1405
1406 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1407 {
1408 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1409 return rtl8366s_get_pvid(smi, port, val);
1410 }
1411
1412 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1413 {
1414 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1415 return rtl8366s_set_pvid(smi, port, val);
1416 }
1417
1418 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1419 {
1420 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1421 int err;
1422
1423 err = rtl8366s_reset_chip(smi);
1424 if (err)
1425 return err;
1426
1427 err = rtl8366s_hw_init(smi);
1428 if (err)
1429 return err;
1430
1431 return rtl8366s_reset_vlan(smi);
1432 }
1433
1434 static struct switch_attr rtl8366s_globals[] = {
1435 {
1436 .type = SWITCH_TYPE_INT,
1437 .name = "enable_vlan",
1438 .description = "Enable VLAN mode",
1439 .set = rtl8366s_sw_set_vlan_enable,
1440 .get = rtl8366s_sw_get_vlan_enable,
1441 .max = 1,
1442 .ofs = 1
1443 }, {
1444 .type = SWITCH_TYPE_INT,
1445 .name = "enable_vlan4k",
1446 .description = "Enable VLAN 4K mode",
1447 .set = rtl8366s_sw_set_vlan_enable,
1448 .get = rtl8366s_sw_get_vlan_enable,
1449 .max = 1,
1450 .ofs = 2
1451 }, {
1452 .type = SWITCH_TYPE_INT,
1453 .name = "reset_mibs",
1454 .description = "Reset all MIB counters",
1455 .set = rtl8366s_sw_reset_mibs,
1456 .get = NULL,
1457 .max = 1
1458 }, {
1459 .type = SWITCH_TYPE_INT,
1460 .name = "blinkrate",
1461 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1462 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1463 .set = rtl8366s_sw_set_blinkrate,
1464 .get = rtl8366s_sw_get_blinkrate,
1465 .max = 5
1466 },
1467 };
1468
1469 static struct switch_attr rtl8366s_port[] = {
1470 {
1471 .type = SWITCH_TYPE_STRING,
1472 .name = "link",
1473 .description = "Get port link information",
1474 .max = 1,
1475 .set = NULL,
1476 .get = rtl8366s_sw_get_port_link,
1477 }, {
1478 .type = SWITCH_TYPE_INT,
1479 .name = "reset_mib",
1480 .description = "Reset single port MIB counters",
1481 .max = 1,
1482 .set = rtl8366s_sw_reset_port_mibs,
1483 .get = NULL,
1484 }, {
1485 .type = SWITCH_TYPE_STRING,
1486 .name = "mib",
1487 .description = "Get MIB counters for port",
1488 .max = 33,
1489 .set = NULL,
1490 .get = rtl8366s_sw_get_port_mib,
1491 }, {
1492 .type = SWITCH_TYPE_INT,
1493 .name = "led",
1494 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1495 .max = 15,
1496 .set = rtl8366s_sw_set_port_led,
1497 .get = rtl8366s_sw_get_port_led,
1498 },
1499 };
1500
1501 static struct switch_attr rtl8366s_vlan[] = {
1502 {
1503 .type = SWITCH_TYPE_STRING,
1504 .name = "info",
1505 .description = "Get vlan information",
1506 .max = 1,
1507 .set = NULL,
1508 .get = rtl8366s_sw_get_vlan_info,
1509 },
1510 };
1511
1512 /* template */
1513 static struct switch_dev rtl8366_switch_dev = {
1514 .name = "RTL8366S",
1515 .cpu_port = RTL8366_PORT_NUM_CPU,
1516 .ports = RTL8366_NUM_PORTS,
1517 .vlans = RTL8366_NUM_VLANS,
1518 .attr_global = {
1519 .attr = rtl8366s_globals,
1520 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1521 },
1522 .attr_port = {
1523 .attr = rtl8366s_port,
1524 .n_attr = ARRAY_SIZE(rtl8366s_port),
1525 },
1526 .attr_vlan = {
1527 .attr = rtl8366s_vlan,
1528 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1529 },
1530
1531 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1532 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1533 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1534 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1535 .reset_switch = rtl8366s_sw_reset_switch,
1536 };
1537
1538 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1539 {
1540 struct switch_dev *dev = &rtl->dev;
1541 int err;
1542
1543 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1544 dev->priv = rtl;
1545 dev->devname = dev_name(rtl->parent);
1546
1547 err = register_switch(dev, NULL);
1548 if (err)
1549 dev_err(rtl->parent, "switch registration failed\n");
1550
1551 return err;
1552 }
1553
1554 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1555 {
1556 unregister_switch(&rtl->dev);
1557 }
1558
1559 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1560 {
1561 struct rtl8366_smi *smi = bus->priv;
1562 u32 val = 0;
1563 int err;
1564
1565 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1566 if (err)
1567 return 0xffff;
1568
1569 return val;
1570 }
1571
1572 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1573 {
1574 struct rtl8366_smi *smi = bus->priv;
1575 u32 t;
1576 int err;
1577
1578 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1579 /* flush write */
1580 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1581
1582 return err;
1583 }
1584
1585 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1586 {
1587 return (bus->read == rtl8366s_mii_read &&
1588 bus->write == rtl8366s_mii_write);
1589 }
1590
1591 static int rtl8366s_setup(struct rtl8366s *rtl)
1592 {
1593 struct rtl8366_smi *smi = &rtl->smi;
1594 int ret;
1595
1596 rtl8366s_debugfs_init(rtl);
1597
1598 ret = rtl8366s_reset_chip(smi);
1599 if (ret)
1600 return ret;
1601
1602 ret = rtl8366s_hw_init(smi);
1603 return ret;
1604 }
1605
1606 static int rtl8366s_detect(struct rtl8366_smi *smi)
1607 {
1608 u32 chip_id = 0;
1609 u32 chip_ver = 0;
1610 int ret;
1611
1612 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1613 if (ret) {
1614 dev_err(smi->parent, "unable to read chip id\n");
1615 return ret;
1616 }
1617
1618 switch (chip_id) {
1619 case RTL8366S_CHIP_ID_8366:
1620 break;
1621 default:
1622 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1623 return -ENODEV;
1624 }
1625
1626 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1627 &chip_ver);
1628 if (ret) {
1629 dev_err(smi->parent, "unable to read chip version\n");
1630 return ret;
1631 }
1632
1633 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1634 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1635
1636 return 0;
1637 }
1638
1639 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1640 .detect = rtl8366s_detect,
1641 .mii_read = rtl8366s_mii_read,
1642 .mii_write = rtl8366s_mii_write,
1643 };
1644
1645 static int __init rtl8366s_probe(struct platform_device *pdev)
1646 {
1647 static int rtl8366_smi_version_printed;
1648 struct rtl8366s_platform_data *pdata;
1649 struct rtl8366s *rtl;
1650 struct rtl8366_smi *smi;
1651 int err;
1652
1653 if (!rtl8366_smi_version_printed++)
1654 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1655 " version " RTL8366S_DRIVER_VER"\n");
1656
1657 pdata = pdev->dev.platform_data;
1658 if (!pdata) {
1659 dev_err(&pdev->dev, "no platform data specified\n");
1660 err = -EINVAL;
1661 goto err_out;
1662 }
1663
1664 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1665 if (!rtl) {
1666 dev_err(&pdev->dev, "no memory for private data\n");
1667 err = -ENOMEM;
1668 goto err_out;
1669 }
1670
1671 rtl->parent = &pdev->dev;
1672
1673 smi = &rtl->smi;
1674 smi->parent = &pdev->dev;
1675 smi->gpio_sda = pdata->gpio_sda;
1676 smi->gpio_sck = pdata->gpio_sck;
1677 smi->ops = &rtl8366s_smi_ops;
1678
1679 err = rtl8366_smi_init(smi);
1680 if (err)
1681 goto err_free_rtl;
1682
1683 platform_set_drvdata(pdev, rtl);
1684
1685 err = rtl8366s_setup(rtl);
1686 if (err)
1687 goto err_clear_drvdata;
1688
1689 err = rtl8366s_switch_init(rtl);
1690 if (err)
1691 goto err_clear_drvdata;
1692
1693 return 0;
1694
1695 err_clear_drvdata:
1696 platform_set_drvdata(pdev, NULL);
1697 rtl8366_smi_cleanup(smi);
1698 err_free_rtl:
1699 kfree(rtl);
1700 err_out:
1701 return err;
1702 }
1703
1704 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1705 {
1706 if (!rtl8366s_mii_bus_match(phydev->bus))
1707 return -EINVAL;
1708
1709 return 0;
1710 }
1711
1712 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1713 {
1714 return 0;
1715 }
1716
1717 static struct phy_driver rtl8366s_phy_driver = {
1718 .phy_id = 0x001cc960,
1719 .name = "Realtek RTL8366S",
1720 .phy_id_mask = 0x1ffffff0,
1721 .features = PHY_GBIT_FEATURES,
1722 .config_aneg = rtl8366s_phy_config_aneg,
1723 .config_init = rtl8366s_phy_config_init,
1724 .read_status = genphy_read_status,
1725 .driver = {
1726 .owner = THIS_MODULE,
1727 },
1728 };
1729
1730 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1731 {
1732 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1733
1734 if (rtl) {
1735 rtl8366s_switch_cleanup(rtl);
1736 rtl8366s_debugfs_remove(rtl);
1737 platform_set_drvdata(pdev, NULL);
1738 rtl8366_smi_cleanup(&rtl->smi);
1739 kfree(rtl);
1740 }
1741
1742 return 0;
1743 }
1744
1745 static struct platform_driver rtl8366s_driver = {
1746 .driver = {
1747 .name = RTL8366S_DRIVER_NAME,
1748 .owner = THIS_MODULE,
1749 },
1750 .probe = rtl8366s_probe,
1751 .remove = __devexit_p(rtl8366s_remove),
1752 };
1753
1754 static int __init rtl8366s_module_init(void)
1755 {
1756 int ret;
1757 ret = platform_driver_register(&rtl8366s_driver);
1758 if (ret)
1759 return ret;
1760
1761 ret = phy_driver_register(&rtl8366s_phy_driver);
1762 if (ret)
1763 goto err_platform_unregister;
1764
1765 return 0;
1766
1767 err_platform_unregister:
1768 platform_driver_unregister(&rtl8366s_driver);
1769 return ret;
1770 }
1771 module_init(rtl8366s_module_init);
1772
1773 static void __exit rtl8366s_module_exit(void)
1774 {
1775 phy_driver_unregister(&rtl8366s_phy_driver);
1776 platform_driver_unregister(&rtl8366s_driver);
1777 }
1778 module_exit(rtl8366s_module_exit);
1779
1780 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1781 MODULE_VERSION(RTL8366S_DRIVER_VER);
1782 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1783 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1784 MODULE_LICENSE("GPL v2");
1785 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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