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generic: rtl8366: don't show link parameters if the link is down
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/phy.h>
20 #include <linux/rtl8366s.h>
21
22 #include "rtl8366_smi.h"
23
24 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
25 #include <linux/debugfs.h>
26 #endif
27
28 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
29 #define RTL8366S_DRIVER_VER "0.2.1"
30
31 #define RTL8366S_PHY_NO_MAX 4
32 #define RTL8366S_PHY_PAGE_MAX 7
33 #define RTL8366S_PHY_ADDR_MAX 31
34
35 #define RTL8366_CHIP_GLOBAL_CTRL_REG 0x0000
36 #define RTL8366_CHIP_CTRL_VLAN (1 << 13)
37
38 #define RTL8366_RESET_CTRL_REG 0x0100
39 #define RTL8366_CHIP_CTRL_RESET_HW 1
40 #define RTL8366_CHIP_CTRL_RESET_SW (1 << 1)
41
42 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
43 #define RTL8366S_CHIP_VERSION_MASK 0xf
44 #define RTL8366S_CHIP_ID_REG 0x0105
45 #define RTL8366S_CHIP_ID_8366 0x8366
46
47 /* PHY registers control */
48 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
49 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
50
51 #define RTL8366S_PHY_CTRL_READ 1
52 #define RTL8366S_PHY_CTRL_WRITE 0
53
54 #define RTL8366S_PHY_REG_MASK 0x1f
55 #define RTL8366S_PHY_PAGE_OFFSET 5
56 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
57 #define RTL8366S_PHY_NO_OFFSET 9
58 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
59
60 /* LED control registers */
61 #define RTL8366_LED_BLINKRATE_REG 0x0420
62 #define RTL8366_LED_BLINKRATE_BIT 0
63 #define RTL8366_LED_BLINKRATE_MASK 0x0007
64
65 #define RTL8366_LED_CTRL_REG 0x0421
66 #define RTL8366_LED_0_1_CTRL_REG 0x0422
67 #define RTL8366_LED_2_3_CTRL_REG 0x0423
68
69 #define RTL8366S_MIB_COUNT 33
70 #define RTL8366S_GLOBAL_MIB_COUNT 1
71 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
72 #define RTL8366S_MIB_COUNTER_BASE 0x1000
73 #define RTL8366S_MIB_CTRL_REG 0x11F0
74 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
75 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
76 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
77
78 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
79 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
80 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
81
82
83 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
84 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
85 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
86 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
87 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
88
89
90 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
91 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
92
93 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
94
95 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
96 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
97 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
98
99 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
100
101
102 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
103 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
104 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
105 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
106 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
107 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
108 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
109
110
111 #define RTL8366_PORT_NUM_CPU 5
112 #define RTL8366_NUM_PORTS 6
113 #define RTL8366_NUM_VLANS 16
114 #define RTL8366_NUM_LEDGROUPS 4
115 #define RTL8366_NUM_VIDS 4096
116 #define RTL8366S_PRIORITYMAX 7
117 #define RTL8366S_FIDMAX 7
118
119
120 #define RTL8366_PORT_1 (1 << 0) /* In userspace port 0 */
121 #define RTL8366_PORT_2 (1 << 1) /* In userspace port 1 */
122 #define RTL8366_PORT_3 (1 << 2) /* In userspace port 2 */
123 #define RTL8366_PORT_4 (1 << 3) /* In userspace port 3 */
124
125 #define RTL8366_PORT_UNKNOWN (1 << 4) /* No known connection */
126 #define RTL8366_PORT_CPU (1 << 5) /* CPU port */
127
128 #define RTL8366_PORT_ALL (RTL8366_PORT_1 | \
129 RTL8366_PORT_2 | \
130 RTL8366_PORT_3 | \
131 RTL8366_PORT_4 | \
132 RTL8366_PORT_UNKNOWN | \
133 RTL8366_PORT_CPU)
134
135 #define RTL8366_PORT_ALL_BUT_CPU (RTL8366_PORT_1 | \
136 RTL8366_PORT_2 | \
137 RTL8366_PORT_3 | \
138 RTL8366_PORT_4 | \
139 RTL8366_PORT_UNKNOWN)
140
141 #define RTL8366_PORT_ALL_EXTERNAL (RTL8366_PORT_1 | \
142 RTL8366_PORT_2 | \
143 RTL8366_PORT_3 | \
144 RTL8366_PORT_4)
145
146 #define RTL8366_PORT_ALL_INTERNAL (RTL8366_PORT_UNKNOWN | \
147 RTL8366_PORT_CPU)
148
149 struct rtl8366s {
150 struct device *parent;
151 struct rtl8366_smi smi;
152 struct mii_bus *mii_bus;
153 int mii_irq[PHY_MAX_ADDR];
154 struct switch_dev dev;
155 char buf[4096];
156 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
157 struct dentry *debugfs_root;
158 #endif
159 };
160
161 struct rtl8366s_vlanconfig {
162 u16 reserved2:1;
163 u16 priority:3;
164 u16 vid:12;
165
166 u16 reserved1:1;
167 u16 fid:3;
168 u16 untag:6;
169 u16 member:6;
170 };
171
172 struct rtl8366s_vlan4kentry {
173 u16 reserved1:4;
174 u16 vid:12;
175
176 u16 reserved2:1;
177 u16 fid:3;
178 u16 untag:6;
179 u16 member:6;
180 };
181
182 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
183 u16 g_dbg_reg;
184 #endif
185
186 struct mib_counter {
187 unsigned offset;
188 unsigned length;
189 const char *name;
190 };
191
192 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
193 { 0, 4, "IfInOctets " },
194 { 4, 4, "EtherStatsOctets " },
195 { 8, 2, "EtherStatsUnderSizePkts " },
196 { 10, 2, "EtherFregament " },
197 { 12, 2, "EtherStatsPkts64Octets " },
198 { 14, 2, "EtherStatsPkts65to127Octets " },
199 { 16, 2, "EtherStatsPkts128to255Octets " },
200 { 18, 2, "EtherStatsPkts256to511Octets " },
201 { 20, 2, "EtherStatsPkts512to1023Octets " },
202 { 22, 2, "EtherStatsPkts1024to1518Octets " },
203 { 24, 2, "EtherOversizeStats " },
204 { 26, 2, "EtherStatsJabbers " },
205 { 28, 2, "IfInUcastPkts " },
206 { 30, 2, "EtherStatsMulticastPkts " },
207 { 32, 2, "EtherStatsBroadcastPkts " },
208 { 34, 2, "EtherStatsDropEvents " },
209 { 36, 2, "Dot3StatsFCSErrors " },
210 { 38, 2, "Dot3StatsSymbolErrors " },
211 { 40, 2, "Dot3InPauseFrames " },
212 { 42, 2, "Dot3ControlInUnknownOpcodes " },
213 { 44, 4, "IfOutOctets " },
214 { 48, 2, "Dot3StatsSingleCollisionFrames " },
215 { 50, 2, "Dot3StatMultipleCollisionFrames " },
216 { 52, 2, "Dot3sDeferredTransmissions " },
217 { 54, 2, "Dot3StatsLateCollisions " },
218 { 56, 2, "EtherStatsCollisions " },
219 { 58, 2, "Dot3StatsExcessiveCollisions " },
220 { 60, 2, "Dot3OutPauseFrames " },
221 { 62, 2, "Dot1dBasePortDelayExceededDiscards" },
222 { 64, 2, "Dot1dTpPortInDiscards " },
223 { 66, 2, "IfOutUcastPkts " },
224 { 68, 2, "IfOutMulticastPkts " },
225 { 70, 2, "IfOutBroadcastPkts " },
226 };
227
228 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
229 {
230 return container_of(sw, struct rtl8366s, dev);
231 }
232
233 static int rtl8366s_reset_chip(struct rtl8366s *rtl)
234 {
235 struct rtl8366_smi *smi = &rtl->smi;
236 int timeout = 10;
237 u32 data;
238
239 rtl8366_smi_write_reg(smi, RTL8366_RESET_CTRL_REG,
240 RTL8366_CHIP_CTRL_RESET_HW);
241 do {
242 msleep(1);
243 if (rtl8366_smi_read_reg(smi, RTL8366_RESET_CTRL_REG, &data))
244 return -EIO;
245
246 if (!(data & RTL8366_CHIP_CTRL_RESET_HW))
247 break;
248 } while (--timeout);
249
250 if (!timeout) {
251 printk("Timeout waiting for the switch to reset\n");
252 return -EIO;
253 }
254
255 return 0;
256 }
257
258 static int rtl8366s_read_phy_reg(struct rtl8366s *rtl,
259 u32 phy_no, u32 page, u32 addr, u32 *data)
260 {
261 struct rtl8366_smi *smi = &rtl->smi;
262 u32 reg;
263 int ret;
264
265 if (phy_no > RTL8366S_PHY_NO_MAX)
266 return -EINVAL;
267
268 if (page > RTL8366S_PHY_PAGE_MAX)
269 return -EINVAL;
270
271 if (addr > RTL8366S_PHY_ADDR_MAX)
272 return -EINVAL;
273
274 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
275 RTL8366S_PHY_CTRL_READ);
276 if (ret)
277 return ret;
278
279 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
280 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
281 (addr & RTL8366S_PHY_REG_MASK);
282
283 ret = rtl8366_smi_write_reg(smi, reg, 0);
284 if (ret)
285 return ret;
286
287 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
288 if (ret)
289 return ret;
290
291 return 0;
292 }
293
294 static int rtl8366s_write_phy_reg(struct rtl8366s *rtl,
295 u32 phy_no, u32 page, u32 addr, u32 data)
296 {
297 struct rtl8366_smi *smi = &rtl->smi;
298 u32 reg;
299 int ret;
300
301 if (phy_no > RTL8366S_PHY_NO_MAX)
302 return -EINVAL;
303
304 if (page > RTL8366S_PHY_PAGE_MAX)
305 return -EINVAL;
306
307 if (addr > RTL8366S_PHY_ADDR_MAX)
308 return -EINVAL;
309
310 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
311 RTL8366S_PHY_CTRL_WRITE);
312 if (ret)
313 return ret;
314
315 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
316 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
317 (addr & RTL8366S_PHY_REG_MASK);
318
319 ret = rtl8366_smi_write_reg(smi, reg, data);
320 if (ret)
321 return ret;
322
323 return 0;
324 }
325
326 static int rtl8366_get_mib_counter(struct rtl8366s *rtl, int counter,
327 int port, unsigned long long *val)
328 {
329 struct rtl8366_smi *smi = &rtl->smi;
330 int i;
331 int err;
332 u32 addr, data;
333 u64 mibvalue;
334
335 if (port > RTL8366_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
336 return -EINVAL;
337
338 addr = RTL8366S_MIB_COUNTER_BASE +
339 RTL8366S_MIB_COUNTER_PORT_OFFSET * (port) +
340 rtl8366s_mib_counters[counter].offset;
341
342 /*
343 * Writing access counter address first
344 * then ASIC will prepare 64bits counter wait for being retrived
345 */
346 data = 0; /* writing data will be discard by ASIC */
347 err = rtl8366_smi_write_reg(smi, addr, data);
348 if (err)
349 return err;
350
351 /* read MIB control register */
352 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
353 if (err)
354 return err;
355
356 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
357 return -EBUSY;
358
359 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
360 return -EIO;
361
362 mibvalue = 0;
363 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
364 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
365 if (err)
366 return err;
367
368 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
369 }
370
371 *val = mibvalue;
372 return 0;
373 }
374
375 static int rtl8366s_get_vlan_4k_entry(struct rtl8366s *rtl, u32 vid,
376 struct rtl8366s_vlan4kentry *vlan4k)
377 {
378 struct rtl8366_smi *smi = &rtl->smi;
379 int err;
380 u32 data;
381 u16 *tableaddr;
382
383 memset(vlan4k, '\0', sizeof(struct rtl8366s_vlan4kentry));
384 vlan4k->vid = vid;
385
386 if (vid >= RTL8366_NUM_VIDS)
387 return -EINVAL;
388
389 tableaddr = (u16 *)vlan4k;
390
391 /* write VID */
392 data = *tableaddr;
393 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
394 if (err)
395 return err;
396
397 /* write table access control word */
398 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
399 RTL8366S_TABLE_VLAN_READ_CTRL);
400 if (err)
401 return err;
402
403 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
404 if (err)
405 return err;
406
407 *tableaddr = data;
408 tableaddr++;
409
410 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
411 &data);
412 if (err)
413 return err;
414
415 *tableaddr = data;
416 vlan4k->vid = vid;
417
418 return 0;
419 }
420
421 static int rtl8366s_set_vlan_4k_entry(struct rtl8366s *rtl,
422 const struct rtl8366s_vlan4kentry *vlan4k)
423 {
424 struct rtl8366_smi *smi = &rtl->smi;
425 int err;
426 u32 data;
427 u16 *tableaddr;
428
429 if (vlan4k->vid >= RTL8366_NUM_VIDS ||
430 vlan4k->member > RTL8366_PORT_ALL ||
431 vlan4k->untag > RTL8366_PORT_ALL ||
432 vlan4k->fid > RTL8366S_FIDMAX)
433 return -EINVAL;
434
435 tableaddr = (u16 *)vlan4k;
436
437 data = *tableaddr;
438
439 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
440 if (err)
441 return err;
442
443 tableaddr++;
444
445 data = *tableaddr;
446
447 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
448 data);
449 if (err)
450 return err;
451
452 /* write table access control word */
453 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
454 RTL8366S_TABLE_VLAN_WRITE_CTRL);
455
456 return err;
457 }
458
459 static int rtl8366s_get_vlan_member_config(struct rtl8366s *rtl, u32 index,
460 struct rtl8366s_vlanconfig *vlanmc)
461 {
462 struct rtl8366_smi *smi = &rtl->smi;
463 int err;
464 u32 addr;
465 u32 data;
466 u16 *tableaddr;
467
468 memset(vlanmc, '\0', sizeof(struct rtl8366s_vlanconfig));
469
470 if (index >= RTL8366_NUM_VLANS)
471 return -EINVAL;
472
473 tableaddr = (u16 *)vlanmc;
474
475 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
476 err = rtl8366_smi_read_reg(smi, addr, &data);
477 if (err)
478 return err;
479
480 *tableaddr = data;
481 tableaddr++;
482
483 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
484 err = rtl8366_smi_read_reg(smi, addr, &data);
485 if (err)
486 return err;
487
488 *tableaddr = data;
489
490 return 0;
491 }
492
493 static int rtl8366s_set_vlan_member_config(struct rtl8366s *rtl, u32 index,
494 const struct rtl8366s_vlanconfig
495 *vlanmc)
496 {
497 struct rtl8366_smi *smi = &rtl->smi;
498 int err;
499 u32 addr;
500 u32 data;
501 u16 *tableaddr;
502
503 if (index >= RTL8366_NUM_VLANS ||
504 vlanmc->vid >= RTL8366_NUM_VIDS ||
505 vlanmc->priority > RTL8366S_PRIORITYMAX ||
506 vlanmc->member > RTL8366_PORT_ALL ||
507 vlanmc->untag > RTL8366_PORT_ALL ||
508 vlanmc->fid > RTL8366S_FIDMAX)
509 return -EINVAL;
510
511 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
512
513 tableaddr = (u16 *)vlanmc;
514 data = *tableaddr;
515
516 err = rtl8366_smi_write_reg(smi, addr, data);
517 if (err)
518 return err;
519
520 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
521
522 tableaddr++;
523 data = *tableaddr;
524
525 err = rtl8366_smi_write_reg(smi, addr, data);
526 if (err)
527 return err;
528
529 return 0;
530 }
531
532 static int rtl8366s_get_port_vlan_index(struct rtl8366s *rtl, int port,
533 int *val)
534 {
535 struct rtl8366_smi *smi = &rtl->smi;
536 u32 data;
537 int err;
538
539 if (port >= RTL8366_NUM_PORTS)
540 return -EINVAL;
541
542 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
543 &data);
544 if (err)
545 return err;
546
547 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
548 RTL8366S_PORT_VLAN_CTRL_MASK;
549
550 return 0;
551
552 }
553
554 static int rtl8366s_get_vlan_port_pvid(struct rtl8366s *rtl, int port,
555 int *val)
556 {
557 struct rtl8366s_vlanconfig vlanmc;
558 int err;
559 int index;
560
561 err = rtl8366s_get_port_vlan_index(rtl, port, &index);
562 if (err)
563 return err;
564
565 err = rtl8366s_get_vlan_member_config(rtl, index, &vlanmc);
566 if (err)
567 return err;
568
569 *val = vlanmc.vid;
570 return 0;
571 }
572
573 static int rtl8366s_set_port_vlan_index(struct rtl8366s *rtl, int port,
574 int index)
575 {
576 struct rtl8366_smi *smi = &rtl->smi;
577 u32 data;
578 int err;
579
580 if (port >= RTL8366_NUM_PORTS || index >= RTL8366_NUM_VLANS)
581 return -EINVAL;
582
583 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
584 &data);
585 if (err)
586 return err;
587
588 data &= ~(RTL8366S_PORT_VLAN_CTRL_MASK <<
589 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
590 data |= (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
591 RTL8366S_PORT_VLAN_CTRL_SHIFT(port);
592
593 err = rtl8366_smi_write_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
594 data);
595 return err;
596 }
597
598 static int rtl8366s_set_vlan_port_pvid(struct rtl8366s *rtl, int port, int val)
599 {
600 int i;
601 struct rtl8366s_vlanconfig vlanmc;
602 struct rtl8366s_vlan4kentry vlan4k;
603
604 if (port >= RTL8366_NUM_PORTS || val >= RTL8366_NUM_VIDS)
605 return -EINVAL;
606
607 /* Updating the 4K entry; lookup it and change the port member set */
608 rtl8366s_get_vlan_4k_entry(rtl, val, &vlan4k);
609 vlan4k.member |= ((1 << port) | RTL8366_PORT_CPU);
610 vlan4k.untag = RTL8366_PORT_ALL_BUT_CPU;
611 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
612
613 /*
614 * For the 16 entries more work needs to be done. First see if such
615 * VID is already there and change it
616 */
617 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
618 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
619
620 /* Try to find an existing vid and update port member set */
621 if (val == vlanmc.vid) {
622 vlanmc.member |= ((1 << port) | RTL8366_PORT_CPU);
623 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
624
625 /* Now update PVID register settings */
626 rtl8366s_set_port_vlan_index(rtl, port, i);
627
628 return 0;
629 }
630 }
631
632 /*
633 * PVID could not be found from vlan table. Replace unused (one that
634 * has no member ports) with new one
635 */
636 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
637 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
638
639 /*
640 * See if this vlan member configuration is unused. It is
641 * unused if member set contains no ports or CPU port only
642 */
643 if (!vlanmc.member || vlanmc.member == RTL8366_PORT_CPU) {
644 vlanmc.vid = val;
645 vlanmc.priority = 0;
646 vlanmc.untag = RTL8366_PORT_ALL_BUT_CPU;
647 vlanmc.member = ((1 << port) | RTL8366_PORT_CPU);
648 vlanmc.fid = 0;
649
650 rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
651
652 /* Now update PVID register settings */
653 rtl8366s_set_port_vlan_index(rtl, port, i);
654
655 return 0;
656 }
657 }
658
659 dev_err(rtl->parent,
660 "All 16 vlan member configurations are in use\n");
661
662 return -EINVAL;
663 }
664
665
666 static int rtl8366s_vlan_set_vlan(struct rtl8366s *rtl, int enable)
667 {
668 struct rtl8366_smi *smi = &rtl->smi;
669 u32 data = 0;
670
671 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
672
673 if (enable)
674 data |= RTL8366_CHIP_CTRL_VLAN;
675 else
676 data &= ~RTL8366_CHIP_CTRL_VLAN;
677
678 return rtl8366_smi_write_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, data);
679 }
680
681 static int rtl8366s_vlan_set_4ktable(struct rtl8366s *rtl, int enable)
682 {
683 struct rtl8366_smi *smi = &rtl->smi;
684 u32 data = 0;
685
686 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
687
688 if (enable)
689 data |= 1;
690 else
691 data &= ~1;
692
693 return rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, data);
694 }
695
696 static int rtl8366s_reset_vlan(struct rtl8366s *rtl)
697 {
698 struct rtl8366s_vlan4kentry vlan4k;
699 struct rtl8366s_vlanconfig vlanmc;
700 int err;
701 int i;
702
703 /* clear 16 VLAN member configuration */
704 vlanmc.vid = 0;
705 vlanmc.priority = 0;
706 vlanmc.member = 0;
707 vlanmc.untag = 0;
708 vlanmc.fid = 0;
709 for (i = 0; i < RTL8366_NUM_VLANS; i++) {
710 err = rtl8366s_set_vlan_member_config(rtl, i, &vlanmc);
711 if (err)
712 return err;
713 }
714
715 /* Set a default VLAN with vid 1 to 4K table for all ports */
716 vlan4k.vid = 1;
717 vlan4k.member = RTL8366_PORT_ALL;
718 vlan4k.untag = RTL8366_PORT_ALL;
719 vlan4k.fid = 0;
720 err = rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
721 if (err)
722 return err;
723
724 /* Set all ports PVID to default VLAN */
725 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
726 err = rtl8366s_set_vlan_port_pvid(rtl, i, 0);
727 if (err)
728 return err;
729 }
730
731 return 0;
732 }
733
734 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
735 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
736 {
737 file->private_data = inode->i_private;
738 return 0;
739 }
740
741 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
742 char __user *user_buf,
743 size_t count, loff_t *ppos)
744 {
745 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
746 int i, j, len = 0;
747 char *buf = rtl->buf;
748
749 len += snprintf(buf + len, sizeof(rtl->buf) - len, "MIB Counters:\n");
750 len += snprintf(buf + len, sizeof(rtl->buf) - len, "Counter"
751 " "
752 "Port 0 \t\t Port 1 \t\t Port 2 \t\t Port 3 \t\t "
753 "Port 4\n");
754
755 for (i = 0; i < 33; ++i) {
756 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d:%s ",
757 i, rtl8366s_mib_counters[i].name);
758 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
759 unsigned long long counter = 0;
760
761 if (!rtl8366_get_mib_counter(rtl, i, j, &counter))
762 len += snprintf(buf + len,
763 sizeof(rtl->buf) - len,
764 "[%llu]", counter);
765 else
766 len += snprintf(buf + len,
767 sizeof(rtl->buf) - len,
768 "[error]");
769
770 if (j != RTL8366_NUM_PORTS - 1) {
771 if (counter < 100000)
772 len += snprintf(buf + len,
773 sizeof(rtl->buf) - len,
774 "\t");
775
776 len += snprintf(buf + len,
777 sizeof(rtl->buf) - len,
778 "\t");
779 }
780 }
781 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
782 }
783
784 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
785
786 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
787 }
788
789 static ssize_t rtl8366s_read_debugfs_vlan(struct file *file,
790 char __user *user_buf,
791 size_t count, loff_t *ppos)
792 {
793 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
794 int i, j, len = 0;
795 char *buf = rtl->buf;
796
797 len += snprintf(buf + len, sizeof(rtl->buf) - len,
798 "VLAN Member Config:\n");
799 len += snprintf(buf + len, sizeof(rtl->buf) - len,
800 "\t id \t vid \t prio \t member \t untag \t fid "
801 "\tports\n");
802
803 for (i = 0; i < RTL8366_NUM_VLANS; ++i) {
804 struct rtl8366s_vlanconfig vlanmc;
805
806 rtl8366s_get_vlan_member_config(rtl, i, &vlanmc);
807
808 len += snprintf(buf + len, sizeof(rtl->buf) - len,
809 "\t[%d] \t %d \t %d \t 0x%04x \t 0x%04x \t %d "
810 "\t", i, vlanmc.vid, vlanmc.priority,
811 vlanmc.member, vlanmc.untag, vlanmc.fid);
812
813 for (j = 0; j < RTL8366_NUM_PORTS; ++j) {
814 int index = 0;
815 if (!rtl8366s_get_port_vlan_index(rtl, j, &index)) {
816 if (index == i)
817 len += snprintf(buf + len,
818 sizeof(rtl->buf) - len,
819 "%d", j);
820 }
821 }
822 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
823 }
824
825 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
826 }
827
828 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
829 char __user *user_buf,
830 size_t count, loff_t *ppos)
831 {
832 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
833 struct rtl8366_smi *smi = &rtl->smi;
834 u32 t, reg = g_dbg_reg;
835 int err, len = 0;
836 char *buf = rtl->buf;
837
838 memset(buf, '\0', sizeof(rtl->buf));
839
840 err = rtl8366_smi_read_reg(smi, reg, &t);
841 if (err) {
842 len += snprintf(buf, sizeof(rtl->buf),
843 "Read failed (reg: 0x%04x)\n", reg);
844 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
845 }
846
847 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
848 reg, t);
849
850 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
851 }
852
853 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
854 const char __user *user_buf,
855 size_t count, loff_t *ppos)
856 {
857 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
858 struct rtl8366_smi *smi = &rtl->smi;
859 unsigned long data;
860 u32 reg = g_dbg_reg;
861 int err;
862 size_t len;
863 char *buf = rtl->buf;
864
865 len = min(count, sizeof(rtl->buf) - 1);
866 if (copy_from_user(buf, user_buf, len)) {
867 dev_err(rtl->parent, "copy from user failed\n");
868 return -EFAULT;
869 }
870
871 buf[len] = '\0';
872 if (len > 0 && buf[len - 1] == '\n')
873 buf[len - 1] = '\0';
874
875
876 if (strict_strtoul(buf, 16, &data)) {
877 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
878 } else {
879 err = rtl8366_smi_write_reg(smi, reg, data);
880 if (err) {
881 dev_err(rtl->parent,
882 "writing reg 0x%04x val 0x%04lx failed\n",
883 reg, data);
884 }
885 }
886
887 return count;
888 }
889
890 static const struct file_operations fops_rtl8366s_regs = {
891 .read = rtl8366s_read_debugfs_reg,
892 .write = rtl8366s_write_debugfs_reg,
893 .open = rtl8366s_debugfs_open,
894 .owner = THIS_MODULE
895 };
896
897 static const struct file_operations fops_rtl8366s_vlan = {
898 .read = rtl8366s_read_debugfs_vlan,
899 .open = rtl8366s_debugfs_open,
900 .owner = THIS_MODULE
901 };
902
903 static const struct file_operations fops_rtl8366s_mibs = {
904 .read = rtl8366s_read_debugfs_mibs,
905 .open = rtl8366s_debugfs_open,
906 .owner = THIS_MODULE
907 };
908
909 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
910 {
911 struct dentry *node;
912 struct dentry *root;
913
914 if (!rtl->debugfs_root)
915 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
916
917 if (!rtl->debugfs_root) {
918 dev_err(rtl->parent, "Unable to create debugfs dir\n");
919 return;
920 }
921 root = rtl->debugfs_root;
922
923 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
924 if (!node) {
925 dev_err(rtl->parent, "Creating debugfs file reg failed\n");
926 return;
927 }
928
929 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
930 &fops_rtl8366s_regs);
931 if (!node) {
932 dev_err(rtl->parent, "Creating debugfs file val failed\n");
933 return;
934 }
935
936 node = debugfs_create_file("vlan", S_IRUSR, root, rtl,
937 &fops_rtl8366s_vlan);
938 if (!node) {
939 dev_err(rtl->parent,
940 "Creating debugfs file vlan failed\n");
941 return;
942 }
943
944 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
945 &fops_rtl8366s_mibs);
946 if (!node) {
947 dev_err(rtl->parent,
948 "Creating debugfs file mibs failed\n");
949 return;
950 }
951 }
952
953 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
954 {
955 if (rtl->debugfs_root) {
956 debugfs_remove_recursive(rtl->debugfs_root);
957 rtl->debugfs_root = NULL;
958 }
959 }
960
961 #else
962 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
963 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
964 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
965
966 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
967 const struct switch_attr *attr,
968 struct switch_val *val)
969 {
970 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
971 struct rtl8366_smi *smi = &rtl->smi;
972 u32 data = 0;
973
974 if (val->value.i == 1) {
975 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
976 data |= (1 << 2);
977 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
978 }
979
980 return 0;
981 }
982
983 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
984 const struct switch_attr *attr,
985 struct switch_val *val)
986 {
987 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
988 struct rtl8366_smi *smi = &rtl->smi;
989 u32 data;
990
991 if (attr->ofs == 1) {
992 rtl8366_smi_read_reg(smi, RTL8366_CHIP_GLOBAL_CTRL_REG, &data);
993
994 if (data & RTL8366_CHIP_CTRL_VLAN)
995 val->value.i = 1;
996 else
997 val->value.i = 0;
998 } else if (attr->ofs == 2) {
999 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
1000
1001 if (data & 0x0001)
1002 val->value.i = 1;
1003 else
1004 val->value.i = 0;
1005 }
1006
1007 return 0;
1008 }
1009
1010 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
1011 const struct switch_attr *attr,
1012 struct switch_val *val)
1013 {
1014 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1015 struct rtl8366_smi *smi = &rtl->smi;
1016 u32 data;
1017
1018 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1019
1020 val->value.i = (data & (RTL8366_LED_BLINKRATE_MASK));
1021
1022 return 0;
1023 }
1024
1025 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
1026 const struct switch_attr *attr,
1027 struct switch_val *val)
1028 {
1029 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1030 struct rtl8366_smi *smi = &rtl->smi;
1031 u32 data;
1032
1033 if (val->value.i >= 6)
1034 return -EINVAL;
1035
1036 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1037
1038 data &= ~RTL8366_LED_BLINKRATE_MASK;
1039 data |= val->value.i;
1040
1041 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1042
1043 return 0;
1044 }
1045
1046 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
1047 const struct switch_attr *attr,
1048 struct switch_val *val)
1049 {
1050 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1051
1052 if (attr->ofs == 1)
1053 return rtl8366s_vlan_set_vlan(rtl, val->value.i);
1054 else
1055 return rtl8366s_vlan_set_4ktable(rtl, val->value.i);
1056 }
1057
1058 static const char *rtl8366s_speed_str(unsigned speed)
1059 {
1060 switch (speed) {
1061 case 0:
1062 return "10baseT";
1063 case 1:
1064 return "100baseT";
1065 case 2:
1066 return "1000baseT";
1067 }
1068
1069 return "unknown";
1070 }
1071
1072 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
1073 const struct switch_attr *attr,
1074 struct switch_val *val)
1075 {
1076 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1077 struct rtl8366_smi *smi = &rtl->smi;
1078 u32 len = 0, data = 0;
1079
1080 if (val->port_vlan >= RTL8366_NUM_PORTS)
1081 return -EINVAL;
1082
1083 memset(rtl->buf, '\0', sizeof(rtl->buf));
1084 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
1085 (val->port_vlan / 2), &data);
1086
1087 if (val->port_vlan % 2)
1088 data = data >> 8;
1089
1090 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
1091 len = snprintf(rtl->buf, sizeof(rtl->buf),
1092 "port:%d link:up speed:%s %s-duplex %s%s%s",
1093 val->port_vlan,
1094 rtl8366s_speed_str(data &
1095 RTL8366S_PORT_STATUS_SPEED_MASK),
1096 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1097 "full" : "half",
1098 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1099 "tx-pause ": "",
1100 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1101 "rx-pause " : "",
1102 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1103 "nway ": "");
1104 } else {
1105 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1106 val->port_vlan);
1107 }
1108
1109 val->value.s = rtl->buf;
1110 val->len = len;
1111
1112 return 0;
1113 }
1114
1115 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1116 const struct switch_attr *attr,
1117 struct switch_val *val)
1118 {
1119 int i;
1120 u32 len = 0;
1121 struct rtl8366s_vlanconfig vlanmc;
1122 struct rtl8366s_vlan4kentry vlan4k;
1123 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1124 char *buf = rtl->buf;
1125
1126 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1127 return -EINVAL;
1128
1129 memset(buf, '\0', sizeof(rtl->buf));
1130
1131 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1132 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1133
1134 len += snprintf(buf + len, sizeof(rtl->buf) - len, "VLAN %d: Ports: ",
1135 val->port_vlan);
1136
1137 for (i = 0; i < RTL8366_NUM_PORTS; ++i) {
1138 int index = 0;
1139 if (!rtl8366s_get_port_vlan_index(rtl, i, &index) &&
1140 index == val->port_vlan)
1141 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1142 "%d", i);
1143 }
1144 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
1145
1146 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1147 "\t\t vid \t prio \t member \t untag \t fid\n");
1148 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\tMC:\t");
1149 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1150 "%d \t %d \t 0x%04x \t 0x%04x \t %d\n",
1151 vlanmc.vid, vlanmc.priority, vlanmc.member,
1152 vlanmc.untag, vlanmc.fid);
1153 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\t4K:\t");
1154 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1155 "%d \t \t 0x%04x \t 0x%04x \t %d",
1156 vlan4k.vid, vlan4k.member, vlan4k.untag, vlan4k.fid);
1157
1158 val->value.s = buf;
1159 val->len = len;
1160
1161 return 0;
1162 }
1163
1164 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1165 const struct switch_attr *attr,
1166 struct switch_val *val)
1167 {
1168 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1169 struct rtl8366_smi *smi = &rtl->smi;
1170 u32 data = 0;
1171
1172 if (val->port_vlan >= RTL8366_NUM_PORTS ||
1173 (1 << val->port_vlan) == RTL8366_PORT_UNKNOWN)
1174 return -EINVAL;
1175
1176 if (val->port_vlan == RTL8366_PORT_NUM_CPU) {
1177 rtl8366_smi_read_reg(smi, RTL8366_LED_BLINKRATE_REG, &data);
1178 data = (data & (~(0xF << 4))) | (val->value.i << 4);
1179 rtl8366_smi_write_reg(smi, RTL8366_LED_BLINKRATE_REG, data);
1180 } else {
1181 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1182 data = (data & (~(0xF << (val->port_vlan * 4)))) |
1183 (val->value.i << (val->port_vlan * 4));
1184 rtl8366_smi_write_reg(smi, RTL8366_LED_CTRL_REG, data);
1185 }
1186
1187 return 0;
1188 }
1189
1190 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1191 const struct switch_attr *attr,
1192 struct switch_val *val)
1193 {
1194 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1195 struct rtl8366_smi *smi = &rtl->smi;
1196 u32 data = 0;
1197
1198 if (val->port_vlan >= RTL8366_NUM_LEDGROUPS)
1199 return -EINVAL;
1200
1201 rtl8366_smi_read_reg(smi, RTL8366_LED_CTRL_REG, &data);
1202 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1203
1204 return 0;
1205 }
1206
1207 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1208 const struct switch_attr *attr,
1209 struct switch_val *val)
1210 {
1211 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1212 struct rtl8366_smi *smi = &rtl->smi;
1213 u32 data = 0;
1214
1215 if (val->port_vlan >= RTL8366_NUM_PORTS)
1216 return -EINVAL;
1217
1218 rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
1219 data |= (1 << (val->port_vlan + 3));
1220 rtl8366_smi_write_reg(smi, RTL8366S_MIB_CTRL_REG, data);
1221
1222 return 0;
1223 }
1224
1225 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1226 const struct switch_attr *attr,
1227 struct switch_val *val)
1228 {
1229 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1230 int i, len = 0;
1231 unsigned long long counter = 0;
1232 char *buf = rtl->buf;
1233
1234 if (val->port_vlan >= RTL8366_NUM_PORTS)
1235 return -EINVAL;
1236
1237 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1238 "Port %d MIB counters\n",
1239 val->port_vlan);
1240
1241 for (i = 0; i < RTL8366S_MIB_COUNT; ++i) {
1242 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1243 "%d:%s\t", i, rtl8366s_mib_counters[i].name);
1244 if (!rtl8366_get_mib_counter(rtl, i, val->port_vlan, &counter))
1245 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1246 "[%llu]\n", counter);
1247 else
1248 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1249 "[error]\n");
1250 }
1251
1252 val->value.s = buf;
1253 val->len = len;
1254 return 0;
1255 }
1256
1257 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1258 struct switch_val *val)
1259 {
1260 struct rtl8366s_vlanconfig vlanmc;
1261 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1262 struct switch_port *port;
1263 int i;
1264
1265 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1266 return -EINVAL;
1267
1268 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1269
1270 port = &val->value.ports[0];
1271 val->len = 0;
1272 for (i = 0; i < RTL8366_NUM_PORTS; i++) {
1273 if (!(vlanmc.member & BIT(i)))
1274 continue;
1275
1276 port->id = i;
1277 port->flags = (vlanmc.untag & BIT(i)) ?
1278 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1279 val->len++;
1280 port++;
1281 }
1282 return 0;
1283 }
1284
1285 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1286 struct switch_val *val)
1287 {
1288 struct rtl8366s_vlanconfig vlanmc;
1289 struct rtl8366s_vlan4kentry vlan4k;
1290 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1291 struct switch_port *port;
1292 int i;
1293
1294 if (val->port_vlan == 0 || val->port_vlan >= RTL8366_NUM_VLANS)
1295 return -EINVAL;
1296
1297 rtl8366s_get_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1298 rtl8366s_get_vlan_4k_entry(rtl, vlanmc.vid, &vlan4k);
1299
1300 vlanmc.untag = 0;
1301 vlanmc.member = 0;
1302
1303 port = &val->value.ports[0];
1304 for (i = 0; i < val->len; i++, port++) {
1305 vlanmc.member |= BIT(port->id);
1306
1307 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1308 vlanmc.untag |= BIT(port->id);
1309 }
1310
1311 vlan4k.member = vlanmc.member;
1312 vlan4k.untag = vlanmc.untag;
1313
1314 rtl8366s_set_vlan_member_config(rtl, val->port_vlan, &vlanmc);
1315 rtl8366s_set_vlan_4k_entry(rtl, &vlan4k);
1316 return 0;
1317 }
1318
1319 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1320 {
1321 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1322 return rtl8366s_get_vlan_port_pvid(rtl, port, val);
1323 }
1324
1325 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1326 {
1327 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1328 return rtl8366s_set_vlan_port_pvid(rtl, port, val);
1329 }
1330
1331 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1332 {
1333 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1334 int err;
1335
1336 err = rtl8366s_reset_chip(rtl);
1337 if (err)
1338 return err;
1339
1340 return rtl8366s_reset_vlan(rtl);
1341 }
1342
1343 static struct switch_attr rtl8366s_globals[] = {
1344 {
1345 .type = SWITCH_TYPE_INT,
1346 .name = "enable_vlan",
1347 .description = "Enable VLAN mode",
1348 .set = rtl8366s_sw_set_vlan_enable,
1349 .get = rtl8366s_sw_get_vlan_enable,
1350 .max = 1,
1351 .ofs = 1
1352 }, {
1353 .type = SWITCH_TYPE_INT,
1354 .name = "enable_vlan4k",
1355 .description = "Enable VLAN 4K mode",
1356 .set = rtl8366s_sw_set_vlan_enable,
1357 .get = rtl8366s_sw_get_vlan_enable,
1358 .max = 1,
1359 .ofs = 2
1360 }, {
1361 .type = SWITCH_TYPE_INT,
1362 .name = "reset_mibs",
1363 .description = "Reset all MIB counters",
1364 .set = rtl8366s_sw_reset_mibs,
1365 .get = NULL,
1366 .max = 1
1367 }, {
1368 .type = SWITCH_TYPE_INT,
1369 .name = "blinkrate",
1370 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1371 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1372 .set = rtl8366s_sw_set_blinkrate,
1373 .get = rtl8366s_sw_get_blinkrate,
1374 .max = 5
1375 },
1376 };
1377
1378 static struct switch_attr rtl8366s_port[] = {
1379 {
1380 .type = SWITCH_TYPE_STRING,
1381 .name = "link",
1382 .description = "Get port link information",
1383 .max = 1,
1384 .set = NULL,
1385 .get = rtl8366s_sw_get_port_link,
1386 }, {
1387 .type = SWITCH_TYPE_INT,
1388 .name = "reset_mib",
1389 .description = "Reset single port MIB counters",
1390 .max = 1,
1391 .set = rtl8366s_sw_reset_port_mibs,
1392 .get = NULL,
1393 }, {
1394 .type = SWITCH_TYPE_STRING,
1395 .name = "mib",
1396 .description = "Get MIB counters for port",
1397 .max = 33,
1398 .set = NULL,
1399 .get = rtl8366s_sw_get_port_mib,
1400 }, {
1401 .type = SWITCH_TYPE_INT,
1402 .name = "led",
1403 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1404 .max = 15,
1405 .set = rtl8366s_sw_set_port_led,
1406 .get = rtl8366s_sw_get_port_led,
1407 },
1408 };
1409
1410 static struct switch_attr rtl8366s_vlan[] = {
1411 {
1412 .type = SWITCH_TYPE_STRING,
1413 .name = "info",
1414 .description = "Get vlan information",
1415 .max = 1,
1416 .set = NULL,
1417 .get = rtl8366s_sw_get_vlan_info,
1418 },
1419 };
1420
1421 /* template */
1422 static struct switch_dev rtl8366_switch_dev = {
1423 .name = "RTL8366S",
1424 .cpu_port = RTL8366_PORT_NUM_CPU,
1425 .ports = RTL8366_NUM_PORTS,
1426 .vlans = RTL8366_NUM_VLANS,
1427 .attr_global = {
1428 .attr = rtl8366s_globals,
1429 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1430 },
1431 .attr_port = {
1432 .attr = rtl8366s_port,
1433 .n_attr = ARRAY_SIZE(rtl8366s_port),
1434 },
1435 .attr_vlan = {
1436 .attr = rtl8366s_vlan,
1437 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1438 },
1439
1440 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1441 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1442 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1443 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1444 .reset_switch = rtl8366s_sw_reset_switch,
1445 };
1446
1447 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1448 {
1449 struct switch_dev *dev = &rtl->dev;
1450 int err;
1451
1452 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1453 dev->priv = rtl;
1454 dev->devname = dev_name(rtl->parent);
1455
1456 err = register_switch(dev, NULL);
1457 if (err)
1458 dev_err(rtl->parent, "switch registration failed\n");
1459
1460 return err;
1461 }
1462
1463 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1464 {
1465 unregister_switch(&rtl->dev);
1466 }
1467
1468 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1469 {
1470 struct rtl8366s *rtl = bus->priv;
1471 u32 val = 0;
1472 int err;
1473
1474 err = rtl8366s_read_phy_reg(rtl, addr, 0, reg, &val);
1475 if (err)
1476 return 0xffff;
1477
1478 return val;
1479 }
1480
1481 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1482 {
1483 struct rtl8366s *rtl = bus->priv;
1484 u32 t;
1485 int err;
1486
1487 err = rtl8366s_write_phy_reg(rtl, addr, 0, reg, val);
1488 /* flush write */
1489 (void) rtl8366s_read_phy_reg(rtl, addr, 0, reg, &t);
1490
1491 return err;
1492 }
1493
1494 static int rtl8366s_mii_init(struct rtl8366s *rtl)
1495 {
1496 int ret;
1497 int i;
1498
1499 rtl->mii_bus = mdiobus_alloc();
1500 if (rtl->mii_bus == NULL) {
1501 ret = -ENOMEM;
1502 goto err;
1503 }
1504
1505 rtl->mii_bus->priv = (void *) rtl;
1506 rtl->mii_bus->name = "rtl8366-rtl";
1507 rtl->mii_bus->read = rtl8366s_mii_read;
1508 rtl->mii_bus->write = rtl8366s_mii_write;
1509 snprintf(rtl->mii_bus->id, MII_BUS_ID_SIZE, "%s",
1510 dev_name(rtl->parent));
1511 rtl->mii_bus->parent = rtl->parent;
1512 rtl->mii_bus->phy_mask = ~(0x1f);
1513 rtl->mii_bus->irq = rtl->mii_irq;
1514 for (i = 0; i < PHY_MAX_ADDR; i++)
1515 rtl->mii_irq[i] = PHY_POLL;
1516
1517 ret = mdiobus_register(rtl->mii_bus);
1518 if (ret)
1519 goto err_free;
1520
1521 return 0;
1522
1523 err_free:
1524 mdiobus_free(rtl->mii_bus);
1525 err:
1526 return ret;
1527 }
1528
1529 static void rtl8366s_mii_cleanup(struct rtl8366s *rtl)
1530 {
1531 mdiobus_unregister(rtl->mii_bus);
1532 mdiobus_free(rtl->mii_bus);
1533 }
1534
1535 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1536 {
1537 return (bus->read == rtl8366s_mii_read &&
1538 bus->write == rtl8366s_mii_write);
1539 }
1540
1541 static int rtl8366s_setup(struct rtl8366s *rtl)
1542 {
1543 struct rtl8366_smi *smi = &rtl->smi;
1544 u32 chip_id = 0;
1545 u32 chip_ver = 0;
1546 int ret;
1547
1548 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1549 if (ret) {
1550 dev_err(rtl->parent, "unable to read chip id\n");
1551 return ret;
1552 }
1553
1554 switch (chip_id) {
1555 case RTL8366S_CHIP_ID_8366:
1556 break;
1557 default:
1558 dev_err(rtl->parent, "unknown chip id (%04x)\n", chip_id);
1559 return -ENODEV;
1560 }
1561
1562 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1563 &chip_ver);
1564 if (ret) {
1565 dev_err(rtl->parent, "unable to read chip version\n");
1566 return ret;
1567 }
1568
1569 dev_info(rtl->parent, "RTL%04x ver. %u chip found\n",
1570 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1571
1572 ret = rtl8366s_reset_chip(rtl);
1573 if (ret)
1574 return ret;
1575
1576 rtl8366s_debugfs_init(rtl);
1577 return 0;
1578 }
1579
1580 static int __init rtl8366s_probe(struct platform_device *pdev)
1581 {
1582 static int rtl8366_smi_version_printed;
1583 struct rtl8366s_platform_data *pdata;
1584 struct rtl8366s *rtl;
1585 struct rtl8366_smi *smi;
1586 int err;
1587
1588 if (!rtl8366_smi_version_printed++)
1589 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1590 " version " RTL8366S_DRIVER_VER"\n");
1591
1592 pdata = pdev->dev.platform_data;
1593 if (!pdata) {
1594 dev_err(&pdev->dev, "no platform data specified\n");
1595 err = -EINVAL;
1596 goto err_out;
1597 }
1598
1599 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1600 if (!rtl) {
1601 dev_err(&pdev->dev, "no memory for private data\n");
1602 err = -ENOMEM;
1603 goto err_out;
1604 }
1605
1606 rtl->parent = &pdev->dev;
1607
1608 smi = &rtl->smi;
1609 smi->parent = &pdev->dev;
1610 smi->gpio_sda = pdata->gpio_sda;
1611 smi->gpio_sck = pdata->gpio_sck;
1612
1613 err = rtl8366_smi_init(smi);
1614 if (err)
1615 goto err_free_rtl;
1616
1617 platform_set_drvdata(pdev, rtl);
1618
1619 err = rtl8366s_setup(rtl);
1620 if (err)
1621 goto err_clear_drvdata;
1622
1623 err = rtl8366s_mii_init(rtl);
1624 if (err)
1625 goto err_clear_drvdata;
1626
1627 err = rtl8366s_switch_init(rtl);
1628 if (err)
1629 goto err_mii_cleanup;
1630
1631 return 0;
1632
1633 err_mii_cleanup:
1634 rtl8366s_mii_cleanup(rtl);
1635 err_clear_drvdata:
1636 platform_set_drvdata(pdev, NULL);
1637 rtl8366_smi_cleanup(smi);
1638 err_free_rtl:
1639 kfree(rtl);
1640 err_out:
1641 return err;
1642 }
1643
1644 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1645 {
1646 if (!rtl8366s_mii_bus_match(phydev->bus))
1647 return -EINVAL;
1648
1649 return 0;
1650 }
1651
1652 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1653 {
1654 return 0;
1655 }
1656
1657 static struct phy_driver rtl8366s_phy_driver = {
1658 .phy_id = 0x001cc960,
1659 .name = "Realtek RTL8366S",
1660 .phy_id_mask = 0x1ffffff0,
1661 .features = PHY_GBIT_FEATURES,
1662 .config_aneg = rtl8366s_phy_config_aneg,
1663 .config_init = rtl8366s_phy_config_init,
1664 .read_status = genphy_read_status,
1665 .driver = {
1666 .owner = THIS_MODULE,
1667 },
1668 };
1669
1670 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1671 {
1672 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1673
1674 if (rtl) {
1675 rtl8366s_switch_cleanup(rtl);
1676 rtl8366s_debugfs_remove(rtl);
1677 rtl8366s_mii_cleanup(rtl);
1678 platform_set_drvdata(pdev, NULL);
1679 rtl8366_smi_cleanup(&rtl->smi);
1680 kfree(rtl);
1681 }
1682
1683 return 0;
1684 }
1685
1686 static struct platform_driver rtl8366s_driver = {
1687 .driver = {
1688 .name = RTL8366S_DRIVER_NAME,
1689 .owner = THIS_MODULE,
1690 },
1691 .probe = rtl8366s_probe,
1692 .remove = __devexit_p(rtl8366s_remove),
1693 };
1694
1695 static int __init rtl8366s_module_init(void)
1696 {
1697 int ret;
1698 ret = platform_driver_register(&rtl8366s_driver);
1699 if (ret)
1700 return ret;
1701
1702 ret = phy_driver_register(&rtl8366s_phy_driver);
1703 if (ret)
1704 goto err_platform_unregister;
1705
1706 return 0;
1707
1708 err_platform_unregister:
1709 platform_driver_unregister(&rtl8366s_driver);
1710 return ret;
1711 }
1712 module_init(rtl8366s_module_init);
1713
1714 static void __exit rtl8366s_module_exit(void)
1715 {
1716 phy_driver_unregister(&rtl8366s_phy_driver);
1717 platform_driver_unregister(&rtl8366s_driver);
1718 }
1719 module_exit(rtl8366s_module_exit);
1720
1721 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1722 MODULE_VERSION(RTL8366S_DRIVER_VER);
1723 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1724 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1725 MODULE_LICENSE("GPL v2");
1726 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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