aa7342d871ceefdbbf552c322d4af3fab00fa00a
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / patches-2.6.23 / 310-ssb_pcicore_fixes.patch
1 Index: linux-2.6.23/drivers/ssb/driver_pcicore.c
2 ===================================================================
3 --- linux-2.6.23.orig/drivers/ssb/driver_pcicore.c 2007-10-13 04:20:23.235499369 +0200
4 +++ linux-2.6.23/drivers/ssb/driver_pcicore.c 2007-10-13 04:21:28.895241103 +0200
5 @@ -93,10 +93,13 @@
6
7 /* Enable PCI bridge BAR1 prefetch and burst */
8 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3);
9 +
10 + /* Make sure our latency is high enough to handle the devices behind us */
11 + pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xa8);
12 }
13 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_fixup_pcibridge);
14
15 -int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
16 +int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
17 {
18 return ssb_mips_irq(extpci_core->dev) + 2;
19 }
20 @@ -110,7 +113,7 @@
21
22 if (unlikely(pc->cardbusmode && dev > 1))
23 goto out;
24 - if (bus == 0) {
25 + if (bus == 0) {//FIXME busnumber ok?
26 /* Type 0 transaction */
27 if (unlikely(dev >= SSB_PCI_SLOT_MAX))
28 goto out;
29 @@ -224,7 +227,7 @@
30 val = *((const u32 *)buf);
31 break;
32 }
33 - writel(*((const u32 *)buf), mmio);
34 + writel(val, mmio);
35
36 err = 0;
37 unmap:
38 @@ -307,6 +310,8 @@
39 udelay(150);
40 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */
41 pcicore_write32(pc, SSB_PCICORE_CTL, val);
42 + val = SSB_PCICORE_ARBCTL_INTERN;
43 + pcicore_write32(pc, SSB_PCICORE_ARBCTL, val);
44 udelay(1);
45
46 //TODO cardbus mode
47 @@ -336,6 +341,7 @@
48 * The following needs change, if we want to port hostmode
49 * to non-MIPS platform. */
50 set_io_port_base((unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000));
51 + mdelay(300);
52 register_pci_controller(&ssb_pcicore_controller);
53 }
54