[8.09] kernel: refresh patches
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / patches-2.6.24 / 009-revert_intel_flash_breakage.patch
1 --- a/drivers/mtd/chips/cfi_cmdset_0001.c
2 +++ b/drivers/mtd/chips/cfi_cmdset_0001.c
3 @@ -944,7 +944,7 @@ static void __xipram xip_enable(struct m
4
5 static int __xipram xip_wait_for_operation(
6 struct map_info *map, struct flchip *chip,
7 - unsigned long adr, unsigned int chip_op_time )
8 + unsigned long adr, int *chip_op_time )
9 {
10 struct cfi_private *cfi = map->fldrv_priv;
11 struct cfi_pri_intelext *cfip = cfi->cmdset_priv;
12 @@ -953,7 +953,7 @@ static int __xipram xip_wait_for_operati
13 flstate_t oldstate, newstate;
14
15 start = xip_currtime();
16 - usec = chip_op_time * 8;
17 + usec = *chip_op_time * 8;
18 if (usec == 0)
19 usec = 500000;
20 done = 0;
21 @@ -1063,8 +1063,8 @@ static int __xipram xip_wait_for_operati
22 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
23 INVALIDATE_CACHED_RANGE(map, from, size)
24
25 -#define INVAL_CACHE_AND_WAIT(map, chip, cmd_adr, inval_adr, inval_len, usec) \
26 - xip_wait_for_operation(map, chip, cmd_adr, usec)
27 +#define INVAL_CACHE_AND_WAIT(map, chip, cmd_adr, inval_adr, inval_len, p_usec) \
28 + xip_wait_for_operation(map, chip, cmd_adr, p_usec)
29
30 #else
31
32 @@ -1076,65 +1076,65 @@ static int __xipram xip_wait_for_operati
33 static int inval_cache_and_wait_for_operation(
34 struct map_info *map, struct flchip *chip,
35 unsigned long cmd_adr, unsigned long inval_adr, int inval_len,
36 - unsigned int chip_op_time)
37 + int *chip_op_time )
38 {
39 struct cfi_private *cfi = map->fldrv_priv;
40 map_word status, status_OK = CMD(0x80);
41 - int chip_state = chip->state;
42 - unsigned int timeo, sleep_time;
43 + int z, chip_state = chip->state;
44 + unsigned long timeo;
45
46 spin_unlock(chip->mutex);
47 if (inval_len)
48 INVALIDATE_CACHED_RANGE(map, inval_adr, inval_len);
49 + if (*chip_op_time)
50 + cfi_udelay(*chip_op_time);
51 spin_lock(chip->mutex);
52
53 - /* set our timeout to 8 times the expected delay */
54 - timeo = chip_op_time * 8;
55 - if (!timeo)
56 - timeo = 500000;
57 - sleep_time = chip_op_time / 2;
58 + timeo = *chip_op_time * 8 * HZ / 1000000;
59 + if (timeo < HZ/2)
60 + timeo = HZ/2;
61 + timeo += jiffies;
62
63 + z = 0;
64 for (;;) {
65 + if (chip->state != chip_state) {
66 + /* Someone's suspended the operation: sleep */
67 + DECLARE_WAITQUEUE(wait, current);
68 +
69 + set_current_state(TASK_UNINTERRUPTIBLE);
70 + add_wait_queue(&chip->wq, &wait);
71 + spin_unlock(chip->mutex);
72 + schedule();
73 + remove_wait_queue(&chip->wq, &wait);
74 + timeo = jiffies + (HZ / 2); /* FIXME */
75 + spin_lock(chip->mutex);
76 + continue;
77 + }
78 +
79 status = map_read(map, cmd_adr);
80 if (map_word_andequal(map, status, status_OK, status_OK))
81 break;
82
83 - if (!timeo) {
84 + /* OK Still waiting */
85 + if (time_after(jiffies, timeo)) {
86 map_write(map, CMD(0x70), cmd_adr);
87 chip->state = FL_STATUS;
88 return -ETIME;
89 }
90
91 - /* OK Still waiting. Drop the lock, wait a while and retry. */
92 + /* Latency issues. Drop the lock, wait a while and retry */
93 + z++;
94 spin_unlock(chip->mutex);
95 - if (sleep_time >= 1000000/HZ) {
96 - /*
97 - * Half of the normal delay still remaining
98 - * can be performed with a sleeping delay instead
99 - * of busy waiting.
100 - */
101 - msleep(sleep_time/1000);
102 - timeo -= sleep_time;
103 - sleep_time = 1000000/HZ;
104 - } else {
105 - udelay(1);
106 - cond_resched();
107 - timeo--;
108 - }
109 + cfi_udelay(1);
110 spin_lock(chip->mutex);
111 -
112 - while (chip->state != chip_state) {
113 - /* Someone's suspended the operation: sleep */
114 - DECLARE_WAITQUEUE(wait, current);
115 - set_current_state(TASK_UNINTERRUPTIBLE);
116 - add_wait_queue(&chip->wq, &wait);
117 - spin_unlock(chip->mutex);
118 - schedule();
119 - remove_wait_queue(&chip->wq, &wait);
120 - spin_lock(chip->mutex);
121 - }
122 }
123
124 + if (!z) {
125 + if (!--(*chip_op_time))
126 + *chip_op_time = 1;
127 + } else if (z > 1)
128 + ++(*chip_op_time);
129 +
130 /* Done and happy. */
131 chip->state = FL_STATUS;
132 return 0;
133 @@ -1143,7 +1143,8 @@ static int inval_cache_and_wait_for_oper
134 #endif
135
136 #define WAIT_TIMEOUT(map, chip, adr, udelay) \
137 - INVAL_CACHE_AND_WAIT(map, chip, adr, 0, 0, udelay);
138 + ({ int __udelay = (udelay); \
139 + INVAL_CACHE_AND_WAIT(map, chip, adr, 0, 0, &__udelay); })
140
141
142 static int do_point_onechip (struct map_info *map, struct flchip *chip, loff_t adr, size_t len)
143 @@ -1374,7 +1375,7 @@ static int __xipram do_write_oneword(str
144
145 ret = INVAL_CACHE_AND_WAIT(map, chip, adr,
146 adr, map_bankwidth(map),
147 - chip->word_write_time);
148 + &chip->word_write_time);
149 if (ret) {
150 xip_enable(map, chip, adr);
151 printk(KERN_ERR "%s: word write error (status timeout)\n", map->name);
152 @@ -1614,7 +1615,7 @@ static int __xipram do_write_buffer(stru
153
154 ret = INVAL_CACHE_AND_WAIT(map, chip, cmd_adr,
155 initial_adr, initial_len,
156 - chip->buffer_write_time);
157 + &chip->buffer_write_time);
158 if (ret) {
159 map_write(map, CMD(0x70), cmd_adr);
160 chip->state = FL_STATUS;
161 @@ -1749,7 +1750,7 @@ static int __xipram do_erase_oneblock(st
162
163 ret = INVAL_CACHE_AND_WAIT(map, chip, adr,
164 adr, len,
165 - chip->erase_time);
166 + &chip->erase_time);
167 if (ret) {
168 map_write(map, CMD(0x70), adr);
169 chip->state = FL_STATUS;