[kernel] refresh patches
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / patches-2.6.28 / 023-mips_delay_gcc4.4.0.patch
1 From: Wu Zhangjin <wuzj@lemote.com>
2
3 the gcc 4.4 support for MIPS mostly refer to this PATCH:
4 http://www.nabble.com/-PATCH--MIPS:-Handle-removal-of-%27h%27-constraint-in-GCC-4.4-td22192768.html
5 but have been tuned a little.
6
7 because only gcc 4.4 have loongson-specific support, so, we need to
8 choose the suitable -march argument for gcc <= 4.3 and gcc >= 4.4, and
9 we also need to consider use -march=loongson2e and -march=loongson2f for
10 loongson2e and loongson2f respectively. this is handled by adding two
11 new kernel options: CPU_LOONGSON2E and CPU_LOONGSON2F(thanks for the
12 solutin provided by ZhangLe).
13
14 I have tested it on FuLoong(2f) in 32bit and 64bit with gcc-4.4 and
15 gcc-4.3. so, basically, it works.
16
17 Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
18 ---
19 arch/mips/Makefile | 9 +++++-
20 arch/mips/include/asm/compiler.h | 10 ++++++
21 arch/mips/include/asm/delay.h | 58 +++++++++++++++++++++++++------------
22 3 files changed, 57 insertions(+), 20 deletions(-)
23
24 --- a/arch/mips/Makefile
25 +++ b/arch/mips/Makefile
26 @@ -119,7 +119,14 @@ cflags-$(CONFIG_CPU_R4300) += -march=r43
27 cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
28 cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
29 cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
30 -cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap
31 +
32 +# only gcc >= 4.4 have the loongson-specific support
33 +cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
34 +cflags-$(CONFIG_CPU_LOONGSON2E) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \
35 + echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2e); fi ;)
36 +cflags-$(CONFIG_CPU_LOONGSON2F) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \
37 + echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2f); fi ;)
38 +
39 cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
40 -Wa,-mips32 -Wa,--trap
41 cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
42 --- a/arch/mips/include/asm/compiler.h
43 +++ b/arch/mips/include/asm/compiler.h
44 @@ -1,5 +1,6 @@
45 /*
46 * Copyright (C) 2004, 2007 Maciej W. Rozycki
47 + * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com
48 *
49 * This file is subject to the terms and conditions of the GNU General Public
50 * License. See the file "COPYING" in the main directory of this archive
51 @@ -16,4 +17,13 @@
52 #define GCC_REG_ACCUM "accum"
53 #endif
54
55 +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
56 +#define GCC_NO_H_CONSTRAINT
57 +#ifdef CONFIG_64BIT
58 +typedef unsigned int uintx_t __attribute__((mode(TI)));
59 +#else
60 +typedef u64 uintx_t;
61 +#endif
62 +#endif
63 +
64 #endif /* _ASM_COMPILER_H */
65 --- a/arch/mips/include/asm/delay.h
66 +++ b/arch/mips/include/asm/delay.h
67 @@ -7,6 +7,7 @@
68 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
69 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
70 * Copyright (C) 2007 Maciej W. Rozycki
71 + * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com
72 */
73 #ifndef _ASM_DELAY_H
74 #define _ASM_DELAY_H
75 @@ -48,6 +49,43 @@ static inline void __delay(unsigned long
76 : "0" (loops), "r" (1));
77 }
78
79 +/*
80 + * convert usecs to loops
81 + *
82 + * handle removal of 'h' constraint in GCC 4.4
83 + */
84 +
85 +#ifndef GCC_NO_H_CONSTRAINT /* gcc <= 4.3 */
86 +static inline unsigned long __usecs_to_loops(unsigned long usecs,
87 + unsigned long lpj)
88 +{
89 + unsigned long hi, lo;
90 +
91 + if (sizeof(long) == 4)
92 + __asm__("multu\t%2, %3"
93 + : "=h" (usecs), "=l" (lo)
94 + : "r" (usecs), "r" (lpj)
95 + : GCC_REG_ACCUM);
96 + else if (sizeof(long) == 8 && !R4000_WAR)
97 + __asm__("dmultu\t%2, %3"
98 + : "=h" (usecs), "=l" (lo)
99 + : "r" (usecs), "r" (lpj)
100 + : GCC_REG_ACCUM);
101 + else if (sizeof(long) == 8 && R4000_WAR)
102 + __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
103 + : "=r" (usecs), "=h" (hi), "=l" (lo)
104 + : "r" (usecs), "r" (lpj)
105 + : GCC_REG_ACCUM);
106 +
107 + return usecs;
108 +}
109 +#else /* GCC_NO_H_CONSTRAINT, gcc >= 4.4 */
110 +static inline unsigned long __usecs_to_loops(unsigned long usecs,
111 + unsigned long lpj)
112 +{
113 + return ((uintx_t)usecs * lpj) >> BITS_PER_LONG;
114 +}
115 +#endif
116
117 /*
118 * Division by multiplication: you don't have to worry about
119 @@ -62,8 +100,6 @@ static inline void __delay(unsigned long
120
121 static inline void __udelay(unsigned long usecs, unsigned long lpj)
122 {
123 - unsigned long hi, lo;
124 -
125 /*
126 * The rates of 128 is rounded wrongly by the catchall case
127 * for 64-bit. Excessive precission? Probably ...
128 @@ -77,23 +113,7 @@ static inline void __udelay(unsigned lon
129 0x80000000ULL) >> 32);
130 #endif
131
132 - if (sizeof(long) == 4)
133 - __asm__("multu\t%2, %3"
134 - : "=h" (usecs), "=l" (lo)
135 - : "r" (usecs), "r" (lpj)
136 - : GCC_REG_ACCUM);
137 - else if (sizeof(long) == 8 && !R4000_WAR)
138 - __asm__("dmultu\t%2, %3"
139 - : "=h" (usecs), "=l" (lo)
140 - : "r" (usecs), "r" (lpj)
141 - : GCC_REG_ACCUM);
142 - else if (sizeof(long) == 8 && R4000_WAR)
143 - __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
144 - : "=r" (usecs), "=h" (hi), "=l" (lo)
145 - : "r" (usecs), "r" (lpj)
146 - : GCC_REG_ACCUM);
147 -
148 - __delay(usecs);
149 + __delay(__usecs_to_loops(usecs, lpj));
150 }
151
152 #define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val