ed95bcdc1cf7f505bdb0e8de212d9770a0944ff8
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / patches-2.6.30 / 023-mips_delay_gcc4.4.0.patch
1 From: Wu Zhangjin <wuzj@lemote.com>
2
3 the gcc 4.4 support for MIPS mostly refer to this PATCH:
4 http://www.nabble.com/-PATCH--MIPS:-Handle-removal-of-%27h%27-constraint-in-GCC-4.4-td22192768.html
5 but have been tuned a little.
6
7 because only gcc 4.4 have loongson-specific support, so, we need to
8 choose the suitable -march argument for gcc <= 4.3 and gcc >= 4.4, and
9 we also need to consider use -march=loongson2e and -march=loongson2f for
10 loongson2e and loongson2f respectively. this is handled by adding two
11 new kernel options: CPU_LOONGSON2E and CPU_LOONGSON2F(thanks for the
12 solutin provided by ZhangLe).
13
14 I have tested it on FuLoong(2f) in 32bit and 64bit with gcc-4.4 and
15 gcc-4.3. so, basically, it works.
16
17 Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com>
18 ---
19 arch/mips/Makefile | 9 +++++-
20 arch/mips/include/asm/compiler.h | 10 ++++++
21 arch/mips/include/asm/delay.h | 58 +++++++++++++++++++++++++------------
22 3 files changed, 57 insertions(+), 20 deletions(-)
23
24 diff --git a/arch/mips/Makefile b/arch/mips/Makefile
25 index a25c2e5..1ee5504 100644
26 --- a/arch/mips/Makefile
27 +++ b/arch/mips/Makefile
28 @@ -120,7 +120,14 @@ cflags-$(CONFIG_CPU_R4300) += -march=r4300 -Wa,--trap
29 cflags-$(CONFIG_CPU_VR41XX) += -march=r4100 -Wa,--trap
30 cflags-$(CONFIG_CPU_R4X00) += -march=r4600 -Wa,--trap
31 cflags-$(CONFIG_CPU_TX49XX) += -march=r4600 -Wa,--trap
32 -cflags-$(CONFIG_CPU_LOONGSON2) += -march=r4600 -Wa,--trap
33 +
34 +# only gcc >= 4.4 have the loongson-specific support
35 +cflags-$(CONFIG_CPU_LOONGSON2) += -Wa,--trap
36 +cflags-$(CONFIG_CPU_LOONGSON2E) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \
37 + echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2e); fi ;)
38 +cflags-$(CONFIG_CPU_LOONGSON2F) += $(shell if [ $(call cc-version) -lt 0440 ] ; then \
39 + echo $(call cc-option,-march=r4600); else echo $(call cc-option,-march=loongson2f); fi ;)
40 +
41 cflags-$(CONFIG_CPU_MIPS32_R1) += $(call cc-option,-march=mips32,-mips32 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
42 -Wa,-mips32 -Wa,--trap
43 cflags-$(CONFIG_CPU_MIPS32_R2) += $(call cc-option,-march=mips32r2,-mips32r2 -U_MIPS_ISA -D_MIPS_ISA=_MIPS_ISA_MIPS32) \
44 diff --git a/arch/mips/include/asm/compiler.h b/arch/mips/include/asm/compiler.h
45 index 71f5c5c..95256a8 100644
46 --- a/arch/mips/include/asm/compiler.h
47 +++ b/arch/mips/include/asm/compiler.h
48 @@ -1,5 +1,6 @@
49 /*
50 * Copyright (C) 2004, 2007 Maciej W. Rozycki
51 + * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com
52 *
53 * This file is subject to the terms and conditions of the GNU General Public
54 * License. See the file "COPYING" in the main directory of this archive
55 @@ -16,4 +17,13 @@
56 #define GCC_REG_ACCUM "accum"
57 #endif
58
59 +#if __GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 4)
60 +#define GCC_NO_H_CONSTRAINT
61 +#ifdef CONFIG_64BIT
62 +typedef unsigned int uintx_t __attribute__((mode(TI)));
63 +#else
64 +typedef u64 uintx_t;
65 +#endif
66 +#endif
67 +
68 #endif /* _ASM_COMPILER_H */
69 diff --git a/arch/mips/include/asm/delay.h b/arch/mips/include/asm/delay.h
70 index b0bccd2..00d7969 100644
71 --- a/arch/mips/include/asm/delay.h
72 +++ b/arch/mips/include/asm/delay.h
73 @@ -7,6 +7,7 @@
74 * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
75 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
76 * Copyright (C) 2007 Maciej W. Rozycki
77 + * Copyright (C) 2009 Wu Zhangjin, wuzj@lemote.com
78 */
79 #ifndef _ASM_DELAY_H
80 #define _ASM_DELAY_H
81 @@ -48,6 +49,43 @@ static inline void __delay(unsigned long loops)
82 : "0" (loops), "r" (1));
83 }
84
85 +/*
86 + * convert usecs to loops
87 + *
88 + * handle removal of 'h' constraint in GCC 4.4
89 + */
90 +
91 +#ifndef GCC_NO_H_CONSTRAINT /* gcc <= 4.3 */
92 +static inline unsigned long __usecs_to_loops(unsigned long usecs,
93 + unsigned long lpj)
94 +{
95 + unsigned long hi, lo;
96 +
97 + if (sizeof(long) == 4)
98 + __asm__("multu\t%2, %3"
99 + : "=h" (usecs), "=l" (lo)
100 + : "r" (usecs), "r" (lpj)
101 + : GCC_REG_ACCUM);
102 + else if (sizeof(long) == 8 && !R4000_WAR)
103 + __asm__("dmultu\t%2, %3"
104 + : "=h" (usecs), "=l" (lo)
105 + : "r" (usecs), "r" (lpj)
106 + : GCC_REG_ACCUM);
107 + else if (sizeof(long) == 8 && R4000_WAR)
108 + __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
109 + : "=r" (usecs), "=h" (hi), "=l" (lo)
110 + : "r" (usecs), "r" (lpj)
111 + : GCC_REG_ACCUM);
112 +
113 + return usecs;
114 +}
115 +#else /* GCC_NO_H_CONSTRAINT, gcc >= 4.4 */
116 +static inline unsigned long __usecs_to_loops(unsigned long usecs,
117 + unsigned long lpj)
118 +{
119 + return ((uintx_t)usecs * lpj) >> BITS_PER_LONG;
120 +}
121 +#endif
122
123 /*
124 * Division by multiplication: you don't have to worry about
125 @@ -62,8 +100,6 @@ static inline void __delay(unsigned long loops)
126
127 static inline void __udelay(unsigned long usecs, unsigned long lpj)
128 {
129 - unsigned long hi, lo;
130 -
131 /*
132 * The rates of 128 is rounded wrongly by the catchall case
133 * for 64-bit. Excessive precission? Probably ...
134 @@ -77,23 +113,7 @@ static inline void __udelay(unsigned long usecs, unsigned long lpj)
135 0x80000000ULL) >> 32);
136 #endif
137
138 - if (sizeof(long) == 4)
139 - __asm__("multu\t%2, %3"
140 - : "=h" (usecs), "=l" (lo)
141 - : "r" (usecs), "r" (lpj)
142 - : GCC_REG_ACCUM);
143 - else if (sizeof(long) == 8 && !R4000_WAR)
144 - __asm__("dmultu\t%2, %3"
145 - : "=h" (usecs), "=l" (lo)
146 - : "r" (usecs), "r" (lpj)
147 - : GCC_REG_ACCUM);
148 - else if (sizeof(long) == 8 && R4000_WAR)
149 - __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
150 - : "=r" (usecs), "=h" (hi), "=l" (lo)
151 - : "r" (usecs), "r" (lpj)
152 - : GCC_REG_ACCUM);
153 -
154 - __delay(usecs);
155 + __delay(__usecs_to_loops(usecs, lpj));
156 }
157
158 #define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
159 --
160 1.6.0.4
161
162
163