kernel: bring ssb in sync with upstream (as of current wireless-testing)
[openwrt/svn-archive/archive.git] / target / linux / generic-2.6 / patches-2.6.30 / 941-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon_pmu.c
2 +++ b/drivers/ssb/driver_chipcommon_pmu.c
3 @@ -28,6 +28,21 @@ static void ssb_chipco_pll_write(struct
4 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
5 }
6
7 +static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
8 + u32 offset, u32 mask, u32 set)
9 +{
10 + u32 value;
11 +
12 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
13 + chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
14 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
15 + value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
16 + value &= mask;
17 + value |= set;
18 + chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
19 + chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
20 +}
21 +
22 struct pmu0_plltab_entry {
23 u16 freq; /* Crystal frequency in kHz.*/
24 u8 xf; /* Crystal frequency value for PMU control */
25 @@ -317,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
26 case 0x5354:
27 ssb_pmu0_pllinit_r0(cc, crystalfreq);
28 break;
29 + case 0x4322:
30 + if (cc->pmu.rev == 2) {
31 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
32 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
33 + }
34 + break;
35 default:
36 ssb_printk(KERN_ERR PFX
37 "ERROR: PLL init unknown for device %04X\n",
38 @@ -402,6 +423,7 @@ static void ssb_pmu_resources_init(struc
39
40 switch (bus->chip_id) {
41 case 0x4312:
42 + case 0x4322:
43 /* We keep the default settings:
44 * min_msk = 0xCBB
45 * max_msk = 0x7FFFF
46 @@ -506,3 +528,82 @@ void ssb_pmu_init(struct ssb_chipcommon
47 ssb_pmu_pll_init(cc);
48 ssb_pmu_resources_init(cc);
49 }
50 +
51 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
52 + enum ssb_pmu_ldo_volt_id id, u32 voltage)
53 +{
54 + struct ssb_bus *bus = cc->dev->bus;
55 + u32 addr, shift, mask;
56 +
57 + switch (bus->chip_id) {
58 + case 0x4328:
59 + case 0x5354:
60 + switch (id) {
61 + case LDO_VOLT1:
62 + addr = 2;
63 + shift = 25;
64 + mask = 0xF;
65 + break;
66 + case LDO_VOLT2:
67 + addr = 3;
68 + shift = 1;
69 + mask = 0xF;
70 + break;
71 + case LDO_VOLT3:
72 + addr = 3;
73 + shift = 9;
74 + mask = 0xF;
75 + break;
76 + case LDO_PAREF:
77 + addr = 3;
78 + shift = 17;
79 + mask = 0x3F;
80 + break;
81 + default:
82 + SSB_WARN_ON(1);
83 + return;
84 + }
85 + break;
86 + case 0x4312:
87 + if (SSB_WARN_ON(id != LDO_PAREF))
88 + return;
89 + addr = 0;
90 + shift = 21;
91 + mask = 0x3F;
92 + break;
93 + default:
94 + return;
95 + }
96 +
97 + ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
98 + (voltage & mask) << shift);
99 +}
100 +
101 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
102 +{
103 + struct ssb_bus *bus = cc->dev->bus;
104 + int ldo;
105 +
106 + switch (bus->chip_id) {
107 + case 0x4312:
108 + ldo = SSB_PMURES_4312_PA_REF_LDO;
109 + break;
110 + case 0x4328:
111 + ldo = SSB_PMURES_4328_PA_REF_LDO;
112 + break;
113 + case 0x5354:
114 + ldo = SSB_PMURES_5354_PA_REF_LDO;
115 + break;
116 + default:
117 + return;
118 + }
119 +
120 + if (on)
121 + chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
122 + else
123 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
124 + chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
125 +}
126 +
127 +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
128 +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
129 --- a/drivers/ssb/main.c
130 +++ b/drivers/ssb/main.c
131 @@ -472,6 +472,8 @@ static int ssb_devices_register(struct s
132 case SSB_BUSTYPE_SSB:
133 dev->dma_mask = &dev->coherent_dma_mask;
134 break;
135 + default:
136 + break;
137 }
138
139 sdev->dev = dev;
140 @@ -1358,8 +1360,10 @@ static int __init ssb_modinit(void)
141 ssb_buses_lock();
142 err = ssb_attach_queued_buses();
143 ssb_buses_unlock();
144 - if (err)
145 + if (err) {
146 bus_unregister(&ssb_bustype);
147 + goto out;
148 + }
149
150 err = b43_pci_ssb_bridge_init();
151 if (err) {
152 @@ -1375,7 +1379,7 @@ static int __init ssb_modinit(void)
153 /* don't fail SSB init because of this */
154 err = 0;
155 }
156 -
157 +out:
158 return err;
159 }
160 /* ssb must be initialized after PCI but before the ssb drivers.
161 --- a/drivers/ssb/pci.c
162 +++ b/drivers/ssb/pci.c
163 @@ -167,10 +167,16 @@ err_pci:
164 }
165
166 /* Get the word-offset for a SSB_SPROM_XXX define. */
167 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
168 +#define SPOFF(offset) ((offset) / sizeof(u16))
169 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
170 -#define SPEX(_outvar, _offset, _mask, _shift) \
171 +#define SPEX16(_outvar, _offset, _mask, _shift) \
172 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
173 +#define SPEX32(_outvar, _offset, _mask, _shift) \
174 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
175 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
176 +#define SPEX(_outvar, _offset, _mask, _shift) \
177 + SPEX16(_outvar, _offset, _mask, _shift)
178 +
179
180 static inline u8 ssb_crc8(u8 crc, u8 data)
181 {
182 @@ -247,7 +253,7 @@ static int sprom_do_read(struct ssb_bus
183 int i;
184
185 for (i = 0; i < bus->sprom_size; i++)
186 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
187 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
188
189 return 0;
190 }
191 @@ -278,7 +284,7 @@ static int sprom_do_write(struct ssb_bus
192 ssb_printk("75%%");
193 else if (i % 2)
194 ssb_printk(".");
195 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
196 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
197 mmiowb();
198 msleep(20);
199 }
200 @@ -474,12 +480,14 @@ static void sprom_extract_r8(struct ssb_
201
202 /* extract the MAC address */
203 for (i = 0; i < 3; i++) {
204 - v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
205 + v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
206 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
207 }
208 SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
209 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
210 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
211 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
212 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
213 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
214 SSB_SPROM8_ANTAVAIL_A_SHIFT);
215 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
216 @@ -490,12 +498,55 @@ static void sprom_extract_r8(struct ssb_
217 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
218 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
219 SSB_SPROM8_ITSSI_A_SHIFT);
220 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
221 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
222 + SSB_SPROM8_MAXP_AL_SHIFT);
223 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
224 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
225 SSB_SPROM8_GPIOA_P1_SHIFT);
226 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
227 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
228 SSB_SPROM8_GPIOB_P3_SHIFT);
229 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
230 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
231 + SSB_SPROM8_TRI5G_SHIFT);
232 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
233 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
234 + SSB_SPROM8_TRI5GH_SHIFT);
235 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
236 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
237 + SSB_SPROM8_RXPO5G_SHIFT);
238 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
239 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
240 + SSB_SPROM8_RSSISMC2G_SHIFT);
241 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
242 + SSB_SPROM8_RSSISAV2G_SHIFT);
243 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
244 + SSB_SPROM8_BXA2G_SHIFT);
245 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
246 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
247 + SSB_SPROM8_RSSISMC5G_SHIFT);
248 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
249 + SSB_SPROM8_RSSISAV5G_SHIFT);
250 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
251 + SSB_SPROM8_BXA5G_SHIFT);
252 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
253 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
254 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
255 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
256 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
257 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
258 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
259 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
260 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
261 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
262 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
263 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
264 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
265 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
266 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
267 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
268 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
269
270 /* Extract the antenna gain values. */
271 SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
272 @@ -549,6 +600,7 @@ static int sprom_extract(struct ssb_bus
273 ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
274 " revision %d detected. Will extract"
275 " v1\n", out->revision);
276 + out->revision = 1;
277 sprom_extract_r123(out, in);
278 }
279 }
280 @@ -568,6 +620,14 @@ static int ssb_pci_sprom_get(struct ssb_
281 int err = -ENOMEM;
282 u16 *buf;
283
284 + if (!ssb_is_sprom_available(bus)) {
285 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
286 + return -ENODEV;
287 + }
288 +
289 + bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ?
290 + SSB_SPROM_BASE1 : SSB_SPROM_BASE31;
291 +
292 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
293 if (!buf)
294 goto out;
295 --- a/drivers/ssb/pcmcia.c
296 +++ b/drivers/ssb/pcmcia.c
297 @@ -583,7 +583,7 @@ static int ssb_pcmcia_sprom_write_all(st
298 ssb_printk(".");
299 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
300 if (err) {
301 - ssb_printk("\n" KERN_NOTICE PFX
302 + ssb_printk(KERN_NOTICE PFX
303 "Failed to write to SPROM.\n");
304 failed = 1;
305 break;
306 @@ -591,7 +591,7 @@ static int ssb_pcmcia_sprom_write_all(st
307 }
308 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
309 if (err) {
310 - ssb_printk("\n" KERN_NOTICE PFX
311 + ssb_printk(KERN_NOTICE PFX
312 "Could not disable SPROM write access.\n");
313 failed = 1;
314 }
315 @@ -617,134 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
316 } \
317 } while (0)
318
319 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
320 - struct ssb_init_invariants *iv)
321 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
322 + tuple_t *tuple,
323 + void *priv)
324 {
325 - tuple_t tuple;
326 - int res;
327 - unsigned char buf[32];
328 + struct ssb_sprom *sprom = priv;
329 +
330 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
331 + return -EINVAL;
332 + if (tuple->TupleDataLen != ETH_ALEN + 2)
333 + return -EINVAL;
334 + if (tuple->TupleData[1] != ETH_ALEN)
335 + return -EINVAL;
336 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
337 + return 0;
338 +};
339 +
340 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
341 + tuple_t *tuple,
342 + void *priv)
343 +{
344 + struct ssb_init_invariants *iv = priv;
345 struct ssb_sprom *sprom = &iv->sprom;
346 struct ssb_boardinfo *bi = &iv->boardinfo;
347 const char *error_description;
348
349 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
350 + switch (tuple->TupleData[0]) {
351 + case SSB_PCMCIA_CIS_ID:
352 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
353 + (tuple->TupleDataLen != 7),
354 + "id tpl size");
355 + bi->vendor = tuple->TupleData[1] |
356 + ((u16)tuple->TupleData[2] << 8);
357 + break;
358 + case SSB_PCMCIA_CIS_BOARDREV:
359 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
360 + "boardrev tpl size");
361 + sprom->board_rev = tuple->TupleData[1];
362 + break;
363 + case SSB_PCMCIA_CIS_PA:
364 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
365 + (tuple->TupleDataLen != 10),
366 + "pa tpl size");
367 + sprom->pa0b0 = tuple->TupleData[1] |
368 + ((u16)tuple->TupleData[2] << 8);
369 + sprom->pa0b1 = tuple->TupleData[3] |
370 + ((u16)tuple->TupleData[4] << 8);
371 + sprom->pa0b2 = tuple->TupleData[5] |
372 + ((u16)tuple->TupleData[6] << 8);
373 + sprom->itssi_a = tuple->TupleData[7];
374 + sprom->itssi_bg = tuple->TupleData[7];
375 + sprom->maxpwr_a = tuple->TupleData[8];
376 + sprom->maxpwr_bg = tuple->TupleData[8];
377 + break;
378 + case SSB_PCMCIA_CIS_OEMNAME:
379 + /* We ignore this. */
380 + break;
381 + case SSB_PCMCIA_CIS_CCODE:
382 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
383 + "ccode tpl size");
384 + sprom->country_code = tuple->TupleData[1];
385 + break;
386 + case SSB_PCMCIA_CIS_ANTENNA:
387 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
388 + "ant tpl size");
389 + sprom->ant_available_a = tuple->TupleData[1];
390 + sprom->ant_available_bg = tuple->TupleData[1];
391 + break;
392 + case SSB_PCMCIA_CIS_ANTGAIN:
393 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
394 + "antg tpl size");
395 + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
396 + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
397 + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
398 + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
399 + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
400 + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
401 + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
402 + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
403 + break;
404 + case SSB_PCMCIA_CIS_BFLAGS:
405 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
406 + (tuple->TupleDataLen != 5),
407 + "bfl tpl size");
408 + sprom->boardflags_lo = tuple->TupleData[1] |
409 + ((u16)tuple->TupleData[2] << 8);
410 + break;
411 + case SSB_PCMCIA_CIS_LEDS:
412 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
413 + "leds tpl size");
414 + sprom->gpio0 = tuple->TupleData[1];
415 + sprom->gpio1 = tuple->TupleData[2];
416 + sprom->gpio2 = tuple->TupleData[3];
417 + sprom->gpio3 = tuple->TupleData[4];
418 + break;
419 + }
420 + return -ENOSPC; /* continue with next entry */
421 +
422 +error:
423 + ssb_printk(KERN_ERR PFX
424 + "PCMCIA: Failed to fetch device invariants: %s\n",
425 + error_description);
426 + return -ENODEV;
427 +}
428 +
429 +
430 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
431 + struct ssb_init_invariants *iv)
432 +{
433 + struct ssb_sprom *sprom = &iv->sprom;
434 + int res;
435 +
436 memset(sprom, 0xFF, sizeof(*sprom));
437 sprom->revision = 1;
438 sprom->boardflags_lo = 0;
439 sprom->boardflags_hi = 0;
440
441 /* First fetch the MAC address. */
442 - memset(&tuple, 0, sizeof(tuple));
443 - tuple.DesiredTuple = CISTPL_FUNCE;
444 - tuple.TupleData = buf;
445 - tuple.TupleDataMax = sizeof(buf);
446 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
447 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
448 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
449 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
450 - while (1) {
451 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
452 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
453 - break;
454 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
455 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
456 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
457 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
458 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
459 + ssb_pcmcia_get_mac, sprom);
460 + if (res != 0) {
461 + ssb_printk(KERN_ERR PFX
462 + "PCMCIA: Failed to fetch MAC address\n");
463 + return -ENODEV;
464 }
465 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
466 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
467
468 /* Fetch the vendor specific tuples. */
469 - memset(&tuple, 0, sizeof(tuple));
470 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
471 - tuple.TupleData = buf;
472 - tuple.TupleDataMax = sizeof(buf);
473 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
474 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
475 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
476 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
477 - while (1) {
478 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
479 - switch (tuple.TupleData[0]) {
480 - case SSB_PCMCIA_CIS_ID:
481 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
482 - (tuple.TupleDataLen != 7),
483 - "id tpl size");
484 - bi->vendor = tuple.TupleData[1] |
485 - ((u16)tuple.TupleData[2] << 8);
486 - break;
487 - case SSB_PCMCIA_CIS_BOARDREV:
488 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
489 - "boardrev tpl size");
490 - sprom->board_rev = tuple.TupleData[1];
491 - break;
492 - case SSB_PCMCIA_CIS_PA:
493 - GOTO_ERROR_ON(tuple.TupleDataLen != 9,
494 - "pa tpl size");
495 - sprom->pa0b0 = tuple.TupleData[1] |
496 - ((u16)tuple.TupleData[2] << 8);
497 - sprom->pa0b1 = tuple.TupleData[3] |
498 - ((u16)tuple.TupleData[4] << 8);
499 - sprom->pa0b2 = tuple.TupleData[5] |
500 - ((u16)tuple.TupleData[6] << 8);
501 - sprom->itssi_a = tuple.TupleData[7];
502 - sprom->itssi_bg = tuple.TupleData[7];
503 - sprom->maxpwr_a = tuple.TupleData[8];
504 - sprom->maxpwr_bg = tuple.TupleData[8];
505 - break;
506 - case SSB_PCMCIA_CIS_OEMNAME:
507 - /* We ignore this. */
508 - break;
509 - case SSB_PCMCIA_CIS_CCODE:
510 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
511 - "ccode tpl size");
512 - sprom->country_code = tuple.TupleData[1];
513 - break;
514 - case SSB_PCMCIA_CIS_ANTENNA:
515 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
516 - "ant tpl size");
517 - sprom->ant_available_a = tuple.TupleData[1];
518 - sprom->ant_available_bg = tuple.TupleData[1];
519 - break;
520 - case SSB_PCMCIA_CIS_ANTGAIN:
521 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
522 - "antg tpl size");
523 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
524 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
525 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
526 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
527 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
528 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
529 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
530 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
531 - break;
532 - case SSB_PCMCIA_CIS_BFLAGS:
533 - GOTO_ERROR_ON(tuple.TupleDataLen != 3,
534 - "bfl tpl size");
535 - sprom->boardflags_lo = tuple.TupleData[1] |
536 - ((u16)tuple.TupleData[2] << 8);
537 - break;
538 - case SSB_PCMCIA_CIS_LEDS:
539 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
540 - "leds tpl size");
541 - sprom->gpio0 = tuple.TupleData[1];
542 - sprom->gpio1 = tuple.TupleData[2];
543 - sprom->gpio2 = tuple.TupleData[3];
544 - sprom->gpio3 = tuple.TupleData[4];
545 - break;
546 - }
547 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
548 - if (res == -ENOSPC)
549 - break;
550 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
551 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
552 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
553 - }
554 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
555 + ssb_pcmcia_do_get_invariants, sprom);
556 + if ((res == 0) || (res == -ENOSPC))
557 + return 0;
558
559 - return 0;
560 -error:
561 ssb_printk(KERN_ERR PFX
562 - "PCMCIA: Failed to fetch device invariants: %s\n",
563 - error_description);
564 + "PCMCIA: Failed to fetch device invariants\n");
565 return -ENODEV;
566 }
567
568 --- a/include/linux/ssb/ssb.h
569 +++ b/include/linux/ssb/ssb.h
570 @@ -27,24 +27,54 @@ struct ssb_sprom {
571 u8 et1mdcport; /* MDIO for enet1 */
572 u8 board_rev; /* Board revision number from SPROM. */
573 u8 country_code; /* Country Code */
574 - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
575 - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
576 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
577 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
578 u16 pa0b0;
579 u16 pa0b1;
580 u16 pa0b2;
581 u16 pa1b0;
582 u16 pa1b1;
583 u16 pa1b2;
584 + u16 pa1lob0;
585 + u16 pa1lob1;
586 + u16 pa1lob2;
587 + u16 pa1hib0;
588 + u16 pa1hib1;
589 + u16 pa1hib2;
590 u8 gpio0; /* GPIO pin 0 */
591 u8 gpio1; /* GPIO pin 1 */
592 u8 gpio2; /* GPIO pin 2 */
593 u8 gpio3; /* GPIO pin 3 */
594 - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
595 - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
596 + u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
597 + u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
598 + u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
599 + u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
600 u8 itssi_a; /* Idle TSSI Target for A-PHY */
601 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
602 - u16 boardflags_lo; /* Boardflags (low 16 bits) */
603 - u16 boardflags_hi; /* Boardflags (high 16 bits) */
604 + u8 tri2g; /* 2.4GHz TX isolation */
605 + u8 tri5gl; /* 5.2GHz TX isolation */
606 + u8 tri5g; /* 5.3GHz TX isolation */
607 + u8 tri5gh; /* 5.8GHz TX isolation */
608 + u8 rxpo2g; /* 2GHz RX power offset */
609 + u8 rxpo5g; /* 5GHz RX power offset */
610 + u8 rssisav2g; /* 2GHz RSSI params */
611 + u8 rssismc2g;
612 + u8 rssismf2g;
613 + u8 bxa2g; /* 2GHz BX arch */
614 + u8 rssisav5g; /* 5GHz RSSI params */
615 + u8 rssismc5g;
616 + u8 rssismf5g;
617 + u8 bxa5g; /* 5GHz BX arch */
618 + u16 cck2gpo; /* CCK power offset */
619 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
620 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
621 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
622 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
623 + u16 boardflags_lo; /* Board flags (bits 0-15) */
624 + u16 boardflags_hi; /* Board flags (bits 16-31) */
625 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
626 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
627 + /* TODO store board flags in a single u64 */
628
629 /* Antenna gain values for up to 4 antennas
630 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
631 @@ -58,7 +88,7 @@ struct ssb_sprom {
632 } ghz5; /* 5GHz band */
633 } antenna_gain;
634
635 - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
636 + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
637 };
638
639 /* Information about the PCB the circuitry is soldered on. */
640 @@ -208,6 +238,7 @@ enum ssb_bustype {
641 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
642 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
643 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
644 + SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
645 };
646
647 /* board_vendor */
648 @@ -238,20 +269,33 @@ struct ssb_bus {
649
650 const struct ssb_bus_ops *ops;
651
652 - /* The core in the basic address register window. (PCI bus only) */
653 + /* The core currently mapped into the MMIO window.
654 + * Not valid on all host-buses. So don't use outside of SSB. */
655 struct ssb_device *mapped_device;
656 - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
657 - u8 mapped_pcmcia_seg;
658 + union {
659 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
660 + u8 mapped_pcmcia_seg;
661 + /* Current SSB base address window for SDIO. */
662 + u32 sdio_sbaddr;
663 + };
664 /* Lock for core and segment switching.
665 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
666 spinlock_t bar_lock;
667
668 - /* The bus this backplane is running on. */
669 + /* The host-bus this backplane is running on. */
670 enum ssb_bustype bustype;
671 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
672 - struct pci_dev *host_pci;
673 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
674 - struct pcmcia_device *host_pcmcia;
675 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
676 + union {
677 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
678 + struct pci_dev *host_pci;
679 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
680 + struct pcmcia_device *host_pcmcia;
681 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
682 + struct sdio_func *host_sdio;
683 + };
684 +
685 + /* See enum ssb_quirks */
686 + unsigned int quirks;
687
688 #ifdef CONFIG_SSB_SPROM
689 /* Mutex to protect the SPROM writing. */
690 @@ -261,6 +305,7 @@ struct ssb_bus {
691 /* ID information about the Chip. */
692 u16 chip_id;
693 u16 chip_rev;
694 + u16 sprom_offset;
695 u16 sprom_size; /* number of words in sprom */
696 u8 chip_package;
697
698 @@ -306,6 +351,11 @@ struct ssb_bus {
699 #endif /* DEBUG */
700 };
701
702 +enum ssb_quirks {
703 + /* SDIO connected card requires performing a read after writing a 32-bit value */
704 + SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
705 +};
706 +
707 /* The initialization-invariants. */
708 struct ssb_init_invariants {
709 /* Versioning information about the PCB. */
710 @@ -336,9 +386,18 @@ extern int ssb_bus_pcmciabus_register(st
711 struct pcmcia_device *pcmcia_dev,
712 unsigned long baseaddr);
713 #endif /* CONFIG_SSB_PCMCIAHOST */
714 +#ifdef CONFIG_SSB_SDIOHOST
715 +extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
716 + struct sdio_func *sdio_func,
717 + unsigned int quirks);
718 +#endif /* CONFIG_SSB_SDIOHOST */
719 +
720
721 extern void ssb_bus_unregister(struct ssb_bus *bus);
722
723 +/* Does the device have an SPROM? */
724 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
725 +
726 /* Set a fallback SPROM.
727 * See kdoc at the function definition for complete documentation. */
728 extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
729 --- a/include/linux/ssb/ssb_driver_chipcommon.h
730 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
731 @@ -53,6 +53,7 @@
732 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
733 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
734 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
735 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
736 #define SSB_CHIPCO_CORECTL 0x0008
737 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
738 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
739 @@ -385,6 +386,7 @@
740
741
742 /** Chip specific Chip-Status register contents. */
743 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
744 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
745 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
746 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
747 @@ -398,6 +400,18 @@
748 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
749 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
750
751 +/** Macros to determine SPROM presence based on Chip-Status register. */
752 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
753 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
754 + SSB_CHIPCO_CHST_4325_OTP_SEL)
755 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
756 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
757 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
758 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
759 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
760 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
761 + SSB_CHIPCO_CHST_4325_OTP_SEL))
762 +
763
764
765 /** Clockcontrol masks and values **/
766 @@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu {
767 struct ssb_chipcommon {
768 struct ssb_device *dev;
769 u32 capabilities;
770 + u32 status;
771 /* Fast Powerup Delay constant */
772 u16 fast_pwrup_delay;
773 struct ssb_chipcommon_pmu pmu;
774 @@ -629,5 +644,15 @@ extern int ssb_chipco_serial_init(struct
775 /* PMU support */
776 extern void ssb_pmu_init(struct ssb_chipcommon *cc);
777
778 +enum ssb_pmu_ldo_volt_id {
779 + LDO_PAREF = 0,
780 + LDO_VOLT1,
781 + LDO_VOLT2,
782 + LDO_VOLT3,
783 +};
784 +
785 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
786 + enum ssb_pmu_ldo_volt_id id, u32 voltage);
787 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
788
789 #endif /* LINUX_SSB_CHIPCO_H_ */
790 --- a/include/linux/ssb/ssb_regs.h
791 +++ b/include/linux/ssb/ssb_regs.h
792 @@ -162,7 +162,7 @@
793
794 /* SPROM shadow area. If not otherwise noted, fields are
795 * two bytes wide. Note that the SPROM can _only_ be read
796 - * in two-byte quantinies.
797 + * in two-byte quantities.
798 */
799 #define SSB_SPROMSIZE_WORDS 64
800 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
801 @@ -170,26 +170,27 @@
802 #define SSB_SPROMSIZE_WORDS_R4 220
803 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
804 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
805 -#define SSB_SPROM_BASE 0x1000
806 -#define SSB_SPROM_REVISION 0x107E
807 +#define SSB_SPROM_BASE1 0x1000
808 +#define SSB_SPROM_BASE31 0x0800
809 +#define SSB_SPROM_REVISION 0x007E
810 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
811 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
812 #define SSB_SPROM_REVISION_CRC_SHIFT 8
813
814 /* SPROM Revision 1 */
815 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
816 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
817 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
818 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
819 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
820 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
821 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
822 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
823 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
824 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
825 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
826 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
827 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
828 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
829 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
830 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
831 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
832 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
833 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
834 -#define SSB_SPROM1_BINF 0x105C /* Board info */
835 +#define SSB_SPROM1_BINF 0x005C /* Board info */
836 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
837 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
838 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
839 @@ -197,63 +198,63 @@
840 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
841 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
842 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
843 -#define SSB_SPROM1_PA0B0 0x105E
844 -#define SSB_SPROM1_PA0B1 0x1060
845 -#define SSB_SPROM1_PA0B2 0x1062
846 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
847 +#define SSB_SPROM1_PA0B0 0x005E
848 +#define SSB_SPROM1_PA0B1 0x0060
849 +#define SSB_SPROM1_PA0B2 0x0062
850 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
851 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
852 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
853 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
854 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
855 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
856 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
857 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
858 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
859 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
860 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
861 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
862 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
863 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
864 -#define SSB_SPROM1_PA1B0 0x106A
865 -#define SSB_SPROM1_PA1B1 0x106C
866 -#define SSB_SPROM1_PA1B2 0x106E
867 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
868 +#define SSB_SPROM1_PA1B0 0x006A
869 +#define SSB_SPROM1_PA1B1 0x006C
870 +#define SSB_SPROM1_PA1B2 0x006E
871 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
872 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
873 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
874 #define SSB_SPROM1_ITSSI_A_SHIFT 8
875 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
876 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
877 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
878 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
879 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
880 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
881 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
882 #define SSB_SPROM1_AGAIN_A_SHIFT 8
883
884 /* SPROM Revision 2 (inherits from rev 1) */
885 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
886 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
887 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
888 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
889 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
890 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
891 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
892 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
893 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
894 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
895 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
896 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
897 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
898 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
899 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
900 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
901 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
902 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
903 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
904 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
905 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
906 #define SSB_SPROM2_OPO_VALUE 0x00FF
907 #define SSB_SPROM2_OPO_UNUSED 0xFF00
908 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
909 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
910
911 /* SPROM Revision 3 (inherits most data from rev 2) */
912 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
913 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
914 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
915 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
916 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
917 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
918 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
919 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
920 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
921 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
922 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
923 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
924 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
925 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
926 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
927 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
928 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
929 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
930 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
931 @@ -264,104 +265,156 @@
932 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
933
934 /* SPROM Revision 4 */
935 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
936 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
937 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
938 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
939 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
940 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
941 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
942 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
943 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
944 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
945 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
946 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
947 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
948 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
949 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
950 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
951 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
952 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
953 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
954 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
955 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
956 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
957 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
958 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
959 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
960 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
961 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
962 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
963 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
964 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
965 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
966 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
967 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
968 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
969 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
970 #define SSB_SPROM4_AGAIN0_SHIFT 0
971 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
972 #define SSB_SPROM4_AGAIN1_SHIFT 8
973 -#define SSB_SPROM4_AGAIN23 0x1060
974 +#define SSB_SPROM4_AGAIN23 0x0060
975 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
976 #define SSB_SPROM4_AGAIN2_SHIFT 0
977 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
978 #define SSB_SPROM4_AGAIN3_SHIFT 8
979 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
980 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
981 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
982 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
983 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
984 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
985 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
986 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
987 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
988 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
989 #define SSB_SPROM4_ITSSI_A_SHIFT 8
990 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
991 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
992 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
993 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
994 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
995 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
996 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
997 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
998 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
999 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
1000 -#define SSB_SPROM4_PA0B2 0x1086
1001 -#define SSB_SPROM4_PA1B0 0x108E
1002 -#define SSB_SPROM4_PA1B1 0x1090
1003 -#define SSB_SPROM4_PA1B2 0x1092
1004 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
1005 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
1006 +#define SSB_SPROM4_PA0B2 0x0086
1007 +#define SSB_SPROM4_PA1B0 0x008E
1008 +#define SSB_SPROM4_PA1B1 0x0090
1009 +#define SSB_SPROM4_PA1B2 0x0092
1010
1011 /* SPROM Revision 5 (inherits most data from rev 4) */
1012 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
1013 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
1014 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
1015 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
1016 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
1017 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
1018 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
1019 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
1020 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
1021 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
1022 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
1023 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
1024 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
1025 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
1026 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
1027 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
1028 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
1029 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
1030
1031 /* SPROM Revision 8 */
1032 -#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */
1033 -#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */
1034 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
1035 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
1036 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
1037 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1038 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1039 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1040 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1041 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
1042 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
1043 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
1044 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
1045 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
1046 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
1047 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
1048 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
1049 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
1050 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1051 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1052 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1053 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
1054 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1055 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1056 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1057 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
1058 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
1059 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
1060 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
1061 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
1062 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
1063 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
1064 #define SSB_SPROM8_AGAIN0_SHIFT 0
1065 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
1066 #define SSB_SPROM8_AGAIN1_SHIFT 8
1067 -#define SSB_SPROM8_AGAIN23 0x10A0
1068 +#define SSB_SPROM8_AGAIN23 0x00A0
1069 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
1070 #define SSB_SPROM8_AGAIN2_SHIFT 0
1071 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
1072 #define SSB_SPROM8_AGAIN3_SHIFT 8
1073 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
1074 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
1075 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
1076 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
1077 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
1078 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
1079 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
1080 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
1081 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */
1082 -#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
1083 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
1084 +#define SSB_SPROM8_RSSISMF2G 0x000F
1085 +#define SSB_SPROM8_RSSISMC2G 0x00F0
1086 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
1087 +#define SSB_SPROM8_RSSISAV2G 0x0700
1088 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
1089 +#define SSB_SPROM8_BXA2G 0x1800
1090 +#define SSB_SPROM8_BXA2G_SHIFT 11
1091 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
1092 +#define SSB_SPROM8_RSSISMF5G 0x000F
1093 +#define SSB_SPROM8_RSSISMC5G 0x00F0
1094 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
1095 +#define SSB_SPROM8_RSSISAV5G 0x0700
1096 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
1097 +#define SSB_SPROM8_BXA5G 0x1800
1098 +#define SSB_SPROM8_BXA5G_SHIFT 11
1099 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
1100 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
1101 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
1102 +#define SSB_SPROM8_TRI5G_SHIFT 8
1103 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
1104 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
1105 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
1106 +#define SSB_SPROM8_TRI5GH_SHIFT 8
1107 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
1108 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
1109 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
1110 +#define SSB_SPROM8_RXPO5G_SHIFT 8
1111 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
1112 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
1113 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
1114 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
1115 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */
1116 -#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
1117 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
1118 +#define SSB_SPROM8_PA0B1 0x00C4
1119 +#define SSB_SPROM8_PA0B2 0x00C6
1120 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
1121 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
1122 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
1123 #define SSB_SPROM8_ITSSI_A_SHIFT 8
1124 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
1125 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
1126 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
1127 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
1128 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
1129 +#define SSB_SPROM8_PA1B1 0x00CE
1130 +#define SSB_SPROM8_PA1B2 0x00D0
1131 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
1132 +#define SSB_SPROM8_PA1LOB1 0x00D4
1133 +#define SSB_SPROM8_PA1LOB2 0x00D6
1134 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
1135 +#define SSB_SPROM8_PA1HIB1 0x00DA
1136 +#define SSB_SPROM8_PA1HIB2 0x00DC
1137 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
1138 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
1139 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
1140 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
1141 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
1142
1143 /* Values for SSB_SPROM1_BINF_CCODE */
1144 enum {
1145 --- a/drivers/ssb/scan.c
1146 +++ b/drivers/ssb/scan.c
1147 @@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid)
1148 static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
1149 u16 offset)
1150 {
1151 + u32 lo, hi;
1152 +
1153 switch (bus->bustype) {
1154 case SSB_BUSTYPE_SSB:
1155 offset += current_coreidx * SSB_CORE_SIZE;
1156 @@ -174,6 +176,10 @@ static u32 scan_read32(struct ssb_bus *b
1157 offset -= 0x800;
1158 } else
1159 ssb_pcmcia_switch_segment(bus, 0);
1160 + lo = readw(bus->mmio + offset);
1161 + hi = readw(bus->mmio + offset + 2);
1162 + return lo | (hi << 16);
1163 + default:
1164 break;
1165 }
1166 return readl(bus->mmio + offset);
1167 @@ -188,6 +194,8 @@ static int scan_switchcore(struct ssb_bu
1168 return ssb_pci_switch_coreidx(bus, coreidx);
1169 case SSB_BUSTYPE_PCMCIA:
1170 return ssb_pcmcia_switch_coreidx(bus, coreidx);
1171 + default:
1172 + break;
1173 }
1174 return 0;
1175 }
1176 @@ -206,6 +214,8 @@ void ssb_iounmap(struct ssb_bus *bus)
1177 SSB_BUG_ON(1); /* Can't reach this code. */
1178 #endif
1179 break;
1180 + default:
1181 + break;
1182 }
1183 bus->mmio = NULL;
1184 bus->mapped_device = NULL;
1185 @@ -230,6 +240,8 @@ static void __iomem *ssb_ioremap(struct
1186 SSB_BUG_ON(1); /* Can't reach this code. */
1187 #endif
1188 break;
1189 + default:
1190 + break;
1191 }
1192
1193 return mmio;
1194 @@ -339,7 +351,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1195 dev->bus = bus;
1196 dev->ops = bus->ops;
1197
1198 - ssb_dprintk(KERN_INFO PFX
1199 + printk(KERN_DEBUG PFX
1200 "Core %d found: %s "
1201 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
1202 i, ssb_core_name(dev->id.coreid),
1203 --- a/drivers/ssb/driver_chipcommon.c
1204 +++ b/drivers/ssb/driver_chipcommon.c
1205 @@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip
1206 {
1207 if (!cc->dev)
1208 return; /* We don't have a ChipCommon */
1209 + if (cc->dev->id.revision >= 11)
1210 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
1211 ssb_pmu_init(cc);
1212 chipco_powercontrol_init(cc);
1213 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
1214 @@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
1215 {
1216 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
1217 }
1218 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
1219
1220 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
1221 {
1222 --- a/drivers/ssb/driver_mipscore.c
1223 +++ b/drivers/ssb/driver_mipscore.c
1224 @@ -49,29 +49,54 @@ static const u32 ipsflag_irq_shift[] = {
1225
1226 static inline u32 ssb_irqflag(struct ssb_device *dev)
1227 {
1228 - return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
1229 + u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
1230 + if (tpsflag)
1231 + return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
1232 + else
1233 + /* not irq supported */
1234 + return 0x3f;
1235 +}
1236 +
1237 +static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
1238 +{
1239 + struct ssb_bus *bus = rdev->bus;
1240 + int i;
1241 + for (i = 0; i < bus->nr_devices; i++) {
1242 + struct ssb_device *dev;
1243 + dev = &(bus->devices[i]);
1244 + if (ssb_irqflag(dev) == irqflag)
1245 + return dev;
1246 + }
1247 + return NULL;
1248 }
1249
1250 /* Get the MIPS IRQ assignment for a specified device.
1251 * If unassigned, 0 is returned.
1252 + * If disabled, 5 is returned.
1253 + * If not supported, 6 is returned.
1254 */
1255 unsigned int ssb_mips_irq(struct ssb_device *dev)
1256 {
1257 struct ssb_bus *bus = dev->bus;
1258 + struct ssb_device *mdev = bus->mipscore.dev;
1259 u32 irqflag;
1260 u32 ipsflag;
1261 u32 tmp;
1262 unsigned int irq;
1263
1264 irqflag = ssb_irqflag(dev);
1265 + if (irqflag == 0x3f)
1266 + return 6;
1267 ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
1268 for (irq = 1; irq <= 4; irq++) {
1269 tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
1270 if (tmp == irqflag)
1271 break;
1272 }
1273 - if (irq == 5)
1274 - irq = 0;
1275 + if (irq == 5) {
1276 + if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
1277 + irq = 0;
1278 + }
1279
1280 return irq;
1281 }
1282 @@ -97,25 +122,56 @@ static void set_irq(struct ssb_device *d
1283 struct ssb_device *mdev = bus->mipscore.dev;
1284 u32 irqflag = ssb_irqflag(dev);
1285
1286 + BUG_ON(oldirq == 6);
1287 +
1288 dev->irq = irq + 2;
1289
1290 - ssb_dprintk(KERN_INFO PFX
1291 - "set_irq: core 0x%04x, irq %d => %d\n",
1292 - dev->id.coreid, oldirq, irq);
1293 /* clear the old irq */
1294 if (oldirq == 0)
1295 ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
1296 - else
1297 + else if (oldirq != 5)
1298 clear_irq(bus, oldirq);
1299
1300 /* assign the new one */
1301 if (irq == 0) {
1302 ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
1303 } else {
1304 + u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
1305 + if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
1306 + u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
1307 + struct ssb_device *olddev = find_device(dev, oldipsflag);
1308 + if (olddev)
1309 + set_irq(olddev, 0);
1310 + }
1311 irqflag <<= ipsflag_irq_shift[irq];
1312 - irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
1313 + irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
1314 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
1315 }
1316 + ssb_dprintk(KERN_INFO PFX
1317 + "set_irq: core 0x%04x, irq %d => %d\n",
1318 + dev->id.coreid, oldirq+2, irq+2);
1319 +}
1320 +
1321 +static void print_irq(struct ssb_device *dev, unsigned int irq)
1322 +{
1323 + int i;
1324 + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
1325 + ssb_dprintk(KERN_INFO PFX
1326 + "core 0x%04x, irq :", dev->id.coreid);
1327 + for (i = 0; i <= 6; i++) {
1328 + ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
1329 + }
1330 + ssb_dprintk("\n");
1331 +}
1332 +
1333 +static void dump_irq(struct ssb_bus *bus)
1334 +{
1335 + int i;
1336 + for (i = 0; i < bus->nr_devices; i++) {
1337 + struct ssb_device *dev;
1338 + dev = &(bus->devices[i]);
1339 + print_irq(dev, ssb_mips_irq(dev));
1340 + }
1341 }
1342
1343 static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
1344 @@ -197,17 +253,23 @@ void ssb_mipscore_init(struct ssb_mipsco
1345
1346 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
1347 for (irq = 2, i = 0; i < bus->nr_devices; i++) {
1348 + int mips_irq;
1349 dev = &(bus->devices[i]);
1350 - dev->irq = ssb_mips_irq(dev) + 2;
1351 + mips_irq = ssb_mips_irq(dev);
1352 + if (mips_irq > 4)
1353 + dev->irq = 0;
1354 + else
1355 + dev->irq = mips_irq + 2;
1356 + if (dev->irq > 5)
1357 + continue;
1358 switch (dev->id.coreid) {
1359 case SSB_DEV_USB11_HOST:
1360 /* shouldn't need a separate irq line for non-4710, most of them have a proper
1361 * external usb controller on the pci */
1362 if ((bus->chip_id == 0x4710) && (irq <= 4)) {
1363 set_irq(dev, irq++);
1364 - break;
1365 }
1366 - /* fallthrough */
1367 + break;
1368 case SSB_DEV_PCI:
1369 case SSB_DEV_ETHERNET:
1370 case SSB_DEV_ETHERNET_GBIT:
1371 @@ -218,8 +280,14 @@ void ssb_mipscore_init(struct ssb_mipsco
1372 set_irq(dev, irq++);
1373 break;
1374 }
1375 + /* fallthrough */
1376 + case SSB_DEV_EXTIF:
1377 + set_irq(dev, 0);
1378 + break;
1379 }
1380 }
1381 + ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
1382 + dump_irq(bus);
1383
1384 ssb_mips_serial_init(mcore);
1385 ssb_mips_flash_detect(mcore);
1386 --- a/drivers/ssb/sprom.c
1387 +++ b/drivers/ssb/sprom.c
1388 @@ -13,6 +13,9 @@
1389
1390 #include "ssb_private.h"
1391
1392 +#include <linux/ctype.h>
1393 +#include <linux/slab.h>
1394 +
1395
1396 static const struct ssb_sprom *fallback_sprom;
1397
1398 @@ -33,17 +36,27 @@ static int sprom2hex(const u16 *sprom, c
1399 static int hex2sprom(u16 *sprom, const char *dump, size_t len,
1400 size_t sprom_size_words)
1401 {
1402 - char tmp[5] = { 0 };
1403 - int cnt = 0;
1404 + char c, tmp[5] = { 0 };
1405 + int err, cnt = 0;
1406 unsigned long parsed;
1407
1408 - if (len < sprom_size_words * 2)
1409 + /* Strip whitespace at the end. */
1410 + while (len) {
1411 + c = dump[len - 1];
1412 + if (!isspace(c) && c != '\0')
1413 + break;
1414 + len--;
1415 + }
1416 + /* Length must match exactly. */
1417 + if (len != sprom_size_words * 4)
1418 return -EINVAL;
1419
1420 while (cnt < sprom_size_words) {
1421 memcpy(tmp, dump, 4);
1422 dump += 4;
1423 - parsed = simple_strtoul(tmp, NULL, 16);
1424 + err = strict_strtoul(tmp, 16, &parsed);
1425 + if (err)
1426 + return err;
1427 sprom[cnt++] = swab16((u16)parsed);
1428 }
1429
1430 @@ -90,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1431 u16 *sprom;
1432 int res = 0, err = -ENOMEM;
1433 size_t sprom_size_words = bus->sprom_size;
1434 + struct ssb_freeze_context freeze;
1435
1436 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
1437 if (!sprom)
1438 @@ -111,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1439 err = -ERESTARTSYS;
1440 if (mutex_lock_interruptible(&bus->sprom_mutex))
1441 goto out_kfree;
1442 - err = ssb_devices_freeze(bus);
1443 - if (err == -EOPNOTSUPP) {
1444 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
1445 - "No suspend support. Is CONFIG_PM enabled?\n");
1446 - goto out_unlock;
1447 - }
1448 + err = ssb_devices_freeze(bus, &freeze);
1449 if (err) {
1450 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
1451 goto out_unlock;
1452 }
1453 res = sprom_write(bus, sprom);
1454 - err = ssb_devices_thaw(bus);
1455 + err = ssb_devices_thaw(&freeze);
1456 if (err)
1457 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
1458 out_unlock:
1459 @@ -167,3 +176,17 @@ const struct ssb_sprom *ssb_get_fallback
1460 {
1461 return fallback_sprom;
1462 }
1463 +
1464 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1465 +bool ssb_is_sprom_available(struct ssb_bus *bus)
1466 +{
1467 + /* status register only exists on chipcomon rev >= 11 and we need check
1468 + for >= 31 only */
1469 + /* this routine differs from specs as we do not access SPROM directly
1470 + on PCMCIA */
1471 + if (bus->bustype == SSB_BUSTYPE_PCI &&
1472 + bus->chipco.dev->id.revision >= 31)
1473 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1474 +
1475 + return true;
1476 +}
1477 --- a/drivers/ssb/ssb_private.h
1478 +++ b/drivers/ssb/ssb_private.h
1479 @@ -136,19 +136,27 @@ extern const struct ssb_sprom *ssb_get_f
1480
1481 /* core.c */
1482 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
1483 -extern int ssb_devices_freeze(struct ssb_bus *bus);
1484 -extern int ssb_devices_thaw(struct ssb_bus *bus);
1485 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
1486 int ssb_for_each_bus_call(unsigned long data,
1487 int (*func)(struct ssb_bus *bus, unsigned long data));
1488 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
1489
1490 +struct ssb_freeze_context {
1491 + /* Pointer to the bus */
1492 + struct ssb_bus *bus;
1493 + /* Boolean list to indicate whether a device is frozen on this bus. */
1494 + bool device_frozen[SSB_MAX_NR_CORES];
1495 +};
1496 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
1497 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
1498 +
1499 +
1500
1501 /* b43_pci_bridge.c */
1502 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
1503 extern int __init b43_pci_ssb_bridge_init(void);
1504 extern void __exit b43_pci_ssb_bridge_exit(void);
1505 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
1506 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
1507 static inline int b43_pci_ssb_bridge_init(void)
1508 {
1509 return 0;
1510 @@ -156,6 +164,6 @@ static inline int b43_pci_ssb_bridge_ini
1511 static inline void b43_pci_ssb_bridge_exit(void)
1512 {
1513 }
1514 -#endif /* CONFIG_SSB_PCIHOST */
1515 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
1516
1517 #endif /* LINUX_SSB_PRIVATE_H_ */