kernel: adm6996: add support for ADM6996L and GPIO interface
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / adm6996.h
1 /*
2 * ADM6996 switch driver
3 *
4 * Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (c) 2010,2011 Peter Lebbing <peter@digitalbrains.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License v2 as published by the
9 * Free Software Foundation
10 */
11 #ifndef __ADM6996_H
12 #define __ADM6996_H
13
14 /*
15 * ADM_PHY_PORTS: Number of ports with a PHY.
16 * We only control ports 0 to 3, because if 4 is connected, it is most likely
17 * not connected to the switch but to a separate MII and MAC for the WAN port.
18 */
19 #define ADM_PHY_PORTS 4
20 #define ADM_NUM_PORTS 6
21 #define ADM_CPU_PORT 5
22
23 #define ADM_NUM_VLANS 16
24 #define ADM_VLAN_MAX_ID 4094
25
26 enum admreg {
27 ADM_EEPROM_BASE = 0x0,
28 ADM_P0_CFG = ADM_EEPROM_BASE + 1,
29 ADM_P1_CFG = ADM_EEPROM_BASE + 3,
30 ADM_P2_CFG = ADM_EEPROM_BASE + 5,
31 ADM_P3_CFG = ADM_EEPROM_BASE + 7,
32 ADM_P4_CFG = ADM_EEPROM_BASE + 8,
33 ADM_P5_CFG = ADM_EEPROM_BASE + 9,
34 ADM_SYSC0 = ADM_EEPROM_BASE + 0xa,
35 ADM_VLAN_PRIOMAP = ADM_EEPROM_BASE + 0xe,
36 ADM_SYSC3 = ADM_EEPROM_BASE + 0x11,
37 /* Input Force No Tag Enable */
38 ADM_IFNTE = ADM_EEPROM_BASE + 0x20,
39 ADM_VID_CHECK = ADM_EEPROM_BASE + 0x26,
40 ADM_P0_PVID = ADM_EEPROM_BASE + 0x28,
41 ADM_P1_PVID = ADM_EEPROM_BASE + 0x29,
42 /* Output Tag Bypass Enable and P2 PVID */
43 ADM_OTBE_P2_PVID = ADM_EEPROM_BASE + 0x2a,
44 ADM_P3_P4_PVID = ADM_EEPROM_BASE + 0x2b,
45 ADM_P5_PVID = ADM_EEPROM_BASE + 0x2c,
46 ADM_EEPROM_EXT_BASE = 0x40,
47 #define ADM_VLAN_FILT_L(n) (ADM_EEPROM_EXT_BASE + 2 * (n))
48 #define ADM_VLAN_FILT_H(n) (ADM_EEPROM_EXT_BASE + 1 + 2 * (n))
49 #define ADM_VLAN_MAP(n) (ADM_EEPROM_BASE + 0x13 + n)
50 ADM_COUNTER_BASE = 0xa0,
51 ADM_SIG0 = ADM_COUNTER_BASE + 0,
52 ADM_SIG1 = ADM_COUNTER_BASE + 1,
53 ADM_PHY_BASE = 0x200,
54 #define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n))
55 };
56
57 /* Chip identification patterns */
58 #define ADM_SIG0_MASK 0xffff
59 #define ADM_SIG0_VAL 0x1023
60 #define ADM_SIG1_MASK 0xffff
61 #define ADM_SIG1_VAL 0x0007
62
63 enum {
64 ADM_PHYCFG_COLTST = (1 << 7), /* Enable collision test */
65 ADM_PHYCFG_DPLX = (1 << 8), /* Enable full duplex */
66 ADM_PHYCFG_ANEN_RST = (1 << 9), /* Restart auto negotiation (self clear) */
67 ADM_PHYCFG_ISO = (1 << 10), /* Isolate PHY */
68 ADM_PHYCFG_PDN = (1 << 11), /* Power down PHY */
69 ADM_PHYCFG_ANEN = (1 << 12), /* Enable auto negotiation */
70 ADM_PHYCFG_SPEED_100 = (1 << 13), /* Enable 100 Mbit/s */
71 ADM_PHYCFG_LPBK = (1 << 14), /* Enable loopback operation */
72 ADM_PHYCFG_RST = (1 << 15), /* Reset the port (self clear) */
73 ADM_PHYCFG_INIT = (
74 ADM_PHYCFG_RST |
75 ADM_PHYCFG_SPEED_100 |
76 ADM_PHYCFG_ANEN |
77 ADM_PHYCFG_ANEN_RST
78 )
79 };
80
81 enum {
82 ADM_PORTCFG_FC = (1 << 0), /* Enable 802.x flow control */
83 ADM_PORTCFG_AN = (1 << 1), /* Enable auto-negotiation */
84 ADM_PORTCFG_SPEED_100 = (1 << 2), /* Enable 100 Mbit/s */
85 ADM_PORTCFG_DPLX = (1 << 3), /* Enable full duplex */
86 ADM_PORTCFG_OT = (1 << 4), /* Output tagged packets */
87 ADM_PORTCFG_PD = (1 << 5), /* Port disable */
88 ADM_PORTCFG_TV_PRIO = (1 << 6), /* 0 = VLAN based priority
89 * 1 = TOS based priority */
90 ADM_PORTCFG_PPE = (1 << 7), /* Port based priority enable */
91 ADM_PORTCFG_PP_S = (1 << 8), /* Port based priority, 2 bits */
92 ADM_PORTCFG_PVID_BASE = (1 << 10), /* Primary VLAN id, 4 bits */
93 ADM_PORTCFG_FSE = (1 << 14), /* Fx select enable */
94 ADM_PORTCFG_CAM = (1 << 15), /* Crossover Auto MDIX */
95
96 ADM_PORTCFG_INIT = (
97 ADM_PORTCFG_FC |
98 ADM_PORTCFG_AN |
99 ADM_PORTCFG_SPEED_100 |
100 ADM_PORTCFG_DPLX |
101 ADM_PORTCFG_CAM
102 ),
103 ADM_PORTCFG_CPU = (
104 ADM_PORTCFG_FC |
105 ADM_PORTCFG_SPEED_100 |
106 ADM_PORTCFG_OT |
107 ADM_PORTCFG_DPLX
108 ),
109 };
110
111 #define ADM_PORTCFG_PPID(n) ((n & 0x3) << 8)
112 #define ADM_PORTCFG_PVID(n) ((n & 0xf) << 10)
113 #define ADM_PORTCFG_PVID_MASK (0xf << 10)
114
115 #define ADM_IFNTE_MASK (0x3f << 9)
116 #define ADM_VID_CHECK_MASK (0x3f << 6)
117
118 #define ADM_P0_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
119 #define ADM_P1_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
120 #define ADM_P2_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
121 #define ADM_P3_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
122 #define ADM_P4_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 8)
123 #define ADM_P5_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
124 #define ADM_P2_PVID_MASK 0xff
125
126 #define ADM_OTBE(n) (((n) & 0x3f) << 8)
127 #define ADM_OTBE_MASK (0x3f << 8)
128
129 /* ADM_SYSC0 */
130 enum {
131 ADM_NTTE = (1 << 2), /* New Tag Transmit Enable */
132 ADM_RVID1 = (1 << 8) /* Replace VLAN ID 1 */
133 };
134
135 /* Tag Based VLAN in ADM_SYSC3 */
136 #define ADM_MAC_CLONE BIT(4)
137 #define ADM_TBV BIT(5)
138
139 static const u8 adm_portcfg[] = {
140 [0] = ADM_P0_CFG,
141 [1] = ADM_P1_CFG,
142 [2] = ADM_P2_CFG,
143 [3] = ADM_P3_CFG,
144 [4] = ADM_P4_CFG,
145 [5] = ADM_P5_CFG,
146 };
147
148 /* Fields in ADM_VLAN_FILT_L(x) */
149 #define ADM_VLAN_FILT_FID(n) (((n) & 0xf) << 12)
150 #define ADM_VLAN_FILT_TAGGED(n) (((n) & 0x3f) << 6)
151 #define ADM_VLAN_FILT_MEMBER(n) (((n) & 0x3f) << 0)
152 #define ADM_VLAN_FILT_MEMBER_MASK 0x3f
153 /* Fields in ADM_VLAN_FILT_H(x) */
154 #define ADM_VLAN_FILT_VALID (1 << 15)
155 #define ADM_VLAN_FILT_VID(n) (((n) & 0xfff) << 0)
156
157 /* Convert ports to a form for ADM6996L VLAN map */
158 #define ADM_VLAN_FILT(ports) ((ports & 0x01) | ((ports & 0x02) << 1) | \
159 ((ports & 0x04) << 2) | ((ports & 0x08) << 3) | \
160 ((ports & 0x10) << 3) | ((ports & 0x20) << 3))
161
162 /*
163 * Split the register address in phy id and register
164 * it will get combined again by the mdio bus op
165 */
166 #define PHYADDR(_reg) ((_reg >> 5) & 0xff), (_reg & 0x1f)
167
168 #endif