target/linux/generic/files/drivers/net/phy/adm6996.h

   1 /*
   2  * ADM6996 switch driver
   3  *
   4  * Copyright (c) 2008 Felix Fietkau <nbd@nbd.name>
   5  * Copyright (c) 2010,2011 Peter Lebbing <peter@digitalbrains.com>
   6  *
   7  * This program is free software; you can redistribute  it and/or modify it
   8  * under  the terms of the GNU General Public License v2 as published by the
   9  * Free Software Foundation
  10  */
  11 #ifndef __ADM6996_H
  12 #define __ADM6996_H
  13
  14 /*
  15  * ADM_PHY_PORTS: Number of ports with a PHY.
  16  * We only control ports 0 to 3, because if 4 is connected, it is most likely
  17  * not connected to the switch but to a separate MII and MAC for the WAN port.
  18  */
  19 #define ADM_PHY_PORTS   4
  20 #define ADM_NUM_PORTS   6
  21 #define ADM_CPU_PORT    5
  22
  23 #define ADM_NUM_VLANS 16
  24 #define ADM_VLAN_MAX_ID 4094
  25
  26 enum admreg {
  27         ADM_EEPROM_BASE         = 0x0,
  28                 ADM_P0_CFG              = ADM_EEPROM_BASE + 1,
  29                 ADM_P1_CFG              = ADM_EEPROM_BASE + 3,
  30                 ADM_P2_CFG              = ADM_EEPROM_BASE + 5,
  31                 ADM_P3_CFG              = ADM_EEPROM_BASE + 7,
  32                 ADM_P4_CFG              = ADM_EEPROM_BASE + 8,
  33                 ADM_P5_CFG              = ADM_EEPROM_BASE + 9,
  34                 ADM_SYSC0               = ADM_EEPROM_BASE + 0xa,
  35                 ADM_VLAN_PRIOMAP        = ADM_EEPROM_BASE + 0xe,
  36                 ADM_SYSC3               = ADM_EEPROM_BASE + 0x11,
  37                 /* Input Force No Tag Enable */
  38                 ADM_IFNTE               = ADM_EEPROM_BASE + 0x20,
  39                 ADM_VID_CHECK           = ADM_EEPROM_BASE + 0x26,
  40                 ADM_P0_PVID             = ADM_EEPROM_BASE + 0x28,
  41                 ADM_P1_PVID             = ADM_EEPROM_BASE + 0x29,
  42                 /* Output Tag Bypass Enable and P2 PVID */
  43                 ADM_OTBE_P2_PVID        = ADM_EEPROM_BASE + 0x2a,
  44                 ADM_P3_P4_PVID          = ADM_EEPROM_BASE + 0x2b,
  45                 ADM_P5_PVID             = ADM_EEPROM_BASE + 0x2c,
  46         ADM_EEPROM_EXT_BASE     = 0x40,
  47 #define ADM_VLAN_FILT_L(n) (ADM_EEPROM_EXT_BASE + 2 * (n))
  48 #define ADM_VLAN_FILT_H(n) (ADM_EEPROM_EXT_BASE + 1 + 2 * (n))
  49 #define ADM_VLAN_MAP(n) (ADM_EEPROM_BASE + 0x13 + n)
  50         ADM_COUNTER_BASE        = 0xa0,
  51                 ADM_SIG0                = ADM_COUNTER_BASE + 0,
  52                 ADM_SIG1                = ADM_COUNTER_BASE + 1,
  53                 ADM_PS0         = ADM_COUNTER_BASE + 2,
  54                 ADM_PS1         = ADM_COUNTER_BASE + 3,
  55                 ADM_PS2         = ADM_COUNTER_BASE + 4,
  56                 ADM_CL0         = ADM_COUNTER_BASE + 8, /* RxPacket */
  57                 ADM_CL6         = ADM_COUNTER_BASE + 0x1a, /* RxByte */
  58                 ADM_CL12                = ADM_COUNTER_BASE + 0x2c, /* TxPacket */
  59                 ADM_CL18                = ADM_COUNTER_BASE + 0x3e, /* TxByte */
  60                 ADM_CL24                = ADM_COUNTER_BASE + 0x50, /* Coll */
  61                 ADM_CL30                = ADM_COUNTER_BASE + 0x62, /* Err */
  62 #define ADM_OFFSET_PORT(n) ((n * 4) - (n / 4) * 2 - (n / 5) * 2)
  63         ADM_PHY_BASE            = 0x200,
  64 #define ADM_PHY_PORT(n) (ADM_PHY_BASE + (0x20 * n))
  65 };
  66
  67 /* Chip identification patterns */
  68 #define ADM_SIG0_MASK   0xffff
  69 #define ADM_SIG0_VAL    0x1023
  70 #define ADM_SIG1_MASK   0xffff
  71 #define ADM_SIG1_VAL    0x0007
  72
  73 enum {
  74         ADM_PHYCFG_COLTST     = (1 << 7),       /* Enable collision test */
  75         ADM_PHYCFG_DPLX       = (1 << 8),       /* Enable full duplex */
  76         ADM_PHYCFG_ANEN_RST   = (1 << 9),       /* Restart auto negotiation (self clear) */
  77         ADM_PHYCFG_ISO        = (1 << 10),      /* Isolate PHY */
  78         ADM_PHYCFG_PDN        = (1 << 11),      /* Power down PHY */
  79         ADM_PHYCFG_ANEN       = (1 << 12),      /* Enable auto negotiation */
  80         ADM_PHYCFG_SPEED_100  = (1 << 13),      /* Enable 100 Mbit/s */
  81         ADM_PHYCFG_LPBK       = (1 << 14),      /* Enable loopback operation */
  82         ADM_PHYCFG_RST        = (1 << 15),      /* Reset the port (self clear) */
  83         ADM_PHYCFG_INIT = (
  84                 ADM_PHYCFG_RST |
  85                 ADM_PHYCFG_SPEED_100 |
  86                 ADM_PHYCFG_ANEN |
  87                 ADM_PHYCFG_ANEN_RST
  88         )
  89 };
  90
  91 enum {
  92         ADM_PORTCFG_FC        = (1 << 0),       /* Enable 802.x flow control */
  93         ADM_PORTCFG_AN        = (1 << 1),       /* Enable auto-negotiation */
  94         ADM_PORTCFG_SPEED_100 = (1 << 2),       /* Enable 100 Mbit/s */
  95         ADM_PORTCFG_DPLX      = (1 << 3),       /* Enable full duplex */
  96         ADM_PORTCFG_OT        = (1 << 4),       /* Output tagged packets */
  97         ADM_PORTCFG_PD        = (1 << 5),       /* Port disable */
  98         ADM_PORTCFG_TV_PRIO   = (1 << 6),       /* 0 = VLAN based priority
  99                                                  * 1 = TOS based priority */
 100         ADM_PORTCFG_PPE       = (1 << 7),       /* Port based priority enable */
 101         ADM_PORTCFG_PP_S      = (1 << 8),       /* Port based priority, 2 bits */
 102         ADM_PORTCFG_PVID_BASE = (1 << 10),      /* Primary VLAN id, 4 bits */
 103         ADM_PORTCFG_FSE       = (1 << 14),      /* Fx select enable */
 104         ADM_PORTCFG_CAM       = (1 << 15),      /* Crossover Auto MDIX */
 105
 106         ADM_PORTCFG_INIT = (
 107                 ADM_PORTCFG_FC |
 108                 ADM_PORTCFG_AN |
 109                 ADM_PORTCFG_SPEED_100 |
 110                 ADM_PORTCFG_DPLX |
 111                 ADM_PORTCFG_CAM
 112         ),
 113         ADM_PORTCFG_CPU = (
 114                 ADM_PORTCFG_FC |
 115                 ADM_PORTCFG_SPEED_100 |
 116                 ADM_PORTCFG_OT |
 117                 ADM_PORTCFG_DPLX
 118         ),
 119 };
 120
 121 #define ADM_PORTCFG_PPID(n) ((n & 0x3) << 8)
 122 #define ADM_PORTCFG_PVID(n) ((n & 0xf) << 10)
 123 #define ADM_PORTCFG_PVID_MASK (0xf << 10)
 124
 125 #define ADM_IFNTE_MASK (0x3f << 9)
 126 #define ADM_VID_CHECK_MASK (0x3f << 6)
 127
 128 #define ADM_P0_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
 129 #define ADM_P1_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
 130 #define ADM_P2_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
 131 #define ADM_P3_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
 132 #define ADM_P4_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 8)
 133 #define ADM_P5_PVID_VAL(n) ((((n) & 0xff0) >> 4) << 0)
 134 #define ADM_P2_PVID_MASK 0xff
 135
 136 #define ADM_OTBE(n) (((n) & 0x3f) << 8)
 137 #define ADM_OTBE_MASK (0x3f << 8)
 138
 139 /* ADM_SYSC0 */
 140 enum {
 141         ADM_NTTE        = (1 << 2),     /* New Tag Transmit Enable */
 142         ADM_RVID1       = (1 << 8)      /* Replace VLAN ID 1 */
 143 };
 144
 145 /* Tag Based VLAN in ADM_SYSC3 */
 146 #define ADM_MAC_CLONE   BIT(4)
 147 #define ADM_TBV         BIT(5)
 148
 149 static const u8 adm_portcfg[] = {
 150         [0] = ADM_P0_CFG,
 151         [1] = ADM_P1_CFG,
 152         [2] = ADM_P2_CFG,
 153         [3] = ADM_P3_CFG,
 154         [4] = ADM_P4_CFG,
 155         [5] = ADM_P5_CFG,
 156 };
 157
 158 /* Fields in ADM_VLAN_FILT_L(x) */
 159 #define ADM_VLAN_FILT_FID(n) (((n) & 0xf) << 12)
 160 #define ADM_VLAN_FILT_TAGGED(n) (((n) & 0x3f) << 6)
 161 #define ADM_VLAN_FILT_MEMBER(n) (((n) & 0x3f) << 0)
 162 #define ADM_VLAN_FILT_MEMBER_MASK 0x3f
 163 /* Fields in ADM_VLAN_FILT_H(x) */
 164 #define ADM_VLAN_FILT_VALID (1 << 15)
 165 #define ADM_VLAN_FILT_VID(n) (((n) & 0xfff) << 0)
 166
 167 /* Convert ports to a form for ADM6996L VLAN map */
 168 #define ADM_VLAN_FILT(ports) ((ports & 0x01) | ((ports & 0x02) << 1) | \
 169                         ((ports & 0x04) << 2) | ((ports & 0x08) << 3) | \
 170                         ((ports & 0x10) << 3) | ((ports & 0x20) << 3))
 171
 172 /* Port status register */
 173 enum {
 174         ADM_PS_LS = (1 << 0),   /* Link status */
 175         ADM_PS_SS = (1 << 1),   /* Speed status */
 176         ADM_PS_DS = (1 << 2),   /* Duplex status */
 177         ADM_PS_FCS = (1 << 3)   /* Flow control status */
 178 };
 179
 180 /*
 181  * Split the register address in phy id and register
 182  * it will get combined again by the mdio bus op
 183  */
 184 #define PHYADDR(_reg)   ((_reg >> 5) & 0xff), (_reg & 0x1f)
 185
 186 #endif