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ar8216: add swconfig attribute to display ARL table on AR8327/AR8337
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/version.h>
37
38 #include "ar8216.h"
39
40 extern const struct ar8xxx_chip ar8327_chip;
41 extern const struct ar8xxx_chip ar8337_chip;
42
43 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
44
45 #define MIB_DESC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 }
51
52 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
53 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
54 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
55 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
56 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
57 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
58 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
59 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
60 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
61 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
62 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
63 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
64 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
65 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
66 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
67 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
68 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
69 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
70 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
71 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
72 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
73 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
74 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
75 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
76 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
77 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
78 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
79 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
80 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
81 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
82 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
83 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
84 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
85 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
86 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
87 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
88 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
89 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
90 };
91
92 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
93 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
94 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
95 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
96 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
97 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
98 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
99 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
100 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
101 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
102 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
103 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
104 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
105 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
106 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
107 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
108 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
109 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
110 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
111 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
112 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
113 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
114 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
115 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
116 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
117 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
118 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
119 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
120 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
121 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
122 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
123 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
124 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
125 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
126 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
127 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
128 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
129 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
130 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
131 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
132 };
133
134 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
135 static LIST_HEAD(ar8xxx_dev_list);
136
137 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
138 static int
139 ar8xxx_phy_poll_reset(struct mii_bus *bus)
140 {
141 unsigned int sleep_msecs = 20;
142 int ret, elapsed, i;
143
144 for (elapsed = sleep_msecs; elapsed <= 600;
145 elapsed += sleep_msecs) {
146 msleep(sleep_msecs);
147 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
148 ret = mdiobus_read(bus, i, MII_BMCR);
149 if (ret < 0)
150 return ret;
151 if (ret & BMCR_RESET)
152 break;
153 if (i == AR8XXX_NUM_PHYS - 1) {
154 usleep_range(1000, 2000);
155 return 0;
156 }
157 }
158 }
159 return -ETIMEDOUT;
160 }
161
162 static int
163 ar8xxx_phy_check_aneg(struct phy_device *phydev)
164 {
165 int ret;
166
167 if (phydev->autoneg != AUTONEG_ENABLE)
168 return 0;
169 /*
170 * BMCR_ANENABLE might have been cleared
171 * by phy_init_hw in certain kernel versions
172 * therefore check for it
173 */
174 ret = phy_read(phydev, MII_BMCR);
175 if (ret < 0)
176 return ret;
177 if (ret & BMCR_ANENABLE)
178 return 0;
179
180 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
181 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
182 return phy_write(phydev, MII_BMCR, ret);
183 }
184
185 void
186 ar8xxx_phy_init(struct ar8xxx_priv *priv)
187 {
188 int i;
189 struct mii_bus *bus;
190
191 bus = priv->mii_bus;
192 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
193 if (priv->chip->phy_fixup)
194 priv->chip->phy_fixup(priv, i);
195
196 /* initialize the port itself */
197 mdiobus_write(bus, i, MII_ADVERTISE,
198 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
199 if (ar8xxx_has_gige(priv))
200 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
201 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
202 }
203
204 ar8xxx_phy_poll_reset(bus);
205 }
206
207 u32
208 mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
209 {
210 struct mii_bus *bus = priv->mii_bus;
211 u16 lo, hi;
212
213 lo = bus->read(bus, phy_id, regnum);
214 hi = bus->read(bus, phy_id, regnum + 1);
215
216 return (hi << 16) | lo;
217 }
218
219 void
220 mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
221 {
222 struct mii_bus *bus = priv->mii_bus;
223 u16 lo, hi;
224
225 lo = val & 0xffff;
226 hi = (u16) (val >> 16);
227
228 if (priv->chip->mii_lo_first)
229 {
230 bus->write(bus, phy_id, regnum, lo);
231 bus->write(bus, phy_id, regnum + 1, hi);
232 } else {
233 bus->write(bus, phy_id, regnum + 1, hi);
234 bus->write(bus, phy_id, regnum, lo);
235 }
236 }
237
238 u32
239 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
240 {
241 struct mii_bus *bus = priv->mii_bus;
242 u16 r1, r2, page;
243 u32 val;
244
245 split_addr((u32) reg, &r1, &r2, &page);
246
247 mutex_lock(&bus->mdio_lock);
248
249 bus->write(bus, 0x18, 0, page);
250 wait_for_page_switch();
251 val = mii_read32(priv, 0x10 | r2, r1);
252
253 mutex_unlock(&bus->mdio_lock);
254
255 return val;
256 }
257
258 void
259 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
260 {
261 struct mii_bus *bus = priv->mii_bus;
262 u16 r1, r2, page;
263
264 split_addr((u32) reg, &r1, &r2, &page);
265
266 mutex_lock(&bus->mdio_lock);
267
268 bus->write(bus, 0x18, 0, page);
269 wait_for_page_switch();
270 mii_write32(priv, 0x10 | r2, r1, val);
271
272 mutex_unlock(&bus->mdio_lock);
273 }
274
275 u32
276 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
277 {
278 struct mii_bus *bus = priv->mii_bus;
279 u16 r1, r2, page;
280 u32 ret;
281
282 split_addr((u32) reg, &r1, &r2, &page);
283
284 mutex_lock(&bus->mdio_lock);
285
286 bus->write(bus, 0x18, 0, page);
287 wait_for_page_switch();
288
289 ret = mii_read32(priv, 0x10 | r2, r1);
290 ret &= ~mask;
291 ret |= val;
292 mii_write32(priv, 0x10 | r2, r1, ret);
293
294 mutex_unlock(&bus->mdio_lock);
295
296 return ret;
297 }
298
299 void
300 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
301 u16 dbg_addr, u16 dbg_data)
302 {
303 struct mii_bus *bus = priv->mii_bus;
304
305 mutex_lock(&bus->mdio_lock);
306 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
307 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
308 mutex_unlock(&bus->mdio_lock);
309 }
310
311 void
312 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
313 {
314 struct mii_bus *bus = priv->mii_bus;
315
316 mutex_lock(&bus->mdio_lock);
317 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
318 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
319 mutex_unlock(&bus->mdio_lock);
320 }
321
322 u16
323 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr)
324 {
325 struct mii_bus *bus = priv->mii_bus;
326 u16 data;
327
328 mutex_lock(&bus->mdio_lock);
329 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
330 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
331 mutex_unlock(&bus->mdio_lock);
332
333 return data;
334 }
335
336 static int
337 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
338 unsigned timeout)
339 {
340 int i;
341
342 for (i = 0; i < timeout; i++) {
343 u32 t;
344
345 t = ar8xxx_read(priv, reg);
346 if ((t & mask) == val)
347 return 0;
348
349 usleep_range(1000, 2000);
350 }
351
352 return -ETIMEDOUT;
353 }
354
355 static int
356 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
357 {
358 unsigned mib_func = priv->chip->mib_func;
359 int ret;
360
361 lockdep_assert_held(&priv->mib_lock);
362
363 /* Capture the hardware statistics for all ports */
364 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
365
366 /* Wait for the capturing to complete. */
367 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
368 if (ret)
369 goto out;
370
371 ret = 0;
372
373 out:
374 return ret;
375 }
376
377 static int
378 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
379 {
380 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
381 }
382
383 static int
384 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
385 {
386 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
387 }
388
389 static void
390 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
391 {
392 unsigned int base;
393 u64 *mib_stats;
394 int i;
395
396 WARN_ON(port >= priv->dev.ports);
397
398 lockdep_assert_held(&priv->mib_lock);
399
400 base = priv->chip->reg_port_stats_start +
401 priv->chip->reg_port_stats_length * port;
402
403 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
404 for (i = 0; i < priv->chip->num_mibs; i++) {
405 const struct ar8xxx_mib_desc *mib;
406 u64 t;
407
408 mib = &priv->chip->mib_decs[i];
409 t = ar8xxx_read(priv, base + mib->offset);
410 if (mib->size == 2) {
411 u64 hi;
412
413 hi = ar8xxx_read(priv, base + mib->offset + 4);
414 t |= hi << 32;
415 }
416
417 if (flush)
418 mib_stats[i] = 0;
419 else
420 mib_stats[i] += t;
421 }
422 }
423
424 static void
425 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
426 struct switch_port_link *link)
427 {
428 u32 status;
429 u32 speed;
430
431 memset(link, '\0', sizeof(*link));
432
433 status = priv->chip->read_port_status(priv, port);
434
435 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
436 if (link->aneg) {
437 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
438 } else {
439 link->link = true;
440
441 if (priv->get_port_link) {
442 int err;
443
444 err = priv->get_port_link(port);
445 if (err >= 0)
446 link->link = !!err;
447 }
448 }
449
450 if (!link->link)
451 return;
452
453 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
454 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
455 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
456
457 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
458 link->eee = priv->chip->read_port_eee_status(priv, port);
459
460 speed = (status & AR8216_PORT_STATUS_SPEED) >>
461 AR8216_PORT_STATUS_SPEED_S;
462
463 switch (speed) {
464 case AR8216_PORT_SPEED_10M:
465 link->speed = SWITCH_PORT_SPEED_10;
466 break;
467 case AR8216_PORT_SPEED_100M:
468 link->speed = SWITCH_PORT_SPEED_100;
469 break;
470 case AR8216_PORT_SPEED_1000M:
471 link->speed = SWITCH_PORT_SPEED_1000;
472 break;
473 default:
474 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
475 break;
476 }
477 }
478
479 static struct sk_buff *
480 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
481 {
482 struct ar8xxx_priv *priv = dev->phy_ptr;
483 unsigned char *buf;
484
485 if (unlikely(!priv))
486 goto error;
487
488 if (!priv->vlan)
489 goto send;
490
491 if (unlikely(skb_headroom(skb) < 2)) {
492 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
493 goto error;
494 }
495
496 buf = skb_push(skb, 2);
497 buf[0] = 0x10;
498 buf[1] = 0x80;
499
500 send:
501 return skb;
502
503 error:
504 dev_kfree_skb_any(skb);
505 return NULL;
506 }
507
508 static void
509 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
510 {
511 struct ar8xxx_priv *priv;
512 unsigned char *buf;
513 int port, vlan;
514
515 priv = dev->phy_ptr;
516 if (!priv)
517 return;
518
519 /* don't strip the header if vlan mode is disabled */
520 if (!priv->vlan)
521 return;
522
523 /* strip header, get vlan id */
524 buf = skb->data;
525 skb_pull(skb, 2);
526
527 /* check for vlan header presence */
528 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
529 return;
530
531 port = buf[0] & 0xf;
532
533 /* no need to fix up packets coming from a tagged source */
534 if (priv->vlan_tagged & (1 << port))
535 return;
536
537 /* lookup port vid from local table, the switch passes an invalid vlan id */
538 vlan = priv->vlan_id[priv->pvid[port]];
539
540 buf[14 + 2] &= 0xf0;
541 buf[14 + 2] |= vlan >> 8;
542 buf[15 + 2] = vlan & 0xff;
543 }
544
545 int
546 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
547 {
548 int timeout = 20;
549 u32 t = 0;
550
551 while (1) {
552 t = ar8xxx_read(priv, reg);
553 if ((t & mask) == val)
554 return 0;
555
556 if (timeout-- <= 0)
557 break;
558
559 udelay(10);
560 }
561
562 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
563 (unsigned int) reg, t, mask, val);
564 return -ETIMEDOUT;
565 }
566
567 static void
568 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
569 {
570 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
571 return;
572 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
573 val &= AR8216_VTUDATA_MEMBER;
574 val |= AR8216_VTUDATA_VALID;
575 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
576 }
577 op |= AR8216_VTU_ACTIVE;
578 ar8xxx_write(priv, AR8216_REG_VTU, op);
579 }
580
581 static void
582 ar8216_vtu_flush(struct ar8xxx_priv *priv)
583 {
584 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
585 }
586
587 static void
588 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
589 {
590 u32 op;
591
592 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
593 ar8216_vtu_op(priv, op, port_mask);
594 }
595
596 static int
597 ar8216_atu_flush(struct ar8xxx_priv *priv)
598 {
599 int ret;
600
601 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
602 if (!ret)
603 ar8xxx_write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH |
604 AR8216_ATU_ACTIVE);
605
606 return ret;
607 }
608
609 static u32
610 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
611 {
612 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
613 }
614
615 static void
616 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
617 {
618 u32 header;
619 u32 egress, ingress;
620 u32 pvid;
621
622 if (priv->vlan) {
623 pvid = priv->vlan_id[priv->pvid[port]];
624 if (priv->vlan_tagged & (1 << port))
625 egress = AR8216_OUT_ADD_VLAN;
626 else
627 egress = AR8216_OUT_STRIP_VLAN;
628 ingress = AR8216_IN_SECURE;
629 } else {
630 pvid = port;
631 egress = AR8216_OUT_KEEP;
632 ingress = AR8216_IN_PORT_ONLY;
633 }
634
635 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
636 header = AR8216_PORT_CTRL_HEADER;
637 else
638 header = 0;
639
640 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
641 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
642 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
643 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
644 AR8216_PORT_CTRL_LEARN | header |
645 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
646 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
647
648 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
649 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
650 AR8216_PORT_VLAN_DEFAULT_ID,
651 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
652 (ingress << AR8216_PORT_VLAN_MODE_S) |
653 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
654 }
655
656 static int
657 ar8216_hw_init(struct ar8xxx_priv *priv)
658 {
659 if (priv->initialized)
660 return 0;
661
662 ar8xxx_phy_init(priv);
663
664 priv->initialized = true;
665 return 0;
666 }
667
668 static void
669 ar8216_init_globals(struct ar8xxx_priv *priv)
670 {
671 /* standard atheros magic */
672 ar8xxx_write(priv, 0x38, 0xc000050e);
673
674 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
675 AR8216_GCTRL_MTU, 1518 + 8 + 2);
676 }
677
678 static void
679 ar8216_init_port(struct ar8xxx_priv *priv, int port)
680 {
681 /* Enable port learning and tx */
682 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
683 AR8216_PORT_CTRL_LEARN |
684 (4 << AR8216_PORT_CTRL_STATE_S));
685
686 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
687
688 if (port == AR8216_PORT_CPU) {
689 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
690 AR8216_PORT_STATUS_LINK_UP |
691 (ar8xxx_has_gige(priv) ?
692 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
693 AR8216_PORT_STATUS_TXMAC |
694 AR8216_PORT_STATUS_RXMAC |
695 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
696 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
697 AR8216_PORT_STATUS_DUPLEX);
698 } else {
699 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
700 AR8216_PORT_STATUS_LINK_AUTO);
701 }
702 }
703
704 static void
705 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
706 {
707 u32 egress, ingress;
708 u32 pvid;
709
710 if (priv->vlan) {
711 pvid = priv->vlan_id[priv->pvid[port]];
712 if (priv->vlan_tagged & (1 << port))
713 egress = AR8216_OUT_ADD_VLAN;
714 else
715 egress = AR8216_OUT_STRIP_VLAN;
716 ingress = AR8216_IN_SECURE;
717 } else {
718 pvid = port;
719 egress = AR8216_OUT_KEEP;
720 ingress = AR8216_IN_PORT_ONLY;
721 }
722
723 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
724 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
725 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
726 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
727 AR8216_PORT_CTRL_LEARN |
728 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
729 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
730
731 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
732 AR8236_PORT_VLAN_DEFAULT_ID,
733 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
734
735 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
736 AR8236_PORT_VLAN2_VLAN_MODE |
737 AR8236_PORT_VLAN2_MEMBER,
738 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
739 (members << AR8236_PORT_VLAN2_MEMBER_S));
740 }
741
742 static void
743 ar8236_init_globals(struct ar8xxx_priv *priv)
744 {
745 /* enable jumbo frames */
746 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
747 AR8316_GCTRL_MTU, 9018 + 8 + 2);
748
749 /* enable cpu port to receive arp frames */
750 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
751 AR8236_ATU_CTRL_RES);
752
753 /* enable cpu port to receive multicast and broadcast frames */
754 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
755 AR8236_FM_CPU_BROADCAST_EN | AR8236_FM_CPU_BCAST_FWD_EN);
756
757 /* Enable MIB counters */
758 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
759 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
760 AR8236_MIB_EN);
761 }
762
763 static int
764 ar8316_hw_init(struct ar8xxx_priv *priv)
765 {
766 u32 val, newval;
767
768 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
769
770 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
771 if (priv->port4_phy) {
772 /* value taken from Ubiquiti RouterStation Pro */
773 newval = 0x81461bea;
774 pr_info("ar8316: Using port 4 as PHY\n");
775 } else {
776 newval = 0x01261be2;
777 pr_info("ar8316: Using port 4 as switch port\n");
778 }
779 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
780 /* value taken from AVM Fritz!Box 7390 sources */
781 newval = 0x010e5b71;
782 } else {
783 /* no known value for phy interface */
784 pr_err("ar8316: unsupported mii mode: %d.\n",
785 priv->phy->interface);
786 return -EINVAL;
787 }
788
789 if (val == newval)
790 goto out;
791
792 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
793
794 if (priv->port4_phy &&
795 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
796 /* work around for phy4 rgmii mode */
797 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
798 /* rx delay */
799 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
800 /* tx delay */
801 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
802 msleep(1000);
803 }
804
805 ar8xxx_phy_init(priv);
806
807 out:
808 priv->initialized = true;
809 return 0;
810 }
811
812 static void
813 ar8316_init_globals(struct ar8xxx_priv *priv)
814 {
815 /* standard atheros magic */
816 ar8xxx_write(priv, 0x38, 0xc000050e);
817
818 /* enable cpu port to receive multicast and broadcast frames */
819 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
820
821 /* enable jumbo frames */
822 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
823 AR8316_GCTRL_MTU, 9018 + 8 + 2);
824
825 /* Enable MIB counters */
826 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
827 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
828 AR8236_MIB_EN);
829 }
830
831 int
832 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
833 struct switch_val *val)
834 {
835 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
836 priv->vlan = !!val->value.i;
837 return 0;
838 }
839
840 int
841 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
842 struct switch_val *val)
843 {
844 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
845 val->value.i = priv->vlan;
846 return 0;
847 }
848
849
850 int
851 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
852 {
853 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
854
855 /* make sure no invalid PVIDs get set */
856
857 if (vlan >= dev->vlans)
858 return -EINVAL;
859
860 priv->pvid[port] = vlan;
861 return 0;
862 }
863
864 int
865 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
866 {
867 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
868 *vlan = priv->pvid[port];
869 return 0;
870 }
871
872 static int
873 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
874 struct switch_val *val)
875 {
876 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
877 priv->vlan_id[val->port_vlan] = val->value.i;
878 return 0;
879 }
880
881 static int
882 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
883 struct switch_val *val)
884 {
885 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
886 val->value.i = priv->vlan_id[val->port_vlan];
887 return 0;
888 }
889
890 int
891 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
892 struct switch_port_link *link)
893 {
894 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
895
896 ar8216_read_port_link(priv, port, link);
897 return 0;
898 }
899
900 static int
901 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
902 {
903 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
904 u8 ports = priv->vlan_table[val->port_vlan];
905 int i;
906
907 val->len = 0;
908 for (i = 0; i < dev->ports; i++) {
909 struct switch_port *p;
910
911 if (!(ports & (1 << i)))
912 continue;
913
914 p = &val->value.ports[val->len++];
915 p->id = i;
916 if (priv->vlan_tagged & (1 << i))
917 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
918 else
919 p->flags = 0;
920 }
921 return 0;
922 }
923
924 static int
925 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
926 {
927 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
928 u8 *vt = &priv->vlan_table[val->port_vlan];
929 int i, j;
930
931 *vt = 0;
932 for (i = 0; i < val->len; i++) {
933 struct switch_port *p = &val->value.ports[i];
934
935 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
936 priv->vlan_tagged |= (1 << p->id);
937 } else {
938 priv->vlan_tagged &= ~(1 << p->id);
939 priv->pvid[p->id] = val->port_vlan;
940
941 /* make sure that an untagged port does not
942 * appear in other vlans */
943 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
944 if (j == val->port_vlan)
945 continue;
946 priv->vlan_table[j] &= ~(1 << p->id);
947 }
948 }
949
950 *vt |= 1 << p->id;
951 }
952 return 0;
953 }
954
955 static void
956 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
957 {
958 int port;
959
960 /* reset all mirror registers */
961 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
962 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
963 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
964 for (port = 0; port < AR8216_NUM_PORTS; port++) {
965 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
966 AR8216_PORT_CTRL_MIRROR_RX);
967
968 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
969 AR8216_PORT_CTRL_MIRROR_TX);
970 }
971
972 /* now enable mirroring if necessary */
973 if (priv->source_port >= AR8216_NUM_PORTS ||
974 priv->monitor_port >= AR8216_NUM_PORTS ||
975 priv->source_port == priv->monitor_port) {
976 return;
977 }
978
979 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
980 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
981 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
982
983 if (priv->mirror_rx)
984 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
985 AR8216_PORT_CTRL_MIRROR_RX);
986
987 if (priv->mirror_tx)
988 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
989 AR8216_PORT_CTRL_MIRROR_TX);
990 }
991
992 int
993 ar8xxx_sw_hw_apply(struct switch_dev *dev)
994 {
995 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
996 u8 portmask[AR8X16_MAX_PORTS];
997 int i, j;
998
999 mutex_lock(&priv->reg_mutex);
1000 /* flush all vlan translation unit entries */
1001 priv->chip->vtu_flush(priv);
1002
1003 memset(portmask, 0, sizeof(portmask));
1004 if (!priv->init) {
1005 /* calculate the port destination masks and load vlans
1006 * into the vlan translation unit */
1007 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1008 u8 vp = priv->vlan_table[j];
1009
1010 if (!vp)
1011 continue;
1012
1013 for (i = 0; i < dev->ports; i++) {
1014 u8 mask = (1 << i);
1015 if (vp & mask)
1016 portmask[i] |= vp & ~mask;
1017 }
1018
1019 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1020 priv->vlan_table[j]);
1021 }
1022 } else {
1023 /* vlan disabled:
1024 * isolate all ports, but connect them to the cpu port */
1025 for (i = 0; i < dev->ports; i++) {
1026 if (i == AR8216_PORT_CPU)
1027 continue;
1028
1029 portmask[i] = 1 << AR8216_PORT_CPU;
1030 portmask[AR8216_PORT_CPU] |= (1 << i);
1031 }
1032 }
1033
1034 /* update the port destination mask registers and tag settings */
1035 for (i = 0; i < dev->ports; i++) {
1036 priv->chip->setup_port(priv, i, portmask[i]);
1037 }
1038
1039 priv->chip->set_mirror_regs(priv);
1040
1041 mutex_unlock(&priv->reg_mutex);
1042 return 0;
1043 }
1044
1045 int
1046 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1047 {
1048 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1049 const struct ar8xxx_chip *chip = priv->chip;
1050 int i;
1051
1052 mutex_lock(&priv->reg_mutex);
1053 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1054 offsetof(struct ar8xxx_priv, vlan));
1055
1056 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1057 priv->vlan_id[i] = i;
1058
1059 /* Configure all ports */
1060 for (i = 0; i < dev->ports; i++)
1061 chip->init_port(priv, i);
1062
1063 priv->mirror_rx = false;
1064 priv->mirror_tx = false;
1065 priv->source_port = 0;
1066 priv->monitor_port = 0;
1067
1068 chip->init_globals(priv);
1069
1070 mutex_unlock(&priv->reg_mutex);
1071
1072 return chip->sw_hw_apply(dev);
1073 }
1074
1075 int
1076 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1077 const struct switch_attr *attr,
1078 struct switch_val *val)
1079 {
1080 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1081 unsigned int len;
1082 int ret;
1083
1084 if (!ar8xxx_has_mib_counters(priv))
1085 return -EOPNOTSUPP;
1086
1087 mutex_lock(&priv->mib_lock);
1088
1089 len = priv->dev.ports * priv->chip->num_mibs *
1090 sizeof(*priv->mib_stats);
1091 memset(priv->mib_stats, '\0', len);
1092 ret = ar8xxx_mib_flush(priv);
1093 if (ret)
1094 goto unlock;
1095
1096 ret = 0;
1097
1098 unlock:
1099 mutex_unlock(&priv->mib_lock);
1100 return ret;
1101 }
1102
1103 int
1104 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1105 const struct switch_attr *attr,
1106 struct switch_val *val)
1107 {
1108 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1109
1110 mutex_lock(&priv->reg_mutex);
1111 priv->mirror_rx = !!val->value.i;
1112 priv->chip->set_mirror_regs(priv);
1113 mutex_unlock(&priv->reg_mutex);
1114
1115 return 0;
1116 }
1117
1118 int
1119 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1120 const struct switch_attr *attr,
1121 struct switch_val *val)
1122 {
1123 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1124 val->value.i = priv->mirror_rx;
1125 return 0;
1126 }
1127
1128 int
1129 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1130 const struct switch_attr *attr,
1131 struct switch_val *val)
1132 {
1133 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1134
1135 mutex_lock(&priv->reg_mutex);
1136 priv->mirror_tx = !!val->value.i;
1137 priv->chip->set_mirror_regs(priv);
1138 mutex_unlock(&priv->reg_mutex);
1139
1140 return 0;
1141 }
1142
1143 int
1144 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1145 const struct switch_attr *attr,
1146 struct switch_val *val)
1147 {
1148 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1149 val->value.i = priv->mirror_tx;
1150 return 0;
1151 }
1152
1153 int
1154 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1155 const struct switch_attr *attr,
1156 struct switch_val *val)
1157 {
1158 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1159
1160 mutex_lock(&priv->reg_mutex);
1161 priv->monitor_port = val->value.i;
1162 priv->chip->set_mirror_regs(priv);
1163 mutex_unlock(&priv->reg_mutex);
1164
1165 return 0;
1166 }
1167
1168 int
1169 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1170 const struct switch_attr *attr,
1171 struct switch_val *val)
1172 {
1173 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1174 val->value.i = priv->monitor_port;
1175 return 0;
1176 }
1177
1178 int
1179 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1180 const struct switch_attr *attr,
1181 struct switch_val *val)
1182 {
1183 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1184
1185 mutex_lock(&priv->reg_mutex);
1186 priv->source_port = val->value.i;
1187 priv->chip->set_mirror_regs(priv);
1188 mutex_unlock(&priv->reg_mutex);
1189
1190 return 0;
1191 }
1192
1193 int
1194 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1195 const struct switch_attr *attr,
1196 struct switch_val *val)
1197 {
1198 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1199 val->value.i = priv->source_port;
1200 return 0;
1201 }
1202
1203 int
1204 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1205 const struct switch_attr *attr,
1206 struct switch_val *val)
1207 {
1208 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1209 int port;
1210 int ret;
1211
1212 if (!ar8xxx_has_mib_counters(priv))
1213 return -EOPNOTSUPP;
1214
1215 port = val->port_vlan;
1216 if (port >= dev->ports)
1217 return -EINVAL;
1218
1219 mutex_lock(&priv->mib_lock);
1220 ret = ar8xxx_mib_capture(priv);
1221 if (ret)
1222 goto unlock;
1223
1224 ar8xxx_mib_fetch_port_stat(priv, port, true);
1225
1226 ret = 0;
1227
1228 unlock:
1229 mutex_unlock(&priv->mib_lock);
1230 return ret;
1231 }
1232
1233 int
1234 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1235 const struct switch_attr *attr,
1236 struct switch_val *val)
1237 {
1238 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1239 const struct ar8xxx_chip *chip = priv->chip;
1240 u64 *mib_stats;
1241 int port;
1242 int ret;
1243 char *buf = priv->buf;
1244 int i, len = 0;
1245
1246 if (!ar8xxx_has_mib_counters(priv))
1247 return -EOPNOTSUPP;
1248
1249 port = val->port_vlan;
1250 if (port >= dev->ports)
1251 return -EINVAL;
1252
1253 mutex_lock(&priv->mib_lock);
1254 ret = ar8xxx_mib_capture(priv);
1255 if (ret)
1256 goto unlock;
1257
1258 ar8xxx_mib_fetch_port_stat(priv, port, false);
1259
1260 len += snprintf(buf + len, sizeof(priv->buf) - len,
1261 "Port %d MIB counters\n",
1262 port);
1263
1264 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1265 for (i = 0; i < chip->num_mibs; i++)
1266 len += snprintf(buf + len, sizeof(priv->buf) - len,
1267 "%-12s: %llu\n",
1268 chip->mib_decs[i].name,
1269 mib_stats[i]);
1270
1271 val->value.s = buf;
1272 val->len = len;
1273
1274 ret = 0;
1275
1276 unlock:
1277 mutex_unlock(&priv->mib_lock);
1278 return ret;
1279 }
1280
1281 int
1282 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1283 const struct switch_attr *attr,
1284 struct switch_val *val)
1285 {
1286 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1287 struct mii_bus *bus = priv->mii_bus;
1288 const struct ar8xxx_chip *chip = priv->chip;
1289 char *buf = priv->arl_buf;
1290 int i, j, k, len = 0;
1291 struct arl_entry *a, *a1;
1292 u32 status;
1293
1294 if (!chip->get_arl_entry)
1295 return -EOPNOTSUPP;
1296
1297 mutex_lock(&priv->reg_mutex);
1298 mutex_lock(&bus->mdio_lock);
1299
1300 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1301
1302 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1303 a = &priv->arl_table[i];
1304 duplicate:
1305 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1306
1307 if (!status)
1308 break;
1309
1310 /* avoid duplicates
1311 * ARL table can include multiple valid entries
1312 * per MAC, just with differing status codes
1313 */
1314 for (j = 0; j < i; ++j) {
1315 a1 = &priv->arl_table[j];
1316 if (a->port == a1->port && !memcmp(a->mac, a1->mac, sizeof(a->mac)))
1317 goto duplicate;
1318 }
1319 }
1320
1321 mutex_unlock(&bus->mdio_lock);
1322
1323 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1324 "address resolution table\n");
1325
1326 if (i == AR8XXX_NUM_ARL_RECORDS)
1327 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1328 "Too many entries found, displaying the first %d only!\n",
1329 AR8XXX_NUM_ARL_RECORDS);
1330
1331 for (j = 0; j < priv->dev.ports; ++j) {
1332 for (k = 0; k < i; ++k) {
1333 a = &priv->arl_table[k];
1334 if (a->port != j)
1335 continue;
1336 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1337 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1338 j,
1339 a->mac[5], a->mac[4], a->mac[3],
1340 a->mac[2], a->mac[1], a->mac[0]);
1341 }
1342 }
1343
1344 val->value.s = buf;
1345 val->len = len;
1346
1347 mutex_unlock(&priv->reg_mutex);
1348
1349 return 0;
1350 }
1351
1352
1353 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1354 {
1355 .type = SWITCH_TYPE_INT,
1356 .name = "enable_vlan",
1357 .description = "Enable VLAN mode",
1358 .set = ar8xxx_sw_set_vlan,
1359 .get = ar8xxx_sw_get_vlan,
1360 .max = 1
1361 },
1362 {
1363 .type = SWITCH_TYPE_NOVAL,
1364 .name = "reset_mibs",
1365 .description = "Reset all MIB counters",
1366 .set = ar8xxx_sw_set_reset_mibs,
1367 },
1368 {
1369 .type = SWITCH_TYPE_INT,
1370 .name = "enable_mirror_rx",
1371 .description = "Enable mirroring of RX packets",
1372 .set = ar8xxx_sw_set_mirror_rx_enable,
1373 .get = ar8xxx_sw_get_mirror_rx_enable,
1374 .max = 1
1375 },
1376 {
1377 .type = SWITCH_TYPE_INT,
1378 .name = "enable_mirror_tx",
1379 .description = "Enable mirroring of TX packets",
1380 .set = ar8xxx_sw_set_mirror_tx_enable,
1381 .get = ar8xxx_sw_get_mirror_tx_enable,
1382 .max = 1
1383 },
1384 {
1385 .type = SWITCH_TYPE_INT,
1386 .name = "mirror_monitor_port",
1387 .description = "Mirror monitor port",
1388 .set = ar8xxx_sw_set_mirror_monitor_port,
1389 .get = ar8xxx_sw_get_mirror_monitor_port,
1390 .max = AR8216_NUM_PORTS - 1
1391 },
1392 {
1393 .type = SWITCH_TYPE_INT,
1394 .name = "mirror_source_port",
1395 .description = "Mirror source port",
1396 .set = ar8xxx_sw_set_mirror_source_port,
1397 .get = ar8xxx_sw_get_mirror_source_port,
1398 .max = AR8216_NUM_PORTS - 1
1399 },
1400 {
1401 .type = SWITCH_TYPE_STRING,
1402 .name = "arl_table",
1403 .description = "Get ARL table",
1404 .set = NULL,
1405 .get = ar8xxx_sw_get_arl_table,
1406 },
1407 };
1408
1409 const struct switch_attr ar8xxx_sw_attr_port[2] = {
1410 {
1411 .type = SWITCH_TYPE_NOVAL,
1412 .name = "reset_mib",
1413 .description = "Reset single port MIB counters",
1414 .set = ar8xxx_sw_set_port_reset_mib,
1415 },
1416 {
1417 .type = SWITCH_TYPE_STRING,
1418 .name = "mib",
1419 .description = "Get port's MIB counters",
1420 .set = NULL,
1421 .get = ar8xxx_sw_get_port_mib,
1422 },
1423 };
1424
1425 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
1426 {
1427 .type = SWITCH_TYPE_INT,
1428 .name = "vid",
1429 .description = "VLAN ID (0-4094)",
1430 .set = ar8xxx_sw_set_vid,
1431 .get = ar8xxx_sw_get_vid,
1432 .max = 4094,
1433 },
1434 };
1435
1436 static const struct switch_dev_ops ar8xxx_sw_ops = {
1437 .attr_global = {
1438 .attr = ar8xxx_sw_attr_globals,
1439 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1440 },
1441 .attr_port = {
1442 .attr = ar8xxx_sw_attr_port,
1443 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1444 },
1445 .attr_vlan = {
1446 .attr = ar8xxx_sw_attr_vlan,
1447 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1448 },
1449 .get_port_pvid = ar8xxx_sw_get_pvid,
1450 .set_port_pvid = ar8xxx_sw_set_pvid,
1451 .get_vlan_ports = ar8xxx_sw_get_ports,
1452 .set_vlan_ports = ar8xxx_sw_set_ports,
1453 .apply_config = ar8xxx_sw_hw_apply,
1454 .reset_switch = ar8xxx_sw_reset_switch,
1455 .get_port_link = ar8xxx_sw_get_port_link,
1456 };
1457
1458 static const struct ar8xxx_chip ar8216_chip = {
1459 .caps = AR8XXX_CAP_MIB_COUNTERS,
1460
1461 .reg_port_stats_start = 0x19000,
1462 .reg_port_stats_length = 0xa0,
1463
1464 .name = "Atheros AR8216",
1465 .ports = AR8216_NUM_PORTS,
1466 .vlans = AR8216_NUM_VLANS,
1467 .swops = &ar8xxx_sw_ops,
1468
1469 .hw_init = ar8216_hw_init,
1470 .init_globals = ar8216_init_globals,
1471 .init_port = ar8216_init_port,
1472 .setup_port = ar8216_setup_port,
1473 .read_port_status = ar8216_read_port_status,
1474 .atu_flush = ar8216_atu_flush,
1475 .vtu_flush = ar8216_vtu_flush,
1476 .vtu_load_vlan = ar8216_vtu_load_vlan,
1477 .set_mirror_regs = ar8216_set_mirror_regs,
1478 .sw_hw_apply = ar8xxx_sw_hw_apply,
1479
1480 .num_mibs = ARRAY_SIZE(ar8216_mibs),
1481 .mib_decs = ar8216_mibs,
1482 .mib_func = AR8216_REG_MIB_FUNC
1483 };
1484
1485 static const struct ar8xxx_chip ar8236_chip = {
1486 .caps = AR8XXX_CAP_MIB_COUNTERS,
1487
1488 .reg_port_stats_start = 0x20000,
1489 .reg_port_stats_length = 0x100,
1490
1491 .name = "Atheros AR8236",
1492 .ports = AR8216_NUM_PORTS,
1493 .vlans = AR8216_NUM_VLANS,
1494 .swops = &ar8xxx_sw_ops,
1495
1496 .hw_init = ar8216_hw_init,
1497 .init_globals = ar8236_init_globals,
1498 .init_port = ar8216_init_port,
1499 .setup_port = ar8236_setup_port,
1500 .read_port_status = ar8216_read_port_status,
1501 .atu_flush = ar8216_atu_flush,
1502 .vtu_flush = ar8216_vtu_flush,
1503 .vtu_load_vlan = ar8216_vtu_load_vlan,
1504 .set_mirror_regs = ar8216_set_mirror_regs,
1505 .sw_hw_apply = ar8xxx_sw_hw_apply,
1506
1507 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1508 .mib_decs = ar8236_mibs,
1509 .mib_func = AR8216_REG_MIB_FUNC
1510 };
1511
1512 static const struct ar8xxx_chip ar8316_chip = {
1513 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1514
1515 .reg_port_stats_start = 0x20000,
1516 .reg_port_stats_length = 0x100,
1517
1518 .name = "Atheros AR8316",
1519 .ports = AR8216_NUM_PORTS,
1520 .vlans = AR8X16_MAX_VLANS,
1521 .swops = &ar8xxx_sw_ops,
1522
1523 .hw_init = ar8316_hw_init,
1524 .init_globals = ar8316_init_globals,
1525 .init_port = ar8216_init_port,
1526 .setup_port = ar8216_setup_port,
1527 .read_port_status = ar8216_read_port_status,
1528 .atu_flush = ar8216_atu_flush,
1529 .vtu_flush = ar8216_vtu_flush,
1530 .vtu_load_vlan = ar8216_vtu_load_vlan,
1531 .set_mirror_regs = ar8216_set_mirror_regs,
1532 .sw_hw_apply = ar8xxx_sw_hw_apply,
1533
1534 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1535 .mib_decs = ar8236_mibs,
1536 .mib_func = AR8216_REG_MIB_FUNC
1537 };
1538
1539 static int
1540 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1541 {
1542 u32 val;
1543 u16 id;
1544 int i;
1545
1546 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1547 if (val == ~0)
1548 return -ENODEV;
1549
1550 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1551 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1552 u16 t;
1553
1554 val = ar8xxx_read(priv, AR8216_REG_CTRL);
1555 if (val == ~0)
1556 return -ENODEV;
1557
1558 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1559 if (t != id)
1560 return -ENODEV;
1561 }
1562
1563 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1564 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1565
1566 switch (priv->chip_ver) {
1567 case AR8XXX_VER_AR8216:
1568 priv->chip = &ar8216_chip;
1569 break;
1570 case AR8XXX_VER_AR8236:
1571 priv->chip = &ar8236_chip;
1572 break;
1573 case AR8XXX_VER_AR8316:
1574 priv->chip = &ar8316_chip;
1575 break;
1576 case AR8XXX_VER_AR8327:
1577 priv->chip = &ar8327_chip;
1578 break;
1579 case AR8XXX_VER_AR8337:
1580 priv->chip = &ar8337_chip;
1581 break;
1582 default:
1583 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1584 priv->chip_ver, priv->chip_rev);
1585
1586 return -ENODEV;
1587 }
1588
1589 return 0;
1590 }
1591
1592 static void
1593 ar8xxx_mib_work_func(struct work_struct *work)
1594 {
1595 struct ar8xxx_priv *priv;
1596 int err;
1597
1598 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1599
1600 mutex_lock(&priv->mib_lock);
1601
1602 err = ar8xxx_mib_capture(priv);
1603 if (err)
1604 goto next_port;
1605
1606 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1607
1608 next_port:
1609 priv->mib_next_port++;
1610 if (priv->mib_next_port >= priv->dev.ports)
1611 priv->mib_next_port = 0;
1612
1613 mutex_unlock(&priv->mib_lock);
1614 schedule_delayed_work(&priv->mib_work,
1615 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1616 }
1617
1618 static int
1619 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1620 {
1621 unsigned int len;
1622
1623 if (!ar8xxx_has_mib_counters(priv))
1624 return 0;
1625
1626 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1627
1628 len = priv->dev.ports * priv->chip->num_mibs *
1629 sizeof(*priv->mib_stats);
1630 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1631
1632 if (!priv->mib_stats)
1633 return -ENOMEM;
1634
1635 return 0;
1636 }
1637
1638 static void
1639 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1640 {
1641 if (!ar8xxx_has_mib_counters(priv))
1642 return;
1643
1644 schedule_delayed_work(&priv->mib_work,
1645 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1646 }
1647
1648 static void
1649 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1650 {
1651 if (!ar8xxx_has_mib_counters(priv))
1652 return;
1653
1654 cancel_delayed_work(&priv->mib_work);
1655 }
1656
1657 static struct ar8xxx_priv *
1658 ar8xxx_create(void)
1659 {
1660 struct ar8xxx_priv *priv;
1661
1662 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1663 if (priv == NULL)
1664 return NULL;
1665
1666 mutex_init(&priv->reg_mutex);
1667 mutex_init(&priv->mib_lock);
1668 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1669
1670 return priv;
1671 }
1672
1673 static void
1674 ar8xxx_free(struct ar8xxx_priv *priv)
1675 {
1676 if (priv->chip && priv->chip->cleanup)
1677 priv->chip->cleanup(priv);
1678
1679 kfree(priv->chip_data);
1680 kfree(priv->mib_stats);
1681 kfree(priv);
1682 }
1683
1684 static int
1685 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1686 {
1687 const struct ar8xxx_chip *chip;
1688 struct switch_dev *swdev;
1689 int ret;
1690
1691 ret = ar8xxx_id_chip(priv);
1692 if (ret)
1693 return ret;
1694
1695 chip = priv->chip;
1696
1697 swdev = &priv->dev;
1698 swdev->cpu_port = AR8216_PORT_CPU;
1699 swdev->name = chip->name;
1700 swdev->vlans = chip->vlans;
1701 swdev->ports = chip->ports;
1702 swdev->ops = chip->swops;
1703
1704 ret = ar8xxx_mib_init(priv);
1705 if (ret)
1706 return ret;
1707
1708 return 0;
1709 }
1710
1711 static int
1712 ar8xxx_start(struct ar8xxx_priv *priv)
1713 {
1714 int ret;
1715
1716 priv->init = true;
1717
1718 ret = priv->chip->hw_init(priv);
1719 if (ret)
1720 return ret;
1721
1722 ret = ar8xxx_sw_reset_switch(&priv->dev);
1723 if (ret)
1724 return ret;
1725
1726 priv->init = false;
1727
1728 ar8xxx_mib_start(priv);
1729
1730 return 0;
1731 }
1732
1733 static int
1734 ar8xxx_phy_config_init(struct phy_device *phydev)
1735 {
1736 struct ar8xxx_priv *priv = phydev->priv;
1737 struct net_device *dev = phydev->attached_dev;
1738 int ret;
1739
1740 if (WARN_ON(!priv))
1741 return -ENODEV;
1742
1743 if (priv->chip->config_at_probe)
1744 return ar8xxx_phy_check_aneg(phydev);
1745
1746 priv->phy = phydev;
1747
1748 if (phydev->addr != 0) {
1749 if (chip_is_ar8316(priv)) {
1750 /* switch device has been initialized, reinit */
1751 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1752 priv->initialized = false;
1753 priv->port4_phy = true;
1754 ar8316_hw_init(priv);
1755 return 0;
1756 }
1757
1758 return 0;
1759 }
1760
1761 ret = ar8xxx_start(priv);
1762 if (ret)
1763 return ret;
1764
1765 /* VID fixup only needed on ar8216 */
1766 if (chip_is_ar8216(priv)) {
1767 dev->phy_ptr = priv;
1768 dev->priv_flags |= IFF_NO_IP_ALIGN;
1769 dev->eth_mangle_rx = ar8216_mangle_rx;
1770 dev->eth_mangle_tx = ar8216_mangle_tx;
1771 }
1772
1773 return 0;
1774 }
1775
1776 static bool
1777 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
1778 {
1779 bool link_new, changed = false;
1780 u32 status;
1781 int i;
1782
1783 mutex_lock(&priv->reg_mutex);
1784
1785 for (i = 0; i < priv->dev.ports; i++) {
1786 status = priv->chip->read_port_status(priv, i);
1787 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
1788 if (link_new == priv->link_up[i])
1789 continue;
1790
1791 priv->link_up[i] = link_new;
1792 changed = true;
1793 dev_info(&priv->phy->dev, "Port %d is %s\n",
1794 i, link_new ? "up" : "down");
1795 }
1796
1797 if (changed)
1798 priv->chip->atu_flush(priv);
1799
1800 mutex_unlock(&priv->reg_mutex);
1801
1802 return changed;
1803 }
1804
1805 static int
1806 ar8xxx_phy_read_status(struct phy_device *phydev)
1807 {
1808 struct ar8xxx_priv *priv = phydev->priv;
1809 struct switch_port_link link;
1810
1811 /* check for link changes and flush ATU
1812 * if a change was detected
1813 */
1814 if (phydev->state == PHY_CHANGELINK)
1815 ar8xxx_check_link_states(priv);
1816
1817 if (phydev->addr != 0)
1818 return genphy_read_status(phydev);
1819
1820 ar8216_read_port_link(priv, phydev->addr, &link);
1821 phydev->link = !!link.link;
1822 if (!phydev->link)
1823 return 0;
1824
1825 switch (link.speed) {
1826 case SWITCH_PORT_SPEED_10:
1827 phydev->speed = SPEED_10;
1828 break;
1829 case SWITCH_PORT_SPEED_100:
1830 phydev->speed = SPEED_100;
1831 break;
1832 case SWITCH_PORT_SPEED_1000:
1833 phydev->speed = SPEED_1000;
1834 break;
1835 default:
1836 phydev->speed = 0;
1837 }
1838 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
1839
1840 phydev->state = PHY_RUNNING;
1841 netif_carrier_on(phydev->attached_dev);
1842 phydev->adjust_link(phydev->attached_dev);
1843
1844 return 0;
1845 }
1846
1847 static int
1848 ar8xxx_phy_config_aneg(struct phy_device *phydev)
1849 {
1850 if (phydev->addr == 0)
1851 return 0;
1852
1853 return genphy_config_aneg(phydev);
1854 }
1855
1856 static const u32 ar8xxx_phy_ids[] = {
1857 0x004dd033,
1858 0x004dd034, /* AR8327 */
1859 0x004dd036, /* AR8337 */
1860 0x004dd041,
1861 0x004dd042,
1862 0x004dd043, /* AR8236 */
1863 };
1864
1865 static bool
1866 ar8xxx_phy_match(u32 phy_id)
1867 {
1868 int i;
1869
1870 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
1871 if (phy_id == ar8xxx_phy_ids[i])
1872 return true;
1873
1874 return false;
1875 }
1876
1877 static bool
1878 ar8xxx_is_possible(struct mii_bus *bus)
1879 {
1880 unsigned i;
1881
1882 for (i = 0; i < 4; i++) {
1883 u32 phy_id;
1884
1885 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
1886 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
1887 if (!ar8xxx_phy_match(phy_id)) {
1888 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
1889 dev_name(&bus->dev), i, phy_id);
1890 return false;
1891 }
1892 }
1893
1894 return true;
1895 }
1896
1897 static int
1898 ar8xxx_phy_probe(struct phy_device *phydev)
1899 {
1900 struct ar8xxx_priv *priv;
1901 struct switch_dev *swdev;
1902 int ret;
1903
1904 /* skip PHYs at unused adresses */
1905 if (phydev->addr != 0 && phydev->addr != 4)
1906 return -ENODEV;
1907
1908 if (!ar8xxx_is_possible(phydev->bus))
1909 return -ENODEV;
1910
1911 mutex_lock(&ar8xxx_dev_list_lock);
1912 list_for_each_entry(priv, &ar8xxx_dev_list, list)
1913 if (priv->mii_bus == phydev->bus)
1914 goto found;
1915
1916 priv = ar8xxx_create();
1917 if (priv == NULL) {
1918 ret = -ENOMEM;
1919 goto unlock;
1920 }
1921
1922 priv->mii_bus = phydev->bus;
1923
1924 ret = ar8xxx_probe_switch(priv);
1925 if (ret)
1926 goto free_priv;
1927
1928 swdev = &priv->dev;
1929 swdev->alias = dev_name(&priv->mii_bus->dev);
1930 ret = register_switch(swdev, NULL);
1931 if (ret)
1932 goto free_priv;
1933
1934 pr_info("%s: %s rev. %u switch registered on %s\n",
1935 swdev->devname, swdev->name, priv->chip_rev,
1936 dev_name(&priv->mii_bus->dev));
1937
1938 found:
1939 priv->use_count++;
1940
1941 if (phydev->addr == 0) {
1942 if (ar8xxx_has_gige(priv)) {
1943 phydev->supported = SUPPORTED_1000baseT_Full;
1944 phydev->advertising = ADVERTISED_1000baseT_Full;
1945 } else {
1946 phydev->supported = SUPPORTED_100baseT_Full;
1947 phydev->advertising = ADVERTISED_100baseT_Full;
1948 }
1949
1950 if (priv->chip->config_at_probe) {
1951 priv->phy = phydev;
1952
1953 ret = ar8xxx_start(priv);
1954 if (ret)
1955 goto err_unregister_switch;
1956 }
1957 } else {
1958 if (ar8xxx_has_gige(priv)) {
1959 phydev->supported |= SUPPORTED_1000baseT_Full;
1960 phydev->advertising |= ADVERTISED_1000baseT_Full;
1961 }
1962 }
1963
1964 phydev->priv = priv;
1965
1966 list_add(&priv->list, &ar8xxx_dev_list);
1967
1968 mutex_unlock(&ar8xxx_dev_list_lock);
1969
1970 return 0;
1971
1972 err_unregister_switch:
1973 if (--priv->use_count)
1974 goto unlock;
1975
1976 unregister_switch(&priv->dev);
1977
1978 free_priv:
1979 ar8xxx_free(priv);
1980 unlock:
1981 mutex_unlock(&ar8xxx_dev_list_lock);
1982 return ret;
1983 }
1984
1985 static void
1986 ar8xxx_phy_detach(struct phy_device *phydev)
1987 {
1988 struct net_device *dev = phydev->attached_dev;
1989
1990 if (!dev)
1991 return;
1992
1993 dev->phy_ptr = NULL;
1994 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
1995 dev->eth_mangle_rx = NULL;
1996 dev->eth_mangle_tx = NULL;
1997 }
1998
1999 static void
2000 ar8xxx_phy_remove(struct phy_device *phydev)
2001 {
2002 struct ar8xxx_priv *priv = phydev->priv;
2003
2004 if (WARN_ON(!priv))
2005 return;
2006
2007 phydev->priv = NULL;
2008 if (--priv->use_count > 0)
2009 return;
2010
2011 mutex_lock(&ar8xxx_dev_list_lock);
2012 list_del(&priv->list);
2013 mutex_unlock(&ar8xxx_dev_list_lock);
2014
2015 unregister_switch(&priv->dev);
2016 ar8xxx_mib_stop(priv);
2017 ar8xxx_free(priv);
2018 }
2019
2020 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2021 static int
2022 ar8xxx_phy_soft_reset(struct phy_device *phydev)
2023 {
2024 /* we don't need an extra reset */
2025 return 0;
2026 }
2027 #endif
2028
2029 static struct phy_driver ar8xxx_phy_driver = {
2030 .phy_id = 0x004d0000,
2031 .name = "Atheros AR8216/AR8236/AR8316",
2032 .phy_id_mask = 0xffff0000,
2033 .features = PHY_BASIC_FEATURES,
2034 .probe = ar8xxx_phy_probe,
2035 .remove = ar8xxx_phy_remove,
2036 .detach = ar8xxx_phy_detach,
2037 .config_init = ar8xxx_phy_config_init,
2038 .config_aneg = ar8xxx_phy_config_aneg,
2039 .read_status = ar8xxx_phy_read_status,
2040 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
2041 .soft_reset = ar8xxx_phy_soft_reset,
2042 #endif
2043 .driver = { .owner = THIS_MODULE },
2044 };
2045
2046 int __init
2047 ar8xxx_init(void)
2048 {
2049 return phy_driver_register(&ar8xxx_phy_driver);
2050 }
2051
2052 void __exit
2053 ar8xxx_exit(void)
2054 {
2055 phy_driver_unregister(&ar8xxx_phy_driver);
2056 }
2057
2058 module_init(ar8xxx_init);
2059 module_exit(ar8xxx_exit);
2060 MODULE_LICENSE("GPL");
2061
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