ccc074fdec99b2046f932ffe6b7991812c8d4a81
[openwrt/svn-archive/archive.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37
38 #include "ar8216.h"
39
40 /* size of the vlan table */
41 #define AR8X16_MAX_VLANS 128
42 #define AR8X16_PROBE_RETRIES 10
43 #define AR8X16_MAX_PORTS 8
44
45 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
46
47 struct ar8xxx_priv;
48
49 #define AR8XXX_CAP_GIGE BIT(0)
50 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
51
52 enum {
53 AR8XXX_VER_AR8216 = 0x01,
54 AR8XXX_VER_AR8236 = 0x03,
55 AR8XXX_VER_AR8316 = 0x10,
56 AR8XXX_VER_AR8327 = 0x12,
57 };
58
59 struct ar8xxx_mib_desc {
60 unsigned int size;
61 unsigned int offset;
62 const char *name;
63 };
64
65 struct ar8xxx_chip {
66 unsigned long caps;
67
68 int (*hw_init)(struct ar8xxx_priv *priv);
69 void (*init_globals)(struct ar8xxx_priv *priv);
70 void (*init_port)(struct ar8xxx_priv *priv, int port);
71 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 egress,
72 u32 ingress, u32 members, u32 pvid);
73 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
74 int (*atu_flush)(struct ar8xxx_priv *priv);
75 void (*vtu_flush)(struct ar8xxx_priv *priv);
76 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
77
78 const struct ar8xxx_mib_desc *mib_decs;
79 unsigned num_mibs;
80 };
81
82 struct ar8327_data {
83 u32 port0_status;
84 u32 port6_status;
85 };
86
87 struct ar8xxx_priv {
88 struct switch_dev dev;
89 struct mii_bus *mii_bus;
90 struct phy_device *phy;
91 u32 (*read)(struct ar8xxx_priv *priv, int reg);
92 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
93 const struct net_device_ops *ndo_old;
94 struct net_device_ops ndo;
95 struct mutex reg_mutex;
96 u8 chip_ver;
97 u8 chip_rev;
98 const struct ar8xxx_chip *chip;
99 union {
100 struct ar8327_data ar8327;
101 } chip_data;
102 bool initialized;
103 bool port4_phy;
104 char buf[2048];
105
106 bool init;
107 bool mii_lo_first;
108
109 struct mutex mib_lock;
110 struct delayed_work mib_work;
111 int mib_next_port;
112 u64 *mib_stats;
113
114 struct list_head list;
115 unsigned int use_count;
116
117 /* all fields below are cleared on reset */
118 bool vlan;
119 u16 vlan_id[AR8X16_MAX_VLANS];
120 u8 vlan_table[AR8X16_MAX_VLANS];
121 u8 vlan_tagged;
122 u16 pvid[AR8X16_MAX_PORTS];
123 };
124
125 #define MIB_DESC(_s , _o, _n) \
126 { \
127 .size = (_s), \
128 .offset = (_o), \
129 .name = (_n), \
130 }
131
132 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
133 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
134 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
135 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
136 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
137 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
138 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
139 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
140 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
141 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
142 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
143 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
144 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
145 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
146 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
147 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
148 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
149 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
150 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
151 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
152 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
153 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
154 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
155 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
156 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
157 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
158 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
159 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
160 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
161 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
162 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
163 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
164 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
165 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
166 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
167 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
168 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
169 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
170 };
171
172 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
173 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
174 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
175 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
176 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
177 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
178 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
179 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
180 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
181 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
182 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
183 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
184 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
185 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
186 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
187 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
188 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
189 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
190 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
191 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
192 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
193 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
194 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
195 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
196 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
197 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
198 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
199 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
200 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
201 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
202 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
203 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
204 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
205 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
206 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
207 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
208 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
209 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
210 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
211 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
212 };
213
214 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
215 static LIST_HEAD(ar8xxx_dev_list);
216
217 static inline struct ar8xxx_priv *
218 swdev_to_ar8xxx(struct switch_dev *swdev)
219 {
220 return container_of(swdev, struct ar8xxx_priv, dev);
221 }
222
223 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
224 {
225 return priv->chip->caps & AR8XXX_CAP_GIGE;
226 }
227
228 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
229 {
230 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
231 }
232
233 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
234 {
235 return priv->chip_ver == AR8XXX_VER_AR8216;
236 }
237
238 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
239 {
240 return priv->chip_ver == AR8XXX_VER_AR8236;
241 }
242
243 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
244 {
245 return priv->chip_ver == AR8XXX_VER_AR8316;
246 }
247
248 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
249 {
250 return priv->chip_ver == AR8XXX_VER_AR8327;
251 }
252
253 static inline void
254 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
255 {
256 regaddr >>= 1;
257 *r1 = regaddr & 0x1e;
258
259 regaddr >>= 5;
260 *r2 = regaddr & 0x7;
261
262 regaddr >>= 3;
263 *page = regaddr & 0x1ff;
264 }
265
266 static u32
267 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
268 {
269 struct mii_bus *bus = priv->mii_bus;
270 u16 r1, r2, page;
271 u16 lo, hi;
272
273 split_addr((u32) reg, &r1, &r2, &page);
274
275 mutex_lock(&bus->mdio_lock);
276
277 bus->write(bus, 0x18, 0, page);
278 usleep_range(1000, 2000); /* wait for the page switch to propagate */
279 lo = bus->read(bus, 0x10 | r2, r1);
280 hi = bus->read(bus, 0x10 | r2, r1 + 1);
281
282 mutex_unlock(&bus->mdio_lock);
283
284 return (hi << 16) | lo;
285 }
286
287 static void
288 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
289 {
290 struct mii_bus *bus = priv->mii_bus;
291 u16 r1, r2, r3;
292 u16 lo, hi;
293
294 split_addr((u32) reg, &r1, &r2, &r3);
295 lo = val & 0xffff;
296 hi = (u16) (val >> 16);
297
298 mutex_lock(&bus->mdio_lock);
299
300 bus->write(bus, 0x18, 0, r3);
301 usleep_range(1000, 2000); /* wait for the page switch to propagate */
302 if (priv->mii_lo_first) {
303 bus->write(bus, 0x10 | r2, r1, lo);
304 bus->write(bus, 0x10 | r2, r1 + 1, hi);
305 } else {
306 bus->write(bus, 0x10 | r2, r1 + 1, hi);
307 bus->write(bus, 0x10 | r2, r1, lo);
308 }
309
310 mutex_unlock(&bus->mdio_lock);
311 }
312
313 static void
314 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
315 u16 dbg_addr, u16 dbg_data)
316 {
317 struct mii_bus *bus = priv->mii_bus;
318
319 mutex_lock(&bus->mdio_lock);
320 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
321 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
322 mutex_unlock(&bus->mdio_lock);
323 }
324
325 static void
326 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
327 {
328 struct mii_bus *bus = priv->mii_bus;
329
330 mutex_lock(&bus->mdio_lock);
331 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
332 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
333 mutex_unlock(&bus->mdio_lock);
334 }
335
336 static u32
337 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
338 {
339 u32 v;
340
341 lockdep_assert_held(&priv->reg_mutex);
342
343 v = priv->read(priv, reg);
344 v &= ~mask;
345 v |= val;
346 priv->write(priv, reg, v);
347
348 return v;
349 }
350
351 static inline void
352 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
353 {
354 u32 v;
355
356 lockdep_assert_held(&priv->reg_mutex);
357
358 v = priv->read(priv, reg);
359 v |= val;
360 priv->write(priv, reg, v);
361 }
362
363 static int
364 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
365 unsigned timeout)
366 {
367 int i;
368
369 for (i = 0; i < timeout; i++) {
370 u32 t;
371
372 t = priv->read(priv, reg);
373 if ((t & mask) == val)
374 return 0;
375
376 usleep_range(1000, 2000);
377 }
378
379 return -ETIMEDOUT;
380 }
381
382 static int
383 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
384 {
385 unsigned mib_func;
386 int ret;
387
388 lockdep_assert_held(&priv->mib_lock);
389
390 if (chip_is_ar8327(priv))
391 mib_func = AR8327_REG_MIB_FUNC;
392 else
393 mib_func = AR8216_REG_MIB_FUNC;
394
395 mutex_lock(&priv->reg_mutex);
396 /* Capture the hardware statistics for all ports */
397 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
398 mutex_unlock(&priv->reg_mutex);
399
400 /* Wait for the capturing to complete. */
401 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
402 if (ret)
403 goto out;
404
405 ret = 0;
406
407 out:
408 return ret;
409 }
410
411 static int
412 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
413 {
414 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
415 }
416
417 static int
418 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
419 {
420 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
421 }
422
423 static void
424 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
425 {
426 unsigned int base;
427 u64 *mib_stats;
428 int i;
429
430 WARN_ON(port >= priv->dev.ports);
431
432 lockdep_assert_held(&priv->mib_lock);
433
434 if (chip_is_ar8327(priv))
435 base = AR8327_REG_PORT_STATS_BASE(port);
436 else if (chip_is_ar8236(priv) ||
437 chip_is_ar8316(priv))
438 base = AR8236_REG_PORT_STATS_BASE(port);
439 else
440 base = AR8216_REG_PORT_STATS_BASE(port);
441
442 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
443 for (i = 0; i < priv->chip->num_mibs; i++) {
444 const struct ar8xxx_mib_desc *mib;
445 u64 t;
446
447 mib = &priv->chip->mib_decs[i];
448 t = priv->read(priv, base + mib->offset);
449 if (mib->size == 2) {
450 u64 hi;
451
452 hi = priv->read(priv, base + mib->offset + 4);
453 t |= hi << 32;
454 }
455
456 if (flush)
457 mib_stats[i] = 0;
458 else
459 mib_stats[i] += t;
460 }
461 }
462
463 static void
464 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
465 struct switch_port_link *link)
466 {
467 u32 status;
468 u32 speed;
469
470 memset(link, '\0', sizeof(*link));
471
472 status = priv->chip->read_port_status(priv, port);
473
474 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
475 if (link->aneg) {
476 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
477 if (!link->link)
478 return;
479 } else {
480 link->link = true;
481 }
482
483 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
484 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
485 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
486
487 speed = (status & AR8216_PORT_STATUS_SPEED) >>
488 AR8216_PORT_STATUS_SPEED_S;
489
490 switch (speed) {
491 case AR8216_PORT_SPEED_10M:
492 link->speed = SWITCH_PORT_SPEED_10;
493 break;
494 case AR8216_PORT_SPEED_100M:
495 link->speed = SWITCH_PORT_SPEED_100;
496 break;
497 case AR8216_PORT_SPEED_1000M:
498 link->speed = SWITCH_PORT_SPEED_1000;
499 break;
500 default:
501 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
502 break;
503 }
504 }
505
506 static struct sk_buff *
507 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
508 {
509 struct ar8xxx_priv *priv = dev->phy_ptr;
510 unsigned char *buf;
511
512 if (unlikely(!priv))
513 goto error;
514
515 if (!priv->vlan)
516 goto send;
517
518 if (unlikely(skb_headroom(skb) < 2)) {
519 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
520 goto error;
521 }
522
523 buf = skb_push(skb, 2);
524 buf[0] = 0x10;
525 buf[1] = 0x80;
526
527 send:
528 return skb;
529
530 error:
531 dev_kfree_skb_any(skb);
532 return NULL;
533 }
534
535 static void
536 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
537 {
538 struct ar8xxx_priv *priv;
539 unsigned char *buf;
540 int port, vlan;
541
542 priv = dev->phy_ptr;
543 if (!priv)
544 return;
545
546 /* don't strip the header if vlan mode is disabled */
547 if (!priv->vlan)
548 return;
549
550 /* strip header, get vlan id */
551 buf = skb->data;
552 skb_pull(skb, 2);
553
554 /* check for vlan header presence */
555 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
556 return;
557
558 port = buf[0] & 0xf;
559
560 /* no need to fix up packets coming from a tagged source */
561 if (priv->vlan_tagged & (1 << port))
562 return;
563
564 /* lookup port vid from local table, the switch passes an invalid vlan id */
565 vlan = priv->vlan_id[priv->pvid[port]];
566
567 buf[14 + 2] &= 0xf0;
568 buf[14 + 2] |= vlan >> 8;
569 buf[15 + 2] = vlan & 0xff;
570 }
571
572 static int
573 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
574 {
575 int timeout = 20;
576 u32 t = 0;
577
578 while (1) {
579 t = priv->read(priv, reg);
580 if ((t & mask) == val)
581 return 0;
582
583 if (timeout-- <= 0)
584 break;
585
586 udelay(10);
587 }
588
589 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
590 (unsigned int) reg, t, mask, val);
591 return -ETIMEDOUT;
592 }
593
594 static void
595 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
596 {
597 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
598 return;
599 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
600 val &= AR8216_VTUDATA_MEMBER;
601 val |= AR8216_VTUDATA_VALID;
602 priv->write(priv, AR8216_REG_VTU_DATA, val);
603 }
604 op |= AR8216_VTU_ACTIVE;
605 priv->write(priv, AR8216_REG_VTU, op);
606 }
607
608 static void
609 ar8216_vtu_flush(struct ar8xxx_priv *priv)
610 {
611 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
612 }
613
614 static void
615 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
616 {
617 u32 op;
618
619 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
620 ar8216_vtu_op(priv, op, port_mask);
621 }
622
623 static int
624 ar8216_atu_flush(struct ar8xxx_priv *priv)
625 {
626 int ret;
627
628 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
629 if (!ret)
630 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
631
632 return ret;
633 }
634
635 static u32
636 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
637 {
638 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
639 }
640
641 static void
642 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
643 u32 members, u32 pvid)
644 {
645 u32 header;
646
647 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
648 header = AR8216_PORT_CTRL_HEADER;
649 else
650 header = 0;
651
652 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
653 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
654 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
655 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
656 AR8216_PORT_CTRL_LEARN | header |
657 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
658 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
659
660 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
661 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
662 AR8216_PORT_VLAN_DEFAULT_ID,
663 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
664 (ingress << AR8216_PORT_VLAN_MODE_S) |
665 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
666 }
667
668 static int
669 ar8216_hw_init(struct ar8xxx_priv *priv)
670 {
671 return 0;
672 }
673
674 static void
675 ar8216_init_globals(struct ar8xxx_priv *priv)
676 {
677 /* standard atheros magic */
678 priv->write(priv, 0x38, 0xc000050e);
679
680 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
681 AR8216_GCTRL_MTU, 1518 + 8 + 2);
682 }
683
684 static void
685 ar8216_init_port(struct ar8xxx_priv *priv, int port)
686 {
687 /* Enable port learning and tx */
688 priv->write(priv, AR8216_REG_PORT_CTRL(port),
689 AR8216_PORT_CTRL_LEARN |
690 (4 << AR8216_PORT_CTRL_STATE_S));
691
692 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
693
694 if (port == AR8216_PORT_CPU) {
695 priv->write(priv, AR8216_REG_PORT_STATUS(port),
696 AR8216_PORT_STATUS_LINK_UP |
697 (ar8xxx_has_gige(priv) ?
698 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
699 AR8216_PORT_STATUS_TXMAC |
700 AR8216_PORT_STATUS_RXMAC |
701 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
702 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
703 AR8216_PORT_STATUS_DUPLEX);
704 } else {
705 priv->write(priv, AR8216_REG_PORT_STATUS(port),
706 AR8216_PORT_STATUS_LINK_AUTO);
707 }
708 }
709
710 static const struct ar8xxx_chip ar8216_chip = {
711 .caps = AR8XXX_CAP_MIB_COUNTERS,
712
713 .hw_init = ar8216_hw_init,
714 .init_globals = ar8216_init_globals,
715 .init_port = ar8216_init_port,
716 .setup_port = ar8216_setup_port,
717 .read_port_status = ar8216_read_port_status,
718 .atu_flush = ar8216_atu_flush,
719 .vtu_flush = ar8216_vtu_flush,
720 .vtu_load_vlan = ar8216_vtu_load_vlan,
721
722 .num_mibs = ARRAY_SIZE(ar8216_mibs),
723 .mib_decs = ar8216_mibs,
724 };
725
726 static void
727 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
728 u32 members, u32 pvid)
729 {
730 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
731 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
732 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
733 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
734 AR8216_PORT_CTRL_LEARN |
735 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
736 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
737
738 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
739 AR8236_PORT_VLAN_DEFAULT_ID,
740 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
741
742 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
743 AR8236_PORT_VLAN2_VLAN_MODE |
744 AR8236_PORT_VLAN2_MEMBER,
745 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
746 (members << AR8236_PORT_VLAN2_MEMBER_S));
747 }
748
749 static int
750 ar8236_hw_init(struct ar8xxx_priv *priv)
751 {
752 int i;
753 struct mii_bus *bus;
754
755 if (priv->initialized)
756 return 0;
757
758 /* Initialize the PHYs */
759 bus = priv->mii_bus;
760 for (i = 0; i < 5; i++) {
761 mdiobus_write(bus, i, MII_ADVERTISE,
762 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
763 ADVERTISE_PAUSE_ASYM);
764 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
765 }
766 msleep(1000);
767
768 priv->initialized = true;
769 return 0;
770 }
771
772 static void
773 ar8236_init_globals(struct ar8xxx_priv *priv)
774 {
775 /* enable jumbo frames */
776 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
777 AR8316_GCTRL_MTU, 9018 + 8 + 2);
778
779 /* Enable MIB counters */
780 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
781 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
782 AR8236_MIB_EN);
783 }
784
785 static const struct ar8xxx_chip ar8236_chip = {
786 .caps = AR8XXX_CAP_MIB_COUNTERS,
787 .hw_init = ar8236_hw_init,
788 .init_globals = ar8236_init_globals,
789 .init_port = ar8216_init_port,
790 .setup_port = ar8236_setup_port,
791 .read_port_status = ar8216_read_port_status,
792 .atu_flush = ar8216_atu_flush,
793 .vtu_flush = ar8216_vtu_flush,
794 .vtu_load_vlan = ar8216_vtu_load_vlan,
795
796 .num_mibs = ARRAY_SIZE(ar8236_mibs),
797 .mib_decs = ar8236_mibs,
798 };
799
800 static int
801 ar8316_hw_init(struct ar8xxx_priv *priv)
802 {
803 int i;
804 u32 val, newval;
805 struct mii_bus *bus;
806
807 val = priv->read(priv, AR8316_REG_POSTRIP);
808
809 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
810 if (priv->port4_phy) {
811 /* value taken from Ubiquiti RouterStation Pro */
812 newval = 0x81461bea;
813 pr_info("ar8316: Using port 4 as PHY\n");
814 } else {
815 newval = 0x01261be2;
816 pr_info("ar8316: Using port 4 as switch port\n");
817 }
818 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
819 /* value taken from AVM Fritz!Box 7390 sources */
820 newval = 0x010e5b71;
821 } else {
822 /* no known value for phy interface */
823 pr_err("ar8316: unsupported mii mode: %d.\n",
824 priv->phy->interface);
825 return -EINVAL;
826 }
827
828 if (val == newval)
829 goto out;
830
831 priv->write(priv, AR8316_REG_POSTRIP, newval);
832
833 if (priv->port4_phy &&
834 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
835 /* work around for phy4 rgmii mode */
836 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
837 /* rx delay */
838 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
839 /* tx delay */
840 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
841 msleep(1000);
842 }
843
844 /* Initialize the ports */
845 bus = priv->mii_bus;
846 for (i = 0; i < 5; i++) {
847 /* initialize the port itself */
848 mdiobus_write(bus, i, MII_ADVERTISE,
849 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
850 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
851 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
852 }
853
854 msleep(1000);
855
856 out:
857 priv->initialized = true;
858 return 0;
859 }
860
861 static void
862 ar8316_init_globals(struct ar8xxx_priv *priv)
863 {
864 /* standard atheros magic */
865 priv->write(priv, 0x38, 0xc000050e);
866
867 /* enable cpu port to receive multicast and broadcast frames */
868 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
869
870 /* enable jumbo frames */
871 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
872 AR8316_GCTRL_MTU, 9018 + 8 + 2);
873
874 /* Enable MIB counters */
875 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
876 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
877 AR8236_MIB_EN);
878 }
879
880 static const struct ar8xxx_chip ar8316_chip = {
881 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
882 .hw_init = ar8316_hw_init,
883 .init_globals = ar8316_init_globals,
884 .init_port = ar8216_init_port,
885 .setup_port = ar8216_setup_port,
886 .read_port_status = ar8216_read_port_status,
887 .atu_flush = ar8216_atu_flush,
888 .vtu_flush = ar8216_vtu_flush,
889 .vtu_load_vlan = ar8216_vtu_load_vlan,
890
891 .num_mibs = ARRAY_SIZE(ar8236_mibs),
892 .mib_decs = ar8236_mibs,
893 };
894
895 static u32
896 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
897 {
898 u32 t;
899
900 if (!cfg)
901 return 0;
902
903 t = 0;
904 switch (cfg->mode) {
905 case AR8327_PAD_NC:
906 break;
907
908 case AR8327_PAD_MAC2MAC_MII:
909 t = AR8327_PAD_MAC_MII_EN;
910 if (cfg->rxclk_sel)
911 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
912 if (cfg->txclk_sel)
913 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
914 break;
915
916 case AR8327_PAD_MAC2MAC_GMII:
917 t = AR8327_PAD_MAC_GMII_EN;
918 if (cfg->rxclk_sel)
919 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
920 if (cfg->txclk_sel)
921 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
922 break;
923
924 case AR8327_PAD_MAC_SGMII:
925 t = AR8327_PAD_SGMII_EN;
926
927 /*
928 * WAR for the QUalcomm Atheros AP136 board.
929 * It seems that RGMII TX/RX delay settings needs to be
930 * applied for SGMII mode as well, The ethernet is not
931 * reliable without this.
932 */
933 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
934 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
935 if (cfg->rxclk_delay_en)
936 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
937 if (cfg->txclk_delay_en)
938 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
939
940 if (cfg->sgmii_delay_en)
941 t |= AR8327_PAD_SGMII_DELAY_EN;
942
943 break;
944
945 case AR8327_PAD_MAC2PHY_MII:
946 t = AR8327_PAD_PHY_MII_EN;
947 if (cfg->rxclk_sel)
948 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
949 if (cfg->txclk_sel)
950 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
951 break;
952
953 case AR8327_PAD_MAC2PHY_GMII:
954 t = AR8327_PAD_PHY_GMII_EN;
955 if (cfg->pipe_rxclk_sel)
956 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
957 if (cfg->rxclk_sel)
958 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
959 if (cfg->txclk_sel)
960 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
961 break;
962
963 case AR8327_PAD_MAC_RGMII:
964 t = AR8327_PAD_RGMII_EN;
965 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
966 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
967 if (cfg->rxclk_delay_en)
968 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
969 if (cfg->txclk_delay_en)
970 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
971 break;
972
973 case AR8327_PAD_PHY_GMII:
974 t = AR8327_PAD_PHYX_GMII_EN;
975 break;
976
977 case AR8327_PAD_PHY_RGMII:
978 t = AR8327_PAD_PHYX_RGMII_EN;
979 break;
980
981 case AR8327_PAD_PHY_MII:
982 t = AR8327_PAD_PHYX_MII_EN;
983 break;
984 }
985
986 return t;
987 }
988
989 static void
990 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
991 {
992 switch (priv->chip_rev) {
993 case 1:
994 /* For 100M waveform */
995 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
996 /* Turn on Gigabit clock */
997 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
998 break;
999
1000 case 2:
1001 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1002 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1003 /* fallthrough */
1004 case 4:
1005 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1006 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1007
1008 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1009 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1010 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1011 break;
1012 }
1013 }
1014
1015 static u32
1016 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1017 {
1018 u32 t;
1019
1020 if (!cfg->force_link)
1021 return AR8216_PORT_STATUS_LINK_AUTO;
1022
1023 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1024 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1025 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1026 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1027
1028 switch (cfg->speed) {
1029 case AR8327_PORT_SPEED_10:
1030 t |= AR8216_PORT_SPEED_10M;
1031 break;
1032 case AR8327_PORT_SPEED_100:
1033 t |= AR8216_PORT_SPEED_100M;
1034 break;
1035 case AR8327_PORT_SPEED_1000:
1036 t |= AR8216_PORT_SPEED_1000M;
1037 break;
1038 }
1039
1040 return t;
1041 }
1042
1043 static int
1044 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1045 struct ar8327_platform_data *pdata)
1046 {
1047 struct ar8327_led_cfg *led_cfg;
1048 struct ar8327_data *data;
1049 u32 pos, new_pos;
1050 u32 t;
1051
1052 if (!pdata)
1053 return -EINVAL;
1054
1055 data = &priv->chip_data.ar8327;
1056
1057 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1058 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1059
1060 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1061 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1062 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1063 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1064 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1065 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1066
1067 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1068 new_pos = pos;
1069
1070 led_cfg = pdata->led_cfg;
1071 if (led_cfg) {
1072 if (led_cfg->open_drain)
1073 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1074 else
1075 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1076
1077 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1078 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1079 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1080 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1081 }
1082
1083 if (new_pos != pos) {
1084 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1085 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1086 }
1087
1088 return 0;
1089 }
1090
1091 #ifdef CONFIG_OF
1092 static int
1093 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1094 {
1095 const __be32 *paddr;
1096 int len;
1097 int i;
1098
1099 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1100 if (!paddr || len < (2 * sizeof(*paddr)))
1101 return -EINVAL;
1102
1103 len /= sizeof(*paddr);
1104
1105 for (i = 0; i < len - 1; i += 2) {
1106 u32 reg;
1107 u32 val;
1108
1109 reg = be32_to_cpup(paddr + i);
1110 val = be32_to_cpup(paddr + i + 1);
1111
1112 switch (reg) {
1113 case AR8327_REG_PORT_STATUS(0):
1114 priv->chip_data.ar8327.port0_status = val;
1115 break;
1116 case AR8327_REG_PORT_STATUS(6):
1117 priv->chip_data.ar8327.port6_status = val;
1118 break;
1119 default:
1120 priv->write(priv, reg, val);
1121 break;
1122 }
1123 }
1124
1125 return 0;
1126 }
1127 #else
1128 static inline int
1129 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1130 {
1131 return -EINVAL;
1132 }
1133 #endif
1134
1135 static int
1136 ar8327_hw_init(struct ar8xxx_priv *priv)
1137 {
1138 struct mii_bus *bus;
1139 int ret;
1140 int i;
1141
1142 if (priv->phy->dev.of_node)
1143 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1144 else
1145 ret = ar8327_hw_config_pdata(priv,
1146 priv->phy->dev.platform_data);
1147
1148 if (ret)
1149 return ret;
1150
1151 bus = priv->mii_bus;
1152 for (i = 0; i < AR8327_NUM_PHYS; i++) {
1153 ar8327_phy_fixup(priv, i);
1154
1155 /* start aneg on the PHY */
1156 mdiobus_write(bus, i, MII_ADVERTISE, ADVERTISE_ALL |
1157 ADVERTISE_PAUSE_CAP |
1158 ADVERTISE_PAUSE_ASYM);
1159 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
1160 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1161 }
1162
1163 msleep(1000);
1164
1165 return 0;
1166 }
1167
1168 static void
1169 ar8327_init_globals(struct ar8xxx_priv *priv)
1170 {
1171 u32 t;
1172
1173 /* enable CPU port and disable mirror port */
1174 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1175 AR8327_FWD_CTRL0_MIRROR_PORT;
1176 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1177
1178 /* forward multicast and broadcast frames to CPU */
1179 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1180 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1181 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1182 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1183
1184 /* setup MTU */
1185 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1186 AR8327_MAX_FRAME_SIZE_MTU, 1518 + 8 + 2);
1187
1188 /* Enable MIB counters */
1189 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1190 AR8327_MODULE_EN_MIB);
1191 }
1192
1193 static void
1194 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1195 {
1196 u32 t;
1197
1198 if (port == AR8216_PORT_CPU)
1199 t = priv->chip_data.ar8327.port0_status;
1200 else if (port == 6)
1201 t = priv->chip_data.ar8327.port6_status;
1202 else
1203 t = AR8216_PORT_STATUS_LINK_AUTO;
1204
1205 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1206 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1207
1208 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1209 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1210 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1211
1212 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1213 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1214
1215 t = AR8327_PORT_LOOKUP_LEARN;
1216 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1217 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1218 }
1219
1220 static u32
1221 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1222 {
1223 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1224 }
1225
1226 static int
1227 ar8327_atu_flush(struct ar8xxx_priv *priv)
1228 {
1229 int ret;
1230
1231 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1232 AR8327_ATU_FUNC_BUSY, 0);
1233 if (!ret)
1234 priv->write(priv, AR8327_REG_ATU_FUNC,
1235 AR8327_ATU_FUNC_OP_FLUSH);
1236
1237 return ret;
1238 }
1239
1240 static void
1241 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1242 {
1243 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1244 AR8327_VTU_FUNC1_BUSY, 0))
1245 return;
1246
1247 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1248 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1249
1250 op |= AR8327_VTU_FUNC1_BUSY;
1251 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1252 }
1253
1254 static void
1255 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1256 {
1257 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1258 }
1259
1260 static void
1261 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1262 {
1263 u32 op;
1264 u32 val;
1265 int i;
1266
1267 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1268 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1269 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1270 u32 mode;
1271
1272 if ((port_mask & BIT(i)) == 0)
1273 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1274 else if (priv->vlan == 0)
1275 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1276 else if (priv->vlan_tagged & BIT(i))
1277 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1278 else
1279 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1280
1281 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1282 }
1283 ar8327_vtu_op(priv, op, val);
1284 }
1285
1286 static void
1287 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 egress, u32 ingress,
1288 u32 members, u32 pvid)
1289 {
1290 u32 t;
1291 u32 mode;
1292
1293 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1294 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1295 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1296
1297 mode = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1298 switch (egress) {
1299 case AR8216_OUT_KEEP:
1300 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1301 break;
1302 case AR8216_OUT_STRIP_VLAN:
1303 mode = AR8327_PORT_VLAN1_OUT_MODE_UNTAG;
1304 break;
1305 case AR8216_OUT_ADD_VLAN:
1306 mode = AR8327_PORT_VLAN1_OUT_MODE_TAG;
1307 break;
1308 }
1309
1310 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1311 t |= mode << AR8327_PORT_VLAN1_OUT_MODE_S;
1312 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1313
1314 t = members;
1315 t |= AR8327_PORT_LOOKUP_LEARN;
1316 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1317 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1318 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1319 }
1320
1321 static const struct ar8xxx_chip ar8327_chip = {
1322 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1323 .hw_init = ar8327_hw_init,
1324 .init_globals = ar8327_init_globals,
1325 .init_port = ar8327_init_port,
1326 .setup_port = ar8327_setup_port,
1327 .read_port_status = ar8327_read_port_status,
1328 .atu_flush = ar8327_atu_flush,
1329 .vtu_flush = ar8327_vtu_flush,
1330 .vtu_load_vlan = ar8327_vtu_load_vlan,
1331
1332 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1333 .mib_decs = ar8236_mibs,
1334 };
1335
1336 static int
1337 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1338 struct switch_val *val)
1339 {
1340 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1341 priv->vlan = !!val->value.i;
1342 return 0;
1343 }
1344
1345 static int
1346 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1347 struct switch_val *val)
1348 {
1349 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1350 val->value.i = priv->vlan;
1351 return 0;
1352 }
1353
1354
1355 static int
1356 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1357 {
1358 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1359
1360 /* make sure no invalid PVIDs get set */
1361
1362 if (vlan >= dev->vlans)
1363 return -EINVAL;
1364
1365 priv->pvid[port] = vlan;
1366 return 0;
1367 }
1368
1369 static int
1370 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1371 {
1372 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1373 *vlan = priv->pvid[port];
1374 return 0;
1375 }
1376
1377 static int
1378 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1379 struct switch_val *val)
1380 {
1381 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1382 priv->vlan_id[val->port_vlan] = val->value.i;
1383 return 0;
1384 }
1385
1386 static int
1387 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1388 struct switch_val *val)
1389 {
1390 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1391 val->value.i = priv->vlan_id[val->port_vlan];
1392 return 0;
1393 }
1394
1395 static int
1396 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1397 struct switch_port_link *link)
1398 {
1399 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1400
1401 ar8216_read_port_link(priv, port, link);
1402 return 0;
1403 }
1404
1405 static int
1406 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1407 {
1408 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1409 u8 ports = priv->vlan_table[val->port_vlan];
1410 int i;
1411
1412 val->len = 0;
1413 for (i = 0; i < dev->ports; i++) {
1414 struct switch_port *p;
1415
1416 if (!(ports & (1 << i)))
1417 continue;
1418
1419 p = &val->value.ports[val->len++];
1420 p->id = i;
1421 if (priv->vlan_tagged & (1 << i))
1422 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1423 else
1424 p->flags = 0;
1425 }
1426 return 0;
1427 }
1428
1429 static int
1430 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1431 {
1432 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1433 u8 *vt = &priv->vlan_table[val->port_vlan];
1434 int i, j;
1435
1436 *vt = 0;
1437 for (i = 0; i < val->len; i++) {
1438 struct switch_port *p = &val->value.ports[i];
1439
1440 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1441 priv->vlan_tagged |= (1 << p->id);
1442 } else {
1443 priv->vlan_tagged &= ~(1 << p->id);
1444 priv->pvid[p->id] = val->port_vlan;
1445
1446 /* make sure that an untagged port does not
1447 * appear in other vlans */
1448 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1449 if (j == val->port_vlan)
1450 continue;
1451 priv->vlan_table[j] &= ~(1 << p->id);
1452 }
1453 }
1454
1455 *vt |= 1 << p->id;
1456 }
1457 return 0;
1458 }
1459
1460 static int
1461 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1462 {
1463 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1464 u8 portmask[AR8X16_MAX_PORTS];
1465 int i, j;
1466
1467 mutex_lock(&priv->reg_mutex);
1468 /* flush all vlan translation unit entries */
1469 priv->chip->vtu_flush(priv);
1470
1471 memset(portmask, 0, sizeof(portmask));
1472 if (!priv->init) {
1473 /* calculate the port destination masks and load vlans
1474 * into the vlan translation unit */
1475 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1476 u8 vp = priv->vlan_table[j];
1477
1478 if (!vp)
1479 continue;
1480
1481 for (i = 0; i < dev->ports; i++) {
1482 u8 mask = (1 << i);
1483 if (vp & mask)
1484 portmask[i] |= vp & ~mask;
1485 }
1486
1487 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
1488 priv->vlan_table[j]);
1489 }
1490 } else {
1491 /* vlan disabled:
1492 * isolate all ports, but connect them to the cpu port */
1493 for (i = 0; i < dev->ports; i++) {
1494 if (i == AR8216_PORT_CPU)
1495 continue;
1496
1497 portmask[i] = 1 << AR8216_PORT_CPU;
1498 portmask[AR8216_PORT_CPU] |= (1 << i);
1499 }
1500 }
1501
1502 /* update the port destination mask registers and tag settings */
1503 for (i = 0; i < dev->ports; i++) {
1504 int egress, ingress;
1505 int pvid;
1506
1507 if (priv->vlan) {
1508 pvid = priv->vlan_id[priv->pvid[i]];
1509 if (priv->vlan_tagged & (1 << i))
1510 egress = AR8216_OUT_ADD_VLAN;
1511 else
1512 egress = AR8216_OUT_STRIP_VLAN;
1513 ingress = AR8216_IN_SECURE;
1514 } else {
1515 pvid = i;
1516 egress = AR8216_OUT_KEEP;
1517 ingress = AR8216_IN_PORT_ONLY;
1518 }
1519
1520 priv->chip->setup_port(priv, i, egress, ingress, portmask[i],
1521 pvid);
1522 }
1523 mutex_unlock(&priv->reg_mutex);
1524 return 0;
1525 }
1526
1527 static int
1528 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1529 {
1530 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1531 int i;
1532
1533 mutex_lock(&priv->reg_mutex);
1534 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1535 offsetof(struct ar8xxx_priv, vlan));
1536
1537 for (i = 0; i < AR8X16_MAX_VLANS; i++)
1538 priv->vlan_id[i] = i;
1539
1540 /* Configure all ports */
1541 for (i = 0; i < dev->ports; i++)
1542 priv->chip->init_port(priv, i);
1543
1544 priv->chip->init_globals(priv);
1545 mutex_unlock(&priv->reg_mutex);
1546
1547 return ar8xxx_sw_hw_apply(dev);
1548 }
1549
1550 static int
1551 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1552 const struct switch_attr *attr,
1553 struct switch_val *val)
1554 {
1555 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1556 unsigned int len;
1557 int ret;
1558
1559 if (!ar8xxx_has_mib_counters(priv))
1560 return -EOPNOTSUPP;
1561
1562 mutex_lock(&priv->mib_lock);
1563
1564 len = priv->dev.ports * priv->chip->num_mibs *
1565 sizeof(*priv->mib_stats);
1566 memset(priv->mib_stats, '\0', len);
1567 ret = ar8xxx_mib_flush(priv);
1568 if (ret)
1569 goto unlock;
1570
1571 ret = 0;
1572
1573 unlock:
1574 mutex_unlock(&priv->mib_lock);
1575 return ret;
1576 }
1577
1578 static int
1579 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1580 const struct switch_attr *attr,
1581 struct switch_val *val)
1582 {
1583 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1584 int port;
1585 int ret;
1586
1587 if (!ar8xxx_has_mib_counters(priv))
1588 return -EOPNOTSUPP;
1589
1590 port = val->port_vlan;
1591 if (port >= dev->ports)
1592 return -EINVAL;
1593
1594 mutex_lock(&priv->mib_lock);
1595 ret = ar8xxx_mib_capture(priv);
1596 if (ret)
1597 goto unlock;
1598
1599 ar8xxx_mib_fetch_port_stat(priv, port, true);
1600
1601 ret = 0;
1602
1603 unlock:
1604 mutex_unlock(&priv->mib_lock);
1605 return ret;
1606 }
1607
1608 static int
1609 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1610 const struct switch_attr *attr,
1611 struct switch_val *val)
1612 {
1613 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1614 const struct ar8xxx_chip *chip = priv->chip;
1615 u64 *mib_stats;
1616 int port;
1617 int ret;
1618 char *buf = priv->buf;
1619 int i, len = 0;
1620
1621 if (!ar8xxx_has_mib_counters(priv))
1622 return -EOPNOTSUPP;
1623
1624 port = val->port_vlan;
1625 if (port >= dev->ports)
1626 return -EINVAL;
1627
1628 mutex_lock(&priv->mib_lock);
1629 ret = ar8xxx_mib_capture(priv);
1630 if (ret)
1631 goto unlock;
1632
1633 ar8xxx_mib_fetch_port_stat(priv, port, false);
1634
1635 len += snprintf(buf + len, sizeof(priv->buf) - len,
1636 "Port %d MIB counters\n",
1637 port);
1638
1639 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1640 for (i = 0; i < chip->num_mibs; i++)
1641 len += snprintf(buf + len, sizeof(priv->buf) - len,
1642 "%-12s: %llu\n",
1643 chip->mib_decs[i].name,
1644 mib_stats[i]);
1645
1646 val->value.s = buf;
1647 val->len = len;
1648
1649 ret = 0;
1650
1651 unlock:
1652 mutex_unlock(&priv->mib_lock);
1653 return ret;
1654 }
1655
1656 static struct switch_attr ar8xxx_sw_attr_globals[] = {
1657 {
1658 .type = SWITCH_TYPE_INT,
1659 .name = "enable_vlan",
1660 .description = "Enable VLAN mode",
1661 .set = ar8xxx_sw_set_vlan,
1662 .get = ar8xxx_sw_get_vlan,
1663 .max = 1
1664 },
1665 {
1666 .type = SWITCH_TYPE_NOVAL,
1667 .name = "reset_mibs",
1668 .description = "Reset all MIB counters",
1669 .set = ar8xxx_sw_set_reset_mibs,
1670 },
1671
1672 };
1673
1674 static struct switch_attr ar8xxx_sw_attr_port[] = {
1675 {
1676 .type = SWITCH_TYPE_NOVAL,
1677 .name = "reset_mib",
1678 .description = "Reset single port MIB counters",
1679 .set = ar8xxx_sw_set_port_reset_mib,
1680 },
1681 {
1682 .type = SWITCH_TYPE_STRING,
1683 .name = "mib",
1684 .description = "Get port's MIB counters",
1685 .set = NULL,
1686 .get = ar8xxx_sw_get_port_mib,
1687 },
1688 };
1689
1690 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
1691 {
1692 .type = SWITCH_TYPE_INT,
1693 .name = "vid",
1694 .description = "VLAN ID (0-4094)",
1695 .set = ar8xxx_sw_set_vid,
1696 .get = ar8xxx_sw_get_vid,
1697 .max = 4094,
1698 },
1699 };
1700
1701 static const struct switch_dev_ops ar8xxx_sw_ops = {
1702 .attr_global = {
1703 .attr = ar8xxx_sw_attr_globals,
1704 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
1705 },
1706 .attr_port = {
1707 .attr = ar8xxx_sw_attr_port,
1708 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
1709 },
1710 .attr_vlan = {
1711 .attr = ar8xxx_sw_attr_vlan,
1712 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
1713 },
1714 .get_port_pvid = ar8xxx_sw_get_pvid,
1715 .set_port_pvid = ar8xxx_sw_set_pvid,
1716 .get_vlan_ports = ar8xxx_sw_get_ports,
1717 .set_vlan_ports = ar8xxx_sw_set_ports,
1718 .apply_config = ar8xxx_sw_hw_apply,
1719 .reset_switch = ar8xxx_sw_reset_switch,
1720 .get_port_link = ar8xxx_sw_get_port_link,
1721 };
1722
1723 static int
1724 ar8xxx_id_chip(struct ar8xxx_priv *priv)
1725 {
1726 u32 val;
1727 u16 id;
1728 int i;
1729
1730 val = priv->read(priv, AR8216_REG_CTRL);
1731 if (val == ~0)
1732 return -ENODEV;
1733
1734 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1735 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
1736 u16 t;
1737
1738 val = priv->read(priv, AR8216_REG_CTRL);
1739 if (val == ~0)
1740 return -ENODEV;
1741
1742 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
1743 if (t != id)
1744 return -ENODEV;
1745 }
1746
1747 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
1748 priv->chip_rev = (id & AR8216_CTRL_REVISION);
1749
1750 switch (priv->chip_ver) {
1751 case AR8XXX_VER_AR8216:
1752 priv->chip = &ar8216_chip;
1753 break;
1754 case AR8XXX_VER_AR8236:
1755 priv->chip = &ar8236_chip;
1756 break;
1757 case AR8XXX_VER_AR8316:
1758 priv->chip = &ar8316_chip;
1759 break;
1760 case AR8XXX_VER_AR8327:
1761 priv->mii_lo_first = true;
1762 priv->chip = &ar8327_chip;
1763 break;
1764 default:
1765 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
1766 priv->chip_ver, priv->chip_rev);
1767
1768 return -ENODEV;
1769 }
1770
1771 return 0;
1772 }
1773
1774 static void
1775 ar8xxx_mib_work_func(struct work_struct *work)
1776 {
1777 struct ar8xxx_priv *priv;
1778 int err;
1779
1780 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
1781
1782 mutex_lock(&priv->mib_lock);
1783
1784 err = ar8xxx_mib_capture(priv);
1785 if (err)
1786 goto next_port;
1787
1788 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
1789
1790 next_port:
1791 priv->mib_next_port++;
1792 if (priv->mib_next_port >= priv->dev.ports)
1793 priv->mib_next_port = 0;
1794
1795 mutex_unlock(&priv->mib_lock);
1796 schedule_delayed_work(&priv->mib_work,
1797 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1798 }
1799
1800 static int
1801 ar8xxx_mib_init(struct ar8xxx_priv *priv)
1802 {
1803 unsigned int len;
1804
1805 if (!ar8xxx_has_mib_counters(priv))
1806 return 0;
1807
1808 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
1809
1810 len = priv->dev.ports * priv->chip->num_mibs *
1811 sizeof(*priv->mib_stats);
1812 priv->mib_stats = kzalloc(len, GFP_KERNEL);
1813
1814 if (!priv->mib_stats)
1815 return -ENOMEM;
1816
1817 return 0;
1818 }
1819
1820 static void
1821 ar8xxx_mib_start(struct ar8xxx_priv *priv)
1822 {
1823 if (!ar8xxx_has_mib_counters(priv))
1824 return;
1825
1826 schedule_delayed_work(&priv->mib_work,
1827 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
1828 }
1829
1830 static void
1831 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
1832 {
1833 if (!ar8xxx_has_mib_counters(priv))
1834 return;
1835
1836 cancel_delayed_work(&priv->mib_work);
1837 }
1838
1839 static struct ar8xxx_priv *
1840 ar8xxx_create(void)
1841 {
1842 struct ar8xxx_priv *priv;
1843
1844 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
1845 if (priv == NULL)
1846 return NULL;
1847
1848 mutex_init(&priv->reg_mutex);
1849 mutex_init(&priv->mib_lock);
1850 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
1851
1852 return priv;
1853 }
1854
1855 static void
1856 ar8xxx_free(struct ar8xxx_priv *priv)
1857 {
1858 kfree(priv->mib_stats);
1859 kfree(priv);
1860 }
1861
1862 static struct ar8xxx_priv *
1863 ar8xxx_create_mii(struct mii_bus *bus)
1864 {
1865 struct ar8xxx_priv *priv;
1866
1867 priv = ar8xxx_create();
1868 if (priv) {
1869 priv->mii_bus = bus;
1870 priv->read = ar8xxx_mii_read;
1871 priv->write = ar8xxx_mii_write;
1872 }
1873
1874 return priv;
1875 }
1876
1877 static int
1878 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
1879 {
1880 struct switch_dev *swdev;
1881 int ret;
1882
1883 ret = ar8xxx_id_chip(priv);
1884 if (ret)
1885 return ret;
1886
1887 swdev = &priv->dev;
1888 swdev->cpu_port = AR8216_PORT_CPU;
1889 swdev->ops = &ar8xxx_sw_ops;
1890
1891 if (chip_is_ar8316(priv)) {
1892 swdev->name = "Atheros AR8316";
1893 swdev->vlans = AR8X16_MAX_VLANS;
1894 swdev->ports = AR8216_NUM_PORTS;
1895 } else if (chip_is_ar8236(priv)) {
1896 swdev->name = "Atheros AR8236";
1897 swdev->vlans = AR8216_NUM_VLANS;
1898 swdev->ports = AR8216_NUM_PORTS;
1899 } else if (chip_is_ar8327(priv)) {
1900 swdev->name = "Atheros AR8327";
1901 swdev->vlans = AR8X16_MAX_VLANS;
1902 swdev->ports = AR8327_NUM_PORTS;
1903 } else {
1904 swdev->name = "Atheros AR8216";
1905 swdev->vlans = AR8216_NUM_VLANS;
1906 swdev->ports = AR8216_NUM_PORTS;
1907 }
1908
1909 ret = ar8xxx_mib_init(priv);
1910 if (ret)
1911 return ret;
1912
1913 return 0;
1914 }
1915
1916 static int
1917 ar8xxx_start(struct ar8xxx_priv *priv)
1918 {
1919 int ret;
1920
1921 priv->init = true;
1922
1923 ret = priv->chip->hw_init(priv);
1924 if (ret)
1925 return ret;
1926
1927 ret = ar8xxx_sw_reset_switch(&priv->dev);
1928 if (ret)
1929 return ret;
1930
1931 priv->init = false;
1932
1933 ar8xxx_mib_start(priv);
1934
1935 return 0;
1936 }
1937
1938 static int
1939 ar8xxx_phy_config_init(struct phy_device *phydev)
1940 {
1941 struct ar8xxx_priv *priv = phydev->priv;
1942 struct net_device *dev = phydev->attached_dev;
1943 int ret;
1944
1945 if (WARN_ON(!priv))
1946 return -ENODEV;
1947
1948 if (chip_is_ar8327(priv))
1949 return 0;
1950
1951 priv->phy = phydev;
1952
1953 if (phydev->addr != 0) {
1954 if (chip_is_ar8316(priv)) {
1955 /* switch device has been initialized, reinit */
1956 priv->dev.ports = (AR8216_NUM_PORTS - 1);
1957 priv->initialized = false;
1958 priv->port4_phy = true;
1959 ar8316_hw_init(priv);
1960 return 0;
1961 }
1962
1963 return 0;
1964 }
1965
1966 ret = ar8xxx_start(priv);
1967 if (ret)
1968 return ret;
1969
1970 /* VID fixup only needed on ar8216 */
1971 if (chip_is_ar8216(priv)) {
1972 dev->phy_ptr = priv;
1973 dev->priv_flags |= IFF_NO_IP_ALIGN;
1974 dev->eth_mangle_rx = ar8216_mangle_rx;
1975 dev->eth_mangle_tx = ar8216_mangle_tx;
1976 }
1977
1978 return 0;
1979 }
1980
1981 static int
1982 ar8xxx_phy_read_status(struct phy_device *phydev)
1983 {
1984 struct ar8xxx_priv *priv = phydev->priv;
1985 struct switch_port_link link;
1986 int ret;
1987
1988 if (phydev->addr != 0)
1989 return genphy_read_status(phydev);
1990
1991 ar8216_read_port_link(priv, phydev->addr, &link);
1992 phydev->link = !!link.link;
1993 if (!phydev->link)
1994 return 0;
1995
1996 switch (link.speed) {
1997 case SWITCH_PORT_SPEED_10:
1998 phydev->speed = SPEED_10;
1999 break;
2000 case SWITCH_PORT_SPEED_100:
2001 phydev->speed = SPEED_100;
2002 break;
2003 case SWITCH_PORT_SPEED_1000:
2004 phydev->speed = SPEED_1000;
2005 break;
2006 default:
2007 phydev->speed = 0;
2008 }
2009 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2010
2011 /* flush the address translation unit */
2012 mutex_lock(&priv->reg_mutex);
2013 ret = priv->chip->atu_flush(priv);
2014 mutex_unlock(&priv->reg_mutex);
2015
2016 phydev->state = PHY_RUNNING;
2017 netif_carrier_on(phydev->attached_dev);
2018 phydev->adjust_link(phydev->attached_dev);
2019
2020 return ret;
2021 }
2022
2023 static int
2024 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2025 {
2026 if (phydev->addr == 0)
2027 return 0;
2028
2029 return genphy_config_aneg(phydev);
2030 }
2031
2032 static const u32 ar8xxx_phy_ids[] = {
2033 0x004dd033,
2034 0x004dd041,
2035 0x004dd042,
2036 };
2037
2038 static bool
2039 ar8xxx_phy_match(u32 phy_id)
2040 {
2041 int i;
2042
2043 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2044 if (phy_id == ar8xxx_phy_ids[i])
2045 return true;
2046
2047 return false;
2048 }
2049
2050 static bool
2051 ar8xxx_is_possible(struct mii_bus *bus)
2052 {
2053 unsigned i;
2054
2055 for (i = 0; i < 4; i++) {
2056 u32 phy_id;
2057
2058 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2059 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2060 if (!ar8xxx_phy_match(phy_id)) {
2061 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2062 dev_name(&bus->dev), i, phy_id);
2063 return false;
2064 }
2065 }
2066
2067 return true;
2068 }
2069
2070 static int
2071 ar8xxx_phy_probe(struct phy_device *phydev)
2072 {
2073 struct ar8xxx_priv *priv;
2074 struct switch_dev *swdev;
2075 int ret;
2076
2077 /* skip PHYs at unused adresses */
2078 if (phydev->addr != 0 && phydev->addr != 4)
2079 return -ENODEV;
2080
2081 if (!ar8xxx_is_possible(phydev->bus))
2082 return -ENODEV;
2083
2084 mutex_lock(&ar8xxx_dev_list_lock);
2085 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2086 if (priv->mii_bus == phydev->bus)
2087 goto found;
2088
2089 priv = ar8xxx_create_mii(phydev->bus);
2090 if (priv == NULL) {
2091 ret = -ENOMEM;
2092 goto unlock;
2093 }
2094
2095 ret = ar8xxx_probe_switch(priv);
2096 if (ret)
2097 goto free_priv;
2098
2099 swdev = &priv->dev;
2100 swdev->alias = dev_name(&priv->mii_bus->dev);
2101 ret = register_switch(swdev, NULL);
2102 if (ret)
2103 goto free_priv;
2104
2105 pr_info("%s: %s switch registered on %s\n",
2106 swdev->devname, swdev->name, dev_name(&priv->mii_bus->dev));
2107
2108 found:
2109 priv->use_count++;
2110
2111 if (phydev->addr == 0) {
2112 if (ar8xxx_has_gige(priv)) {
2113 phydev->supported = SUPPORTED_1000baseT_Full;
2114 phydev->advertising = ADVERTISED_1000baseT_Full;
2115 } else {
2116 phydev->supported = SUPPORTED_100baseT_Full;
2117 phydev->advertising = ADVERTISED_100baseT_Full;
2118 }
2119
2120 if (chip_is_ar8327(priv)) {
2121 priv->phy = phydev;
2122
2123 ret = ar8xxx_start(priv);
2124 if (ret)
2125 goto err_unregister_switch;
2126 }
2127 } else {
2128 if (ar8xxx_has_gige(priv)) {
2129 phydev->supported |= SUPPORTED_1000baseT_Full;
2130 phydev->advertising |= ADVERTISED_1000baseT_Full;
2131 }
2132 }
2133
2134 phydev->priv = priv;
2135
2136 list_add(&priv->list, &ar8xxx_dev_list);
2137
2138 mutex_unlock(&ar8xxx_dev_list_lock);
2139
2140 return 0;
2141
2142 err_unregister_switch:
2143 if (--priv->use_count)
2144 goto unlock;
2145
2146 unregister_switch(&priv->dev);
2147
2148 free_priv:
2149 ar8xxx_free(priv);
2150 unlock:
2151 mutex_unlock(&ar8xxx_dev_list_lock);
2152 return ret;
2153 }
2154
2155 static void
2156 ar8xxx_phy_detach(struct phy_device *phydev)
2157 {
2158 struct net_device *dev = phydev->attached_dev;
2159
2160 if (!dev)
2161 return;
2162
2163 dev->phy_ptr = NULL;
2164 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2165 dev->eth_mangle_rx = NULL;
2166 dev->eth_mangle_tx = NULL;
2167 }
2168
2169 static void
2170 ar8xxx_phy_remove(struct phy_device *phydev)
2171 {
2172 struct ar8xxx_priv *priv = phydev->priv;
2173
2174 if (WARN_ON(!priv))
2175 return;
2176
2177 phydev->priv = NULL;
2178 if (--priv->use_count > 0)
2179 return;
2180
2181 mutex_lock(&ar8xxx_dev_list_lock);
2182 list_del(&priv->list);
2183 mutex_unlock(&ar8xxx_dev_list_lock);
2184
2185 unregister_switch(&priv->dev);
2186 ar8xxx_mib_stop(priv);
2187 ar8xxx_free(priv);
2188 }
2189
2190 static struct phy_driver ar8xxx_phy_driver = {
2191 .phy_id = 0x004d0000,
2192 .name = "Atheros AR8216/AR8236/AR8316",
2193 .phy_id_mask = 0xffff0000,
2194 .features = PHY_BASIC_FEATURES,
2195 .probe = ar8xxx_phy_probe,
2196 .remove = ar8xxx_phy_remove,
2197 .detach = ar8xxx_phy_detach,
2198 .config_init = ar8xxx_phy_config_init,
2199 .config_aneg = ar8xxx_phy_config_aneg,
2200 .read_status = ar8xxx_phy_read_status,
2201 .driver = { .owner = THIS_MODULE },
2202 };
2203
2204 int __init
2205 ar8xxx_init(void)
2206 {
2207 return phy_driver_register(&ar8xxx_phy_driver);
2208 }
2209
2210 void __exit
2211 ar8xxx_exit(void)
2212 {
2213 phy_driver_unregister(&ar8xxx_phy_driver);
2214 }
2215
2216 module_init(ar8xxx_init);
2217 module_exit(ar8xxx_exit);
2218 MODULE_LICENSE("GPL");
2219